+// Various macros
+
+#if 0
+#define CLR_Z (regs.cc &= ~FLAG_Z)
+#define CLR_ZN (regs.cc &= ~(FLAG_Z | FLAG_N))
+#define CLR_ZNC (regs.cc &= ~(FLAG_Z | FLAG_N | FLAG_C))
+#define CLR_NVC (regs.cc &= ~(FLAG_N | FLAG_V | FLAG_C))
+#define CLR_VC (regs.cc &= ~(FLAG_V | FLAG_C))
+#define CLR_V (regs.cc &= ~FLAG_V)
+#define CLR_N (regs.cc &= ~FLAG_N)
+#define SET_Z(r) (regs.cc = ((r) == 0 ? regs.cc | FLAG_Z : regs.cc & ~FLAG_Z))
+#define SET_N(r) (regs.cc = ((r) & 0x80 ? regs.cc | FLAG_N : regs.cc & ~FLAG_N))
+#define SET_V(a,b,r) (regs.cc = ((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x80 ? regs.cc | FLAG_V : regs.cc & ~FLAG_V)
+
+//Not sure that this code is computing the carry correctly... Investigate! [Seems to be]
+#define SET_C_ADD(a,b) (regs.cc = ((uint8)(b) > (uint8)(~(a)) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_C_CMP(a,b) (regs.cc = ((uint8)(b) < (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_ZN(r) SET_N(r); SET_Z(r)
+#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
+#define SET_ZNVC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b); SET_V(a,b,r)
+
+#define SET_N16(r) (regs.cc = ((r) & 0x8000 ? regs.cc | FLAG_N : regs.cc & ~FLAG_N))
+#define SET_V16(a,b,r) (regs.cc = ((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x8000 ? regs.cc | FLAG_V : regs.cc & ~FLAG_V)
+#define SET_C_CMP16(a,b) (regs.cc = ((uint16)(b) < (uint16)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_ZNVC_CMP16(a,b,r) SET_N16(r); SET_Z(r); SET_C_CMP16(a,b); SET_V16(a,b,r)
+#else
+#define CLR_Z (flagZ = 0)
+#define CLR_ZN (flagZ = flagN = 0)
+#define CLR_ZNC (flagZ = flagN = flagC = 0)
+#define CLR_NVC (flagN = flagV = flagC = 0)
+#define CLR_VC (flagV = flagC = 0)
+#define CLR_V (flagV = 0)
+#define CLR_N (flagN = 0)
+#define SET_Z(r) (flagZ = ((r) == 0 ? 1 : 0))
+#define SET_N(r) (flagN = ((r) & 0x80) >> 7)
+#define SET_V(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x80) >> 7)
+
+#define SET_C_CMP(a,b) (flagC = ((uint8)(b) < (uint8)(a) ? 1 : 0))
+#define SET_ZN(r) SET_N(r); SET_Z(r)
+#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
+#define SET_ZNVC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b); SET_V(a,b,r)
+
+#define SET_N16(r) (flagN = ((r) & 0x8000) >> 15)
+#define SET_V16(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x8000) >> 15)
+#define SET_C_CMP16(a,b) (flagC = ((uint16)(b) < (uint16)(a) ? 1 : 0))
+#define SET_ZNVC_CMP16(a,b,r) SET_N16(r); SET_Z(r); SET_C_CMP16(a,b); SET_V16(a,b,r)
+#endif
+
+//Small problem with the EA_ macros: ABS macros don't increment the PC!!! !!! FIX !!! [DONE, kinda]
+#define EA_IMM regs.pc++
+#define EA_ZP regs.RdMem(regs.pc++)
+#define EA_ZP_X (regs.RdMem(regs.pc++) + regs.x)
+#define EA_ABS RdMemW(regs.pc)
+
+#define READ_IMM regs.RdMem(EA_IMM)
+#define READ_ZP regs.RdMem(EA_ZP)
+#define READ_ZP_X regs.RdMem(EA_ZP_X)
+#define READ_ABS regs.RdMem(EA_ABS); regs.pc += 2
+
+#define READ_IMM16 RdMemW(regs.pc); regs.pc += 2
+#define READ_ZP16 RdMemW(EA_ZP)
+#define READ_ZP_X16 RdMemW(EA_ZP_X)
+#define READ_ABS16 RdMemW(EA_ABS); regs.pc += 2
+
+#define READ_IMM_WB(v) uint16 addr = EA_IMM; v = regs.RdMem(addr)
+#define READ_ZP_WB(v) uint16 addr = EA_ZP; v = regs.RdMem(addr)
+#define READ_ZP_X_WB(v) uint16 addr = EA_ZP_X; v = regs.RdMem(addr)
+#define READ_ABS_WB(v) uint16 addr = EA_ABS; v = regs.RdMem(addr); regs.pc += 2
+
+#define WRITE_BACK(d) regs.WrMem(addr, (d))
+
+#define PULL regs.RdMem(regs.s++)
+#define PUSH(r) regs.WrMem(--regs.s, (r))
+#define PULL16 RdMemW(regs.s); regs.s += 2
+#define PUSH16(r) regs.WrMem(--regs.s, (r) & 0xFF); regs.WrMem(--regs.s, (r) >> 8)
+
+#define PACK_FLAGS ((regs.cc & 0xC0) | (flagH << 5) | (flagI << 4) | (flagN << 3) | (flagZ << 2) | (flagV << 1) | flagC)
+#define UNPACK_FLAGS flagH = (regs.cc & FLAG_H) >> 5; \
+ flagI = (regs.cc & FLAG_I) >> 4; \
+ flagN = (regs.cc & FLAG_N) >> 3; \
+ flagZ = (regs.cc & FLAG_Z) >> 2; \
+ flagV = (regs.cc & FLAG_V) >> 1; \
+ flagC = (regs.cc & FLAG_C)
+