+//
+// Virtual 6809 v1.3
+//
+// by James L. Hammons
+// (c) 1997, 2006 Underground Software
+//
+// JLH = James L. Hammons <jlhamm@acm.org>
+//
+// WHO WHEN WHAT
+// --- ---------- ------------------------------------------------------------
+// JLH 06/15/2006 Added changelog ;-)
+// JLH 06/15/2006 Scrubbed all BYTE, WORD & DWORD references from the code
+//
+
+// Mebbe someday I'll get around to fixing the core to be more like V65C02...
+//
+
+#include "v6809.h"
+
+#ifdef __DEBUG__
+#include "dis6809.h" // Temporary...
+#include "log.h" // Temporary...
+#endif
+
+// Private global variables
+
+static V6809REGS regs;
+static uint16 addr; // Temporary variables common to all funcs...
+static uint8 tmp;
+
+// Private function prototypes
+
+static int SignedB(uint8); // Return signed byte from unsigned
+static int SignedW(uint16); // Return signed word from unsigned
+static uint16 FetchW(void);
+static uint16 RdMemW(uint16 addr);
+static void WrMemW(uint16 addr, uint16 w);
+static uint16 ReadEXG(uint8); // Read TFR/EXG post byte
+static void WriteEXG(uint8, uint16); // Set TFR/EXG data
+static uint16 DecodeReg(uint8); // Decode register data
+static uint16 DecodeIDX(uint8); // Decode IDX data
+
+//static void (* exec_op1[256])();
+//static void (* exec_op2[256])();
+#if 1
+
+// This is here because of the stupid forward declaration rule that C++ forces (the C++ compiler
+// isn't smart enough to know that the identifiers in the arrays are declared later, it doesn't
+// even *try* to see if they're there).
+
+#define FD(x) static void Op##x(); // FD -> "Forward Declaration"
+#define FE(x) static void Op10##x();
+#define FF(x) static void Op11##x();
+
+FD(00) FD(03) FD(04) FD(06) FD(07) FD(08) FD(09) FD(0A) FD(0C) FD(0D) FD(0E) FD(0F) FD(10) FD(11)
+FD(12) FD(13) FD(16) FD(17) FD(19) FD(1A) FD(1C) FD(1D) FD(1E) FD(1F) FD(20) FD(21) FD(22) FD(23)
+FD(24) FD(25) FD(26) FD(27) FD(28) FD(29) FD(2A) FD(2B) FD(2C) FD(2D) FD(2E) FD(2F) FD(30) FD(31)
+FD(32) FD(33) FD(34) FD(35) FD(36) FD(37) FD(39) FD(3A) FD(3B) FD(3C) FD(3D) FD(3E) FD(3F) FD(40)
+FD(43) FD(44) FD(46) FD(47) FD(48) FD(49) FD(4A) FD(4C) FD(4D) FD(4F) FD(50) FD(53) FD(54) FD(56)
+FD(57) FD(58) FD(59) FD(5A) FD(5C) FD(5D) FD(5F) FD(60) FD(63) FD(64) FD(66) FD(67) FD(68) FD(69)
+FD(6A) FD(6C) FD(6D) FD(6E) FD(6F) FD(70) FD(73) FD(74) FD(76) FD(77) FD(78) FD(79) FD(7A) FD(7C)
+FD(7D) FD(7E) FD(7F) FD(80) FD(81) FD(82) FD(83) FD(84) FD(85) FD(86) FD(88) FD(89) FD(8A) FD(8B)
+FD(8C) FD(8D) FD(8E) FD(90) FD(91) FD(92) FD(93) FD(94) FD(95) FD(96) FD(97) FD(98) FD(99) FD(9A)
+FD(9B) FD(9C) FD(9D) FD(9E) FD(9F) FD(A0) FD(A1) FD(A2) FD(A3) FD(A4) FD(A5) FD(A6) FD(A7) FD(A8)
+FD(A9) FD(AA) FD(AB) FD(AC) FD(AD) FD(AE) FD(AF) FD(B0) FD(B1) FD(B2) FD(B3) FD(B4) FD(B5) FD(B6)
+FD(B7) FD(B8) FD(B9) FD(BA) FD(BB) FD(BC) FD(BD) FD(BE) FD(BF) FD(C0) FD(C1) FD(C2) FD(C3) FD(C4)
+FD(C5) FD(C6) FD(C8) FD(C9) FD(CA) FD(CB) FD(CC) FD(CE) FD(D0) FD(D1) FD(D2) FD(D3) FD(D4) FD(D5)
+FD(D6) FD(D7) FD(D8) FD(D9) FD(DA) FD(DB) FD(DC) FD(DD) FD(DE) FD(DF) FD(E0) FD(E1) FD(E2) FD(E3)
+FD(E4) FD(E5) FD(E6) FD(E7) FD(E8) FD(E9) FD(EA) FD(EB) FD(EC) FD(ED) FD(EE) FD(EF) FD(F0) FD(F1)
+FD(F2) FD(F3) FD(F4) FD(F5) FD(F6) FD(F7) FD(F8) FD(F9) FD(FA) FD(FB) FD(FC) FD(FD) FD(FE) FD(FF)
+FD(__) FD(01)
+
+FE(21) FE(22) FE(23) FE(24) FE(25) FE(26) FE(27) FE(28) FE(29) FE(2A) FE(2B) FE(2C) FE(2D) FE(2E)
+FE(2F) FE(3F) FE(83) FE(8C) FE(8E) FE(93) FE(9C) FE(9E) FE(9F) FE(A3) FE(AC) FE(AE) FE(AF) FE(B3)
+FE(BC) FE(BE) FE(BF) FE(CE) FE(DE) FE(DF) FE(EE) FE(EF) FE(FE) FE(FF)
+
+FF(3F) FF(83) FF(8C) FF(93) FF(9C) FF(A3) FF(AC) FF(B3) FF(BC)
+
+#undef FD
+#undef FE
+#undef FF
+
+#endif
+
+// We can move these down and do away with the forward declarations... !!! FIX !!!
+// Actually, we can't because these are used in a couple of the opcode functions.
+// Have to think about how to fix that...
+
+//
+// Function arrays
+//
+
+// Array of page zero opcode functions...
+static void (* exec_op0[256])() = {
+ Op00, Op01, Op__, Op03, Op04, Op__, Op06, Op07, Op08, Op09, Op0A, Op__, Op0C, Op0D, Op0E, Op0F,
+ Op10, Op11, Op12, Op13, Op__, Op__, Op16, Op17, Op__, Op19, Op1A, Op__, Op1C, Op1D, Op1E, Op1F,
+ Op20, Op21, Op22, Op23, Op24, Op25, Op26, Op27, Op28, Op29, Op2A, Op2B, Op2C, Op2D, Op2E, Op2F,
+ Op30, Op31, Op32, Op33, Op34, Op35, Op36, Op37, Op__, Op39, Op3A, Op3B, Op3C, Op3D, Op3E, Op3F,
+ Op40, Op__, Op__, Op43, Op44, Op__, Op46, Op47, Op48, Op49, Op4A, Op__, Op4C, Op4D, Op__, Op4F,
+ Op50, Op__, Op__, Op53, Op54, Op__, Op56, Op57, Op58, Op59, Op5A, Op__, Op5C, Op5D, Op__, Op5F,
+ Op60, Op__, Op__, Op63, Op64, Op__, Op66, Op67, Op68, Op69, Op6A, Op__, Op6C, Op6D, Op6E, Op6F,
+ Op70, Op__, Op__, Op73, Op74, Op__, Op76, Op77, Op78, Op79, Op7A, Op__, Op7C, Op7D, Op7E, Op7F,
+ Op80, Op81, Op82, Op83, Op84, Op85, Op86, Op__, Op88, Op89, Op8A, Op8B, Op8C, Op8D, Op8E, Op__,
+ Op90, Op91, Op92, Op93, Op94, Op95, Op96, Op97, Op98, Op99, Op9A, Op9B, Op9C, Op9D, Op9E, Op9F,
+ OpA0, OpA1, OpA2, OpA3, OpA4, OpA5, OpA6, OpA7, OpA8, OpA9, OpAA, OpAB, OpAC, OpAD, OpAE, OpAF,
+ OpB0, OpB1, OpB2, OpB3, OpB4, OpB5, OpB6, OpB7, OpB8, OpB9, OpBA, OpBB, OpBC, OpBD, OpBE, OpBF,
+ OpC0, OpC1, OpC2, OpC3, OpC4, OpC5, OpC6, Op__, OpC8, OpC9, OpCA, OpCB, OpCC, Op__, OpCE, Op__,
+ OpD0, OpD1, OpD2, OpD3, OpD4, OpD5, OpD6, OpD7, OpD8, OpD9, OpDA, OpDB, OpDC, OpDD, OpDE, OpDF,
+ OpE0, OpE1, OpE2, OpE3, OpE4, OpE5, OpE6, OpE7, OpE8, OpE9, OpEA, OpEB, OpEC, OpED, OpEE, OpEF,
+ OpF0, OpF1, OpF2, OpF3, OpF4, OpF5, OpF6, OpF7, OpF8, OpF9, OpFA, OpFB, OpFC, OpFD, OpFE, OpFF
+};
+
+// Array of page one opcode functions...
+static void (* exec_op1[256])() = {
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op1021, Op1022, Op1023, Op1024, Op1025, Op1026, Op1027, Op1028, Op1029, Op102A, Op102B, Op102C, Op102D, Op102E, Op102F,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op103F,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op1083, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op108C, Op__, Op108E, Op__,
+ Op__, Op__, Op__, Op1093, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op109C, Op__, Op109E, Op109F,
+ Op__, Op__, Op__, Op10A3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10AC, Op__, Op10AE, Op10AF,
+ Op__, Op__, Op__, Op10B3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10BC, Op__, Op10BE, Op10BF,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10CE, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10DE, Op10DF,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10EE, Op10EF,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10FE, Op10FF
+};
+
+// Array of page two opcode functions...
+static void (* exec_op2[256])() = {
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op113F,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op1183, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op118C, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op1193, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op119C, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op11A3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op11AC, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op11B3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op11BC, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
+ Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__
+};
+
+
+//
+// Fetch a word out of 6809 memory (little endian format)
+// This is a leftover from when fetches were separated from garden variety reads...
+//
+static uint16 FetchW()
+{
+ uint16 w = RdMemW(regs.pc);
+ regs.pc += 2;
+ return w;
+}
+//
+// Fetch word function
+//
+/*uint16 FetchW(void)
+{
+ return (uint16)(regs.RdMem(regs.pc++) << 8) | regs.RdMem(regs.pc++);
+}*/
+
+//
+// Read word from memory function
+//
+uint16 RdMemW(uint16 addr)
+{
+ return (uint16)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
+}
+
+//
+// Write word to memory function
+//
+void WrMemW(uint16 addr, uint16 w)
+{
+ regs.WrMem(addr + 0, w >> 8);
+ regs.WrMem(addr + 1, w & 0xFF);
+}
+
+//
+// return signed byte from unsigned
+//
+int SignedB(uint8 b)
+{
+ return (b & 0x80 ? b - 256 : b);
+}
+
+//
+// return signed word from unsigned
+//
+int SignedW(uint16 w)
+{
+ return (w & 0x8000 ? w - 65536 : w);
+}
+
+//
+// Function to read TFR/EXG post byte
+//
+uint16 ReadEXG(uint8 code)
+{
+ uint16 retval;
+
+ switch (code)
+ {
+ case 0:
+ retval = (regs.a << 8) | regs.b;
+ break;
+ case 1:
+ retval = regs.x;
+ break;
+ case 2:
+ retval = regs.y;
+ break;
+ case 3:
+ retval = regs.u;
+ break;
+ case 4:
+ retval = regs.s;
+ break;
+ case 5:
+ retval = regs.pc;
+ break;
+ case 8:
+ retval = regs.a;
+ break;
+ case 9:
+ retval = regs.b;
+ break;
+ case 10:
+ retval = regs.cc;
+ break;
+ case 11:
+ retval = regs.dp;
+ break;
+ default:
+ retval = 0xFF;
+ }
+
+ return retval;
+}
+
+//
+// Function to set TFR/EXG data
+//
+void WriteEXG(uint8 code, uint16 data)
+{
+ switch (code)
+ {
+ case 0:
+ regs.a = data >> 8, regs.b = data & 0xFF; break;
+ case 1:
+ regs.x = data; break;
+ case 2:
+ regs.y = data; break;
+ case 3:
+ regs.u = data; break;
+ case 4:
+ regs.s = data; break;
+ case 5:
+ regs.pc = data; break;
+ case 8:
+ regs.a = data & 0xFF; break;
+ case 9:
+ regs.b = data & 0xFF; break;
+ case 10:
+ regs.cc = data & 0xFF; break;
+ case 11:
+ regs.dp = data & 0xFF; break;
+ }
+}
+
+//
+// Function to decode register data
+//
+uint16 DecodeReg(uint8 reg)
+{
+ uint16 retval;
+
+ switch (reg)
+ {
+ case 0:
+ retval = regs.x; break;
+ case 1:
+ retval = regs.y; break;
+ case 2:
+ retval = regs.u; break;
+ case 3:
+ retval = regs.s; break;
+ }
+
+ return retval;
+}
+
+//
+// Function to decode IDX data
+//
+uint16 DecodeIDX(uint8 code)
+{
+ uint16 addr, woff;
+ uint8 reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
+
+ if (!(code & 0x80)) // Hi bit unset? Then decode 4 bit offset
+ addr = DecodeReg(reg) + (idxind ? lo_nyb - 16 : lo_nyb);
+ else
+ {
+ if (idxind)
+ {
+ switch (lo_nyb)
+ {
+ case 1:
+ woff = DecodeReg(reg);
+ addr = RdMemW(woff);
+ switch (reg)
+ {
+ case 0: regs.x += 2; break;
+ case 1: regs.y += 2; break;
+ case 2: regs.u += 2; break;
+ case 3: regs.s += 2; break;
+ }
+ break;
+ case 3:
+ switch (reg)
+ {
+ case 0: regs.x -= 2; break;
+ case 1: regs.y -= 2; break;
+ case 2: regs.u -= 2; break;
+ case 3: regs.s -= 2; break;
+ }
+ woff = DecodeReg(reg);
+ addr = RdMemW(woff);
+ break;
+ case 4:
+ woff = DecodeReg(reg);
+ addr = RdMemW(woff);
+ break;
+ case 5:
+ woff = DecodeReg(reg) + SignedB(regs.b);
+ addr = RdMemW(woff);
+ break;
+ case 6:
+ woff = DecodeReg(reg) + SignedB(regs.a);
+ addr = RdMemW(woff);
+ break;
+ case 8:
+ woff = DecodeReg(reg) + SignedB(regs.RdMem(regs.pc++));
+ addr = RdMemW(woff);
+ break;
+ case 9:
+ woff = DecodeReg(reg) + SignedW(FetchW());
+ addr = RdMemW(woff);
+ break;
+ case 11:
+ woff = DecodeReg(reg) + SignedW((regs.a << 8) | regs.b);
+ addr = RdMemW(woff);
+ break;
+ case 12:
+ woff = regs.pc + SignedB(regs.RdMem(regs.pc++));
+ addr = RdMemW(woff);
+ break;
+ case 13:
+ woff = regs.pc + SignedW(FetchW());
+ addr = RdMemW(woff);
+ break;
+ case 15:
+ woff = FetchW();
+ addr = RdMemW(woff);
+ break;
+ }
+ }
+ else
+ {
+ switch (lo_nyb)
+ {
+ case 0:
+ addr = DecodeReg(reg);
+ switch (reg)
+ {
+ case 0: regs.x++; break;
+ case 1: regs.y++; break;
+ case 2: regs.u++; break;
+ case 3: regs.s++; break;
+ }
+ break;
+ case 1:
+ addr = DecodeReg(reg);
+ switch (reg)
+ {
+ case 0: regs.x += 2; break;
+ case 1: regs.y += 2; break;
+ case 2: regs.u += 2; break;
+ case 3: regs.s += 2; break;
+ }
+ break;
+ case 2: { switch(reg)
+ {
+ case 0: regs.x--; break;
+ case 1: regs.y--; break;
+ case 2: regs.u--; break;
+ case 3: regs.s--; break;
+ }
+ addr = DecodeReg(reg); break; }
+ case 3: { switch(reg)
+ {
+ case 0: regs.x--; regs.x--; break;
+ case 1: regs.y--; regs.y--; break;
+ case 2: regs.u--; regs.u--; break;
+ case 3: regs.s--; regs.s--; break;
+ }
+ addr = DecodeReg(reg); break; }
+ case 4: { addr = DecodeReg(reg); break; }
+ case 5: { addr = DecodeReg(reg) + SignedB(regs.b); break; }
+ case 6: { addr = DecodeReg(reg) + SignedB(regs.a); break; }
+ case 8: { addr = DecodeReg(reg) + SignedB(regs.RdMem(regs.pc++)); break; }
+ case 9: { addr = DecodeReg(reg) + SignedW(FetchW()); break; }
+ case 11: { addr = DecodeReg(reg) + SignedW((regs.a << 8) | regs.b); break; }
+ case 12: { addr = regs.pc + SignedB(regs.RdMem(regs.pc++)); break; }
+ case 13: { addr = regs.pc + SignedW(FetchW()); break; }
+ }
+ }
+ }
+
+ return addr;
+}
+
+//
+// Page zero instructions...
+//
+
+static void Op00(void) // NEG DP
+{
+ addr = (regs.dp << 8) | regs.RdMem(regs.pc++);
+ tmp = 256 - regs.RdMem(addr);
+ regs.WrMem(addr, tmp);
+
+ (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp & 0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (tmp > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
+
+ regs.clock += 6;
+}
+
+static void Op01(void) // NEG DP (Undocumented)
+{
+ Op00();
+}
+
+static void Op03(void) // COM DP
+{
+ addr = (regs.dp << 8) | regs.RdMem(regs.pc++);
+ tmp = 0xFF ^ regs.RdMem(addr);
+ regs.WrMem(addr, tmp);
+
+ regs.cc &= 0xFD; regs.cc |= 0x01; // CLV SEC
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+
+ regs.clock += 6;
+}
+
+static void Op04(void) // LSR DP
+{
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
+ tmp = regs.RdMem(addr);
+ (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
+ tmp >>= 1; regs.WrMem(addr, tmp);
+ regs.cc &= 0xF7; // CLN
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ regs.clock += 6;
+}
+static void Op06(void) // ROR DP
+{
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr);
+ tmp = (tmp2>>1) + (regs.cc&0x01)*128;
+ regs.WrMem(addr, tmp);
+ (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op07(void) // ASR DP
+{
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++); tmp = regs.RdMem(addr);
+ (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ tmp >>= 1;
+ if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
+ regs.WrMem(addr, tmp);
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op08(void) // LSL DP
+{
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++); // NEEDS OVERFLOW ADJUSTMENT
+ tmp = regs.RdMem(addr);
+ (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ tmp <<= 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op09(void) // ROL DP
+{
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr);
+ tmp = (tmp2<<1) + (regs.cc&0x01);
+ regs.WrMem(addr, tmp);
+ (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ ((tmp2&0x80)^((tmp2<<1)&0x80) ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op0A(void) // DEC DP
+{
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
+ tmp = regs.RdMem(addr) - 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op0C(void) // INC DP
+{
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
+ tmp = regs.RdMem(addr) + 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op0D(void) // TST DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // CLV
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op0E(void) // JMP DP
+{
+ regs.pc = (regs.dp<<8) | regs.RdMem(regs.pc++);
+ regs.clock += 3;
+}
+static void Op0F(void) // CLR DP
+{
+ regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), 0);
+ regs.cc &= 0xF0; regs.cc |= 0x04; // CLN, SEZ, CLV, CLC
+ regs.clock += 6;
+}
+
+static void Op10(void) // Page 1 opcode
+{
+ exec_op1[regs.RdMem(regs.pc++)]();
+}
+
+static void Op11(void) // Page 2 opcode
+{
+ exec_op2[regs.RdMem(regs.pc++)]();
+}
+
+static void Op12(void) // NOP
+{
+ regs.clock += 2;
+}
+
+static void Op13(void) // SYNC
+{
+ regs.clock += 2;
+}
+static void Op16(void) // LBRA
+{
+ regs.pc += SignedW(FetchW());
+ regs.clock += 5;
+}
+static void Op17(void) // LBSR
+{
+ addr = FetchW();
+ regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
+ regs.pc += SignedW(addr);
+ regs.clock += 9;
+}
+static void Op19(void) // DAA
+{
+ if ((regs.cc&0x20) || ((regs.a&0x0F) > 0x09)) // H set or lo nyb too big?
+ {
+ regs.a += 0x06; regs.cc |= 0x20; // Then adjust & set half carry
+ }
+ if ((regs.cc&0x01) || (regs.a > 0x9F)) // C set or hi nyb too big?
+ {
+ regs.a += 0x60; regs.cc |= 0x01; // Then adjust & set carry
+ }
+ regs.cc &= 0xF1; // CL NZV
+ if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
+ regs.clock += 2;
+}
+
+static void Op1A(void) // ORCC #
+{
+ regs.cc |= regs.RdMem(regs.pc++);
+
+ regs.clock += 3;
+}
+
+static void Op1C(void) // ANDCC #
+{
+ regs.cc &= regs.RdMem(regs.pc++);
+
+ regs.clock += 3;
+}
+
+static void Op1D(void) // SEX
+{
+ (regs.b & 0x80 ? regs.a = 0xFF : regs.a = 0x00);
+
+ ((regs.a | regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a & 0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+
+ regs.clock += 2;
+}
+
+static void Op1E(void) // EXG
+{
+ tmp = regs.RdMem(regs.pc++);
+ addr = ReadEXG(tmp >> 4);
+ WriteEXG(tmp >> 4, ReadEXG(tmp & 0xF));
+ WriteEXG(tmp & 0xF, addr);
+
+ regs.clock += 8;
+}
+
+static void Op1F(void) // TFR
+{
+ tmp = regs.RdMem(regs.pc++);
+ WriteEXG(tmp&0xF, ReadEXG(tmp>>4));
+ regs.clock += 7;
+}
+static void Op20(void) // BRA
+{
+ regs.pc += SignedB(regs.RdMem(regs.pc++)); // Branch always
+ regs.clock += 3;
+}
+static void Op21(void) // BRN
+{
+ regs.RdMem(regs.pc++);
+ regs.clock += 3;
+}
+static void Op22(void) // BHI
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (!(regs.cc&0x05)) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op23(void) // BLS
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (regs.cc&0x05) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op24(void) // BCC (BHS)
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (!(regs.cc&0x01)) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op25(void) // BCS (BLO)
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (regs.cc&0x01) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op26(void) // BNE
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (!(regs.cc&0x04)) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op27(void) // BEQ
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (regs.cc&0x04) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op28(void) // BVC
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (!(regs.cc&0x02)) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op29(void) // BVS
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (regs.cc&0x02) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op2A(void) // BPL
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (!(regs.cc&0x08)) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op2B(void) // BMI
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (regs.cc&0x08) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op2C(void) // BGE
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (!(((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op2D(void) // BLT
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op2E(void) // BGT
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (!((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)))) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op2F(void) // BLE
+{
+ tmp = regs.RdMem(regs.pc++);
+ if ((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedB(tmp);
+ regs.clock += 3;
+}
+static void Op30(void) // LEAX
+{
+ regs.x = DecodeIDX(regs.RdMem(regs.pc++));
+ (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ regs.clock += 4;
+}
+static void Op31(void) // LEAY
+{
+ regs.y = DecodeIDX(regs.RdMem(regs.pc++));
+ (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ regs.clock += 4;
+}
+static void Op32(void) // LEAS
+{
+ regs.s = DecodeIDX(regs.RdMem(regs.pc++));
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ regs.clock += 4;
+}
+static void Op33(void) // LEAU
+{
+ regs.u = DecodeIDX(regs.RdMem(regs.pc++));
+ (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ regs.clock += 4;
+}
+static void Op34(void) // PSHS
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (tmp&0x80) { regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8); }
+ if (tmp&0x40) { regs.WrMem(--regs.s, regs.u&0xFF); regs.WrMem(--regs.s, regs.u>>8); }
+ if (tmp&0x20) { regs.WrMem(--regs.s, regs.y&0xFF); regs.WrMem(--regs.s, regs.y>>8); }
+ if (tmp&0x10) { regs.WrMem(--regs.s, regs.x&0xFF); regs.WrMem(--regs.s, regs.x>>8); }
+ if (tmp&0x08) regs.WrMem(--regs.s, regs.dp);
+ if (tmp&0x04) regs.WrMem(--regs.s, regs.b);
+ if (tmp&0x02) regs.WrMem(--regs.s, regs.a);
+ if (tmp&0x01) regs.WrMem(--regs.s, regs.cc);
+ regs.clock += 5;
+}
+static void Op35(void) // PULS
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (tmp&0x01) regs.cc = regs.RdMem(regs.s++);
+ if (tmp&0x02) regs.a = regs.RdMem(regs.s++);
+ if (tmp&0x04) regs.b = regs.RdMem(regs.s++);
+ if (tmp&0x08) regs.dp = regs.RdMem(regs.s++);
+ if (tmp&0x10) regs.x = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ if (tmp&0x20) regs.y = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ if (tmp&0x40) regs.u = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ if (tmp&0x80) regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ regs.clock += 5;
+}
+
+static void Op36(void) // PSHU
+{
+ tmp = regs.RdMem(regs.pc++);
+
+ if (tmp & 0x80) { regs.WrMem(--regs.u, regs.pc & 0xFF); regs.WrMem(--regs.u, regs.pc >> 8); }
+ if (tmp & 0x40) { regs.WrMem(--regs.u, regs.s & 0xFF); regs.WrMem(--regs.u, regs.s >> 8); }
+ if (tmp & 0x20) { regs.WrMem(--regs.u, regs.y & 0xFF); regs.WrMem(--regs.u, regs.y >> 8); }
+ if (tmp & 0x10) { regs.WrMem(--regs.u, regs.x & 0xFF); regs.WrMem(--regs.u, regs.x >> 8); }
+ if (tmp & 0x08) regs.WrMem(--regs.u, regs.dp);
+ if (tmp & 0x04) regs.WrMem(--regs.u, regs.b);
+ if (tmp & 0x02) regs.WrMem(--regs.u, regs.a);
+ if (tmp & 0x01) regs.WrMem(--regs.u, regs.cc);
+
+ regs.clock += 5;
+}
+
+static void Op37(void) // PULU
+{
+ tmp = regs.RdMem(regs.pc++);
+ if (tmp&0x01) regs.cc = regs.RdMem(regs.u++);
+ if (tmp&0x02) regs.a = regs.RdMem(regs.u++);
+ if (tmp&0x04) regs.b = regs.RdMem(regs.u++);
+ if (tmp&0x08) regs.dp = regs.RdMem(regs.u++);
+ if (tmp&0x10) regs.x = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
+ if (tmp&0x20) regs.y = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
+ if (tmp&0x40) regs.s = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
+ if (tmp&0x80) regs.pc = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++);
+ regs.clock += 5;
+}
+static void Op39(void) // RTS
+{
+ regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ regs.clock += 5;
+}
+static void Op3A(void) // ABX
+{
+ regs.x += regs.b;
+ regs.clock += 3;
+}
+static void Op3B(void) // RTI
+{
+ regs.cc = regs.RdMem(regs.s++);
+ if (regs.cc&0x80) // If E flag set, pull all regs
+ {
+ regs.a = regs.RdMem(regs.s++); regs.b = regs.RdMem(regs.s++); regs.dp = regs.RdMem(regs.s++);
+ regs.x = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ regs.y = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ regs.u = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+ regs.clock += 15;
+ }
+ else
+ {
+ regs.clock += 6;
+ }
+ regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++);
+}
+static void Op3C(void) // CWAI
+{
+ regs.cc &= regs.RdMem(regs.pc++); regs.cc |= 0x80;
+ regs.clock += 1000000; // Force interrupt
+}
+static void Op3D(void) // MUL
+{
+ addr = regs.a * regs.b; regs.a = addr>>8; regs.b = addr&0xFF;
+ (addr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
+ (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
+ regs.clock += 11;
+}
+static void Op3E(void) // RESET
+{
+}
+static void Op3F(void) // SWI
+{
+}
+static void Op40(void) // NEGA
+{
+ regs.a = 256 - regs.a;
+ (regs.a > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
+ (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op43(void) // COMA
+{
+ regs.a ^= 0xFF;
+ regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op44(void) // LSRA
+{
+ (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
+ regs.a >>= 1;
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op46(void) // RORA
+{
+ tmp = regs.a; regs.a = (tmp>>1) + (regs.cc&0x01)*128;
+ (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op47(void) // ASRA
+{
+ (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ regs.a >>= 1; // Do the shift
+ if (regs.a&0x40) regs.a |= 0x80; // Set neg if it was set
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op48(void) // LSLA [Keep checking from here...]
+{
+ (regs.a&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ regs.a <<= 1;
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op49(void) // ROLA
+{
+ tmp = regs.a; regs.a = (tmp<<1) + (regs.cc&0x01);
+ (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op4A(void) // DECA
+{
+ regs.a--;
+ (regs.a == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op4C(void) // INCA
+ {
+ regs.a++;
+ (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op4D(void) // TSTA
+ {
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op4F(void) // CLRA
+{
+ regs.a = 0;
+ regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
+ regs.clock += 2;
+}
+static void Op50(void) // NEGB
+ {
+ regs.b = 256 - regs.b;
+// ((regs.b^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
+ (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.b > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
+ regs.clock += 2;
+ }
+static void Op53(void) // COMB
+ {
+ regs.b ^= 0xFF;
+ regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op54(void) // LSRB
+ {
+ (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
+ regs.b >>= 1;
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op56(void) // RORB
+ {
+ tmp = regs.b; regs.b = (regs.b >> 1) + (regs.cc&0x01)*128;
+ (tmp&0x01 ? regs.cc |=0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op57(void) // ASRB
+ {
+ (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ regs.b >>= 1; // Do the shift
+ if (regs.b&0x40) regs.b |= 0x80; // Set neg if it was set
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op58(void) // LSLB
+ {
+ (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ regs.b <<= 1;
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op59(void) // ROLB
+{
+ tmp = regs.b;
+ regs.b = (tmp<<1) + (regs.cc&0x01);
+ (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op5A(void) // DECB
+ {
+ regs.b--;
+ (regs.b == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op5C(void) // INCB
+ {
+ regs.b++;
+ (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op5D(void) // TSTB
+ {
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op5F(void) // CLRB
+ {
+ regs.b = 0;
+ regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
+ regs.clock += 2;
+ }
+static void Op60(void) // NEG IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
+ regs.WrMem(addr, res);
+// ((res^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
+ (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
+ regs.clock += 6;
+ }
+static void Op63(void) // COM IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr) ^ 0xFF;
+ regs.WrMem(addr, tmp);
+ regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op64(void) // LSR IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr);
+ (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
+ tmp >>= 1; regs.WrMem(addr, tmp);
+ regs.cc &= 0xF7; // CLN
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ regs.clock += 6;
+ }
+static void Op66(void) // ROR IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
+ tmp = (tmp >> 1) + (regs.cc&0x01)*128;
+ regs.WrMem(addr, tmp);
+ (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op67(void) // ASR IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr);
+ (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ tmp >>= 1;
+ if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
+ regs.WrMem(addr, tmp);
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op68(void) // LSL IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr);
+ (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ tmp <<= 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op69(void) // ROL IDX
+{
+ uint8 tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ tmp = (tmp2<<1) + (regs.cc&0x01);
+ regs.WrMem(addr, tmp);
+ (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op6A(void) // DEC IDX
+ {
+ uint8 tmp; uint16 addr;
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr) - 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op6C(void) // INC IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ tmp = regs.RdMem(addr) + 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op6D(void) // TST IDX
+ {
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op6E(void) // JMP IDX
+{
+ regs.pc = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.clock += 3;
+}
+static void Op6F(void) // CLR IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.WrMem(addr, 0);
+ regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
+ regs.clock += 6;
+}
+static void Op70(void) // NEG ABS
+ {
+ addr = FetchW();
+ tmp = regs.RdMem(addr); uint8 res = 256 - tmp;
+ regs.WrMem(addr, res);
+ (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
+ regs.clock += 7;
+ }
+static void Op73(void) // COM ABS
+ {
+ addr = FetchW();
+ tmp = regs.RdMem(addr) ^ 0xFF;
+ regs.WrMem(addr, tmp);
+ regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op74(void) // LSR ABS
+ {
+ addr = FetchW();
+ tmp = regs.RdMem(addr);
+ (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry
+ tmp >>= 1; regs.WrMem(addr, tmp);
+ regs.cc &= 0xF7; // CLN
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ regs.clock += 7;
+ }
+static void Op76(void) // ROR ABS
+ {
+ uint8 tmp; uint16 addr;
+ addr = FetchW();
+ tmp = regs.RdMem(addr); uint8 tmp2 = tmp;
+ tmp = (tmp >> 1) + (regs.cc&0x01)*128;
+ regs.WrMem(addr, tmp);
+ (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op77(void) // ASR ABS
+ {
+ uint8 tmp; uint16 addr;
+ addr = FetchW();
+ tmp = regs.RdMem(addr);
+ (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
+ tmp >>= 1;
+ if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
+ regs.WrMem(addr, tmp);
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op78(void) // LSL ABS
+ {
+ uint8 tmp; uint16 addr;
+ addr = FetchW();
+ tmp = regs.RdMem(addr);
+ (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ tmp <<= 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op79(void) // ROL ABS
+{
+ uint8 tmp2 = regs.RdMem(FetchW());
+ tmp = (tmp2<<1) + (regs.cc&0x01);
+ regs.WrMem(addr, tmp);
+ (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+}
+static void Op7A(void) // DEC ABS
+ {
+ uint8 tmp; uint16 addr;
+ addr = FetchW();
+ tmp = regs.RdMem(addr) - 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op7C(void) // INC ABS
+ {
+ uint8 tmp; uint16 addr;
+ addr = FetchW();
+ tmp = regs.RdMem(addr) + 1;
+ regs.WrMem(addr, tmp);
+ (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+
+static void Op7D(void) // TST ABS
+{
+ uint8 tmp = regs.RdMem(FetchW());
+
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+
+ regs.clock += 7;
+}
+
+static void Op7E(void) // JMP ABS
+{
+ regs.pc = FetchW();
+ regs.clock += 3;
+}
+static void Op7F(void) // CLR ABS
+ {
+ regs.WrMem(FetchW(), 0);
+ regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC
+ regs.clock += 7;
+ }
+static void Op80(void) // SUBA #
+{
+ uint8 tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
+ regs.a -= tmp;
+ (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op81(void) // CMPA #
+{
+ tmp = regs.RdMem(regs.pc++);
+ uint8 db = regs.a - tmp;
+ (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op82(void) // SBCA #
+{
+ tmp = regs.RdMem(regs.pc++); uint8 as = regs.a;
+ regs.a = regs.a - tmp - (regs.cc&0x01);
+ (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void Op83(void) // SUBD #
+{
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+ dr -= addr;
+ (ds < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 4;
+}
+static void Op84(void) // ANDA #
+ {
+ regs.a &= regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op85(void) // BITA #
+ {
+ tmp = regs.a & regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op86(void) // LDA #
+ {
+ regs.a = regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op88(void) // EORA #
+ {
+ regs.a ^= regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op89(void) // ADCA #
+{
+ tmp = regs.RdMem(regs.pc++);
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.a = addr & 0xFF; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
+ regs.clock += 2;
+}
+static void Op8A(void) // ORA #
+ {
+ regs.a |= regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void Op8B(void) // ADDA #
+{
+ tmp = regs.RdMem(regs.pc++); addr = regs.a + tmp;
+ (addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.a = addr & 0xFF; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 2;
+}
+static void Op8C(void) // CMPX #
+{
+ addr = FetchW();
+ uint16 dw = regs.x - addr;
+ (regs.x < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.x^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+}
+static void Op8D(void) // Bregs.s
+ {
+ tmp = regs.RdMem(regs.pc++);
+ regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
+ regs.pc += SignedB(tmp);
+ regs.clock += 7;
+ }
+static void Op8E(void) // LDX #
+ {
+ regs.x = FetchW();
+ regs.cc &= 0xFD; // CLV
+ (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 3;
+ }
+static void Op90(void) // SUBA DP
+ {
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
+ regs.a -= tmp;
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+ }
+static void Op91(void) // CMPA DP
+ {
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ uint8 db = regs.a - tmp;
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+ }
+static void Op92(void) // SBCA DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a;
+ regs.a = regs.a - tmp - (regs.cc&0x01);
+ (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+}
+static void Op93(void) // SUBD DP
+{
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ dr -= adr2;
+ (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 6;
+}
+static void Op94(void) // ANDA DP
+{
+ regs.a &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
+ regs.clock += 4;
+}
+static void Op95(void) // BITA DP
+ {
+ tmp = regs.a & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void Op96(void) // LDA DP
+{
+ regs.a = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xF1; // CLN CLZ CLV
+ if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
+ if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 4;
+}
+static void Op97(void) // STA DP
+ {
+ regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.a);
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void Op98(void) // EORA DP
+ {
+ regs.a ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void Op99(void) // ADCA DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.a = addr & 0xFF; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative
+ regs.clock += 4;
+}
+static void Op9A(void) // ORA DP
+ {
+ regs.a |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void Op9B(void) // ADDA DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ addr = (uint16)regs.a + (uint16)tmp;
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.a = addr & 0xFF; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 4;
+}
+static void Op9C(void) // CMPX DP
+ {
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.x - adr2;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.x < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.x^adr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 6;
+ }
+static void Op9D(void) // JSR DP
+ {
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
+ regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
+ regs.pc = addr; // JSR to DP location...
+ regs.clock += 7;
+ }
+static void Op9E(void) // LDX DP
+ {
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
+ regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void Op9F(void) // STX DP
+ {
+ addr = (regs.dp<<8) | regs.RdMem(regs.pc++);
+ regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void OpA0(void) // SUBA IDX
+ {
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
+ regs.a -= tmp;
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+ }
+static void OpA1(void) // CMPA IDX
+ {
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ uint8 db = regs.a - tmp;
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+ }
+static void OpA2(void) // SBCA IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a;
+ regs.a = regs.a - tmp - (regs.cc&0x01);
+ (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+}
+static void OpA3(void) // SUBD IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++)); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ dr -= adr2;
+ (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 6;
+}
+static void OpA4(void) // ANDA IDX
+ {
+ regs.a &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpA5(void) // BITA IDX
+ {
+ tmp = regs.a & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpA6(void) // LDA IDX
+{
+ regs.a = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
+ if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 4;
+}
+static void OpA7(void) // STA IDX
+{
+ regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.a);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag
+ if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 4;
+}
+static void OpA8(void) // EORA IDX
+ {
+ regs.a ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpA9(void) // ADCA IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.a = addr & 0xFF; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 4;
+}
+static void OpAA(void) // ORA IDX
+{
+ regs.a |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+}
+static void OpAB(void) // ADDA IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ addr = (uint16)regs.a + (uint16)tmp;
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.a = addr & 0xFF; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 4;
+}
+static void OpAC(void) // CMPX IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.x - addr2;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 6;
+}
+static void OpAD(void) // JSR IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
+ regs.pc = addr; // Jregs.s directly to IDX ptr
+ regs.clock += 7;
+}
+static void OpAE(void) // LDX IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpAF(void) // STX IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.x == 0) regs.cc |= 0x04; // Set Zero flag
+ if (regs.x&0x8000) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 5;
+}
+static void OpB0(void) // SUBA ABS
+ {
+ tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
+ regs.a -= tmp;
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 5;
+ }
+static void OpB1(void) // CMPA ABS
+ {
+ tmp = regs.RdMem(FetchW());
+ uint8 db = regs.a - tmp;
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 5;
+ }
+static void OpB2(void) // SBCA ABS
+{
+ tmp = regs.RdMem(FetchW()); uint8 as = regs.a;
+ regs.a = regs.a - tmp - (regs.cc&0x01);
+ (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpB3(void) // SUBD ABS
+{
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ dr -= adr2;
+ (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 7;
+}
+static void OpB4(void) // ANDA ABS
+{
+ regs.a &= regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpB5(void) // BITA ABS
+{
+ tmp = regs.a & regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpB6(void) // LDA ABS
+{
+ regs.a = regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpB7(void) // STA ABS
+{
+ regs.WrMem(FetchW(), regs.a);
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpB8(void) // EORA ABS
+{
+ regs.a ^= regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpB9(void) // ADCA ABS
+{
+ tmp = regs.RdMem(FetchW());
+ addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.a = addr; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 5;
+}
+static void OpBA(void) // ORA ABS
+{
+ regs.a |= regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // CLV
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpBB(void) // ADDA ABS
+{
+ tmp = regs.RdMem(FetchW());
+ addr = (uint16)regs.a + (uint16)tmp;
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.a = addr & 0xFF; // Set accumulator
+ (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 5;
+}
+static void OpBC(void) // CMPX ABS
+{
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.x - addr2;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 7;
+}
+static void OpBD(void) // JSR ABS
+{
+ addr = FetchW();
+ regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8);
+ regs.pc = addr; // Go to absolute address (Not indir)
+ regs.clock += 8;
+}
+
+static void OpBE(void) // LDX ABS
+{
+// addr = FetchW();
+// regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
+ regs.x = RdMemW(FetchW());
+
+ regs.cc &= 0xFD; // CLV
+ (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+
+ regs.clock += 6;
+}
+
+static void OpBF(void) // STX ABS
+{
+// addr = FetchW();
+// regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF);
+ WrMemW(FetchW(), regs.x);
+
+ regs.cc &= 0xFD; // CLV
+ (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+
+ regs.clock += 6;
+}
+
+static void OpC0(void) // SUBB #
+ {
+ tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
+ regs.b -= tmp;
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 2;
+ }
+static void OpC1(void) // CMPB #
+ {
+ tmp = regs.RdMem(regs.pc++);
+ uint8 db = regs.b - tmp;
+ (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void OpC2(void) // SBCB #
+{
+ tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b;
+ regs.b = regs.b - tmp - (regs.cc&0x01);
+ (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+}
+static void OpC3(void) // ADDD #
+{
+ addr = FetchW(); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
+ dr += addr;
+ (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ dr &= 0xFFFF;
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 4;
+}
+static void OpC4(void) // ANDB #
+ {
+ regs.b &= regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void OpC5(void) // BITB #
+{
+ tmp = regs.b & regs.RdMem(regs.pc++);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (tmp == 0) regs.cc |= 0x04; // Set Zero flag
+ if (tmp&0x80) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 2;
+}
+static void OpC6(void) // LDB #
+{
+ regs.b = regs.RdMem(regs.pc++);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.b == 0) regs.cc |= 0x04; // Set Zero flag
+ if (regs.b&0x80) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 2;
+}
+static void OpC8(void) // EORB #
+ {
+ regs.b ^= regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void OpC9(void) // ADCB #
+{
+ tmp = regs.RdMem(regs.pc++);
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.b = addr & 0xFF; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 2;
+}
+static void OpCA(void) // ORB #
+ {
+ regs.b |= regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 2;
+ }
+static void OpCB(void) // ADDB #
+{
+ tmp = regs.RdMem(regs.pc++); addr = regs.b + tmp;
+ (addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.b = addr & 0xFF; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 2;
+}
+static void OpCC(void) // LDD #
+{
+ regs.a = regs.RdMem(regs.pc++); regs.b = regs.RdMem(regs.pc++);
+ regs.cc &= 0xFD; // CLV
+ ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 3;
+}
+static void OpCE(void) // LDU #
+{
+ regs.u = FetchW();
+ regs.cc &= 0xFD; // CLV
+ (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 3;
+}
+static void OpD0(void) // SUBB DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
+ regs.b -= tmp;
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+}
+static void OpD1(void) // CMPB DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ uint8 db = regs.b - tmp;
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+}
+static void OpD2(void) // SBCB DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b;
+ regs.b = regs.b - tmp - (regs.cc&0x01);
+ (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+}
+static void OpD3(void) // ADDD DP
+{
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+ dr += adr2;
+ (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ dr &= 0xFFFF;
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 6;
+}
+static void OpD4(void) // ANDB DP
+ {
+ regs.b &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpD5(void) // BITB DP
+ {
+ tmp = regs.b & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpD6(void) // LDB DP
+{
+ regs.b = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+}
+static void OpD7(void) // STB DP
+ {
+ regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.b);
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpD8(void) // EORB DP
+ {
+ regs.b ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpD9(void) // ADCB DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.b = addr; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 4;
+}
+static void OpDA(void) // ORB DP
+ {
+ regs.b |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpDB(void) // ADDB DP
+{
+ tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
+ addr = (uint16)regs.b + (uint16)tmp;
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.b = addr & 0xFF; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 4;
+}
+static void OpDC(void) // LDD DP
+{
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpDD(void) // STD DP
+{
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
+ regs.cc &= 0xFD; // CLV
+ ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpDE(void) // LDU DP
+{
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpDF(void) // STU DP
+{
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpE0(void) // SUBB IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
+ regs.b -= tmp;
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+}
+static void OpE1(void) // CMPB IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ uint8 db = regs.b - tmp;
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 4;
+}
+static void OpE2(void) // SBCB IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b;
+ regs.b = regs.b - tmp - (regs.cc&0x01);
+ (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+}
+static void OpE3(void) // ADDD IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++)); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+ dr += adr2;
+ (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ dr &= 0xFFFF;
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 6;
+}
+static void OpE4(void) // ANDB IDX
+ {
+ regs.b &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpE5(void) // BITB IDX
+ {
+ tmp = regs.b & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpE6(void) // LDB IDX
+ {
+ regs.b = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpE7(void) // STB IDX
+{
+ regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.b);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.b == 0) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.b&0x80) regs.cc |= 0x08; // Adjust Negative flag
+ regs.clock += 4;
+}
+static void OpE8(void) // EORB IDX
+ {
+ regs.b ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpE9(void) // ADCB IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.b = addr; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 4;
+}
+static void OpEA(void) // ORB IDX
+ {
+ regs.b |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void OpEB(void) // ADDB IDX
+{
+ tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+ addr = (uint16)regs.b + (uint16)tmp;
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.b = addr; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 4;
+}
+static void OpEC(void) // LDD IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpED(void) // STD IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
+ regs.cc &= 0xF1; // CLV CLZ CLZ
+ if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag
+ regs.clock += 5;
+}
+static void OpEE(void) // LDU IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag
+ if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 5;
+}
+static void OpEF(void) // STU IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag
+ if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 5;
+}
+static void OpF0(void) // SUBB ABS
+ {
+ tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
+ regs.b -= tmp;
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ }
+static void OpF1(void) // CMPB ABS
+ {
+ tmp = regs.RdMem(FetchW());
+ uint8 db = regs.b - tmp;
+ (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 5;
+ }
+static void OpF2(void) // SBCB ABS
+{
+ tmp = regs.RdMem(FetchW()); uint8 bs = regs.b;
+ regs.b = regs.b - tmp - (regs.cc&0x01);
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
+ regs.clock += 5;
+}
+static void OpF3(void) // ADDD ABS
+{
+ addr = FetchW(); long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
+ uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+ dr += adr2;
+ (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ dr &= 0xFFFF;
+ (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.a = dr>>8; regs.b = dr&0xFF;
+ regs.clock += 7;
+}
+static void OpF4(void) // ANDB ABS
+ {
+ regs.b &= regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void OpF5(void) // BITB ABS
+ {
+ tmp = regs.b & regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // Clear oVerflow flag
+ (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void OpF6(void) // LDB ABS
+ {
+ regs.b = regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void OpF7(void) // STB ABS
+ {
+ regs.WrMem(FetchW(), regs.b);
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void OpF8(void) // EORB ABS
+ {
+ regs.b ^= regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void OpF9(void) // ADCB ABS
+{
+ tmp = regs.RdMem(FetchW());
+ addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.b = addr & 0xFF; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 5;
+}
+static void OpFA(void) // ORB ABS
+ {
+ regs.b |= regs.RdMem(FetchW());
+ regs.cc &= 0xFD; // CLV
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 5;
+ }
+static void OpFB(void) // ADDB ABS
+{
+ tmp = regs.RdMem(FetchW());
+ addr = (uint16)regs.b + (uint16)tmp;
+ (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
+ ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Set Half carry
+ ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
+ regs.b = addr & 0xFF; // Set accumulator
+ (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Set Zero flag
+ (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Set Negative flag
+ regs.clock += 5;
+}
+static void OpFC(void) // LDD ABS
+ {
+ addr = FetchW();
+ regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void OpFD(void) // STD ABS
+ {
+ addr = FetchW();
+ regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b);
+ regs.cc &= 0xFD; // CLV
+ ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void OpFE(void) // LDU ABS
+ {
+ addr = FetchW();
+ regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void OpFF(void) // STU ABS
+ {
+ addr = FetchW();
+ regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+
+//
+// Page one opcodes' execute code
+//
+
+static void Op1021(void) // LBRN
+{
+ addr = FetchW();
+ regs.clock += 5;
+}
+static void Op1022(void) // LBHI
+{
+ addr = FetchW();
+ if (!((regs.cc&0x01)|(regs.cc&0x04))) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op1023(void) // LBLS
+{
+ addr = FetchW();
+ if ((regs.cc&0x01)|(regs.cc&0x04)) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op1024(void) // LBCC (LBHS)
+{
+ addr = FetchW();
+ if (!(regs.cc&0x01)) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op1025(void) // LBCS (LBLO)
+{
+ addr = FetchW();
+ if (regs.cc&0x01) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op1026(void) // LBNE
+{
+ addr = FetchW();
+ if (!(regs.cc&0x04)) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op1027(void) // LBEQ
+{
+ addr = FetchW();
+ if (regs.cc&0x04) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op1028(void) // LBVC
+{
+ addr = FetchW();
+ if (!(regs.cc&0x02)) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op1029(void) // LBVS
+{
+ addr = FetchW();
+ if (regs.cc&0x02) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op102A(void) // LBPL
+{
+ addr = FetchW();
+ if (!(regs.cc&0x08)) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op102B(void) // LBMI
+{
+ addr = FetchW();
+ if (regs.cc&0x08) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op102C(void) // LBGE
+{
+ addr = FetchW();
+ if (!(((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op102D(void) // LBLT
+{
+ addr = FetchW();
+ if (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op102E(void) // LBGT
+{
+ addr = FetchW();
+ if (!((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)))) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op102F(void) // LBLE
+{
+ addr = FetchW();
+ if ((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedW(addr);
+ regs.clock += 5;
+}
+static void Op103F(void) // SWI2 (Not yet implemented)
+{
+ regs.clock += 20;
+}
+static void Op1083(void) // CMPD #
+ {
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b;
+ uint16 dw = dr - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((dr^addr^dw^((uint16)regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 5;
+ }
+static void Op108C(void) // CMPY #
+ {
+ addr = FetchW();
+ uint16 dw = regs.y - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.y^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 5;
+ }
+static void Op108E(void) // LDY #
+ {
+ regs.y = FetchW();
+ regs.cc &= 0xFD; // CLV
+ (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void Op1093(void) // CMPD DP
+ {
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++), dr = (regs.a<<8)|regs.b;
+ addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
+ uint16 dw = dr - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((dr^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 7;
+ }
+static void Op109C(void) // CMPY DP
+ {
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
+ uint16 dw = regs.y - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ ((regs.y^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 7;
+ }
+
+static void Op109E(void) // LDY DP
+ {
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+
+static void Op109F(void) // STY DP
+ {
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op10A3(void) // CMPD IDX
+{
+ uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++)), dr = (regs.a<<8)|regs.b;
+ addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
+ uint16 dw = dr - addr;
+ regs.cc &= 0xF0; // CLC CLV CLZ CLN
+ if (dr < addr) regs.cc |= 0x01; // Set Carry flag
+ if ((dr^addr^dw^(regs.cc<<15))&0x8000) regs.cc |= 0x02; // Set oVerflow
+ if (dw == 0) regs.cc |= 0x04; // Set Zero flag
+ if (dw&0x8000) regs.cc |= 0x08; // Set Negative flag
+ regs.clock += 7;
+}
+static void Op10AC(void) // CMPY IDX
+ {
+ uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++));
+ addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
+ uint16 dw = regs.y - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.y^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 7;
+ }
+static void Op10AE(void) // LDY IDX
+{
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ regs.cc &= 0xF1; // CLV CLZ CLN
+ if (regs.y == 0) regs.cc |= 0x04; // Adjust Zero flag
+ if (regs.y&0x8000) regs.cc |= 0x08; // Adjust Negative flag
+ regs.clock += 6;
+}
+static void Op10AF(void) // STY IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op10B3(void) // CMPD ABS
+ {
+ addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b;
+ uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = dr - addr2;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (dr < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^dr^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 8;
+ }
+static void Op10BC(void) // CMPY ABS
+ {
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.y - addr2;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.y < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.y^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 8;
+ }
+static void Op10BE(void) // LDY ABS
+ {
+ addr = FetchW();
+ regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op10BF(void) // STY ABS
+ {
+ addr = FetchW();
+ regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op10CE(void) // LDS #
+ {
+ regs.s = FetchW();
+ regs.cc &= 0xFD; // CLV
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 4;
+ }
+static void Op10DE(void) // LDS DP
+ {
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op10DF(void) // STS DP
+ {
+ addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op10EE(void) // LDS IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op10EF(void) // STS IDX
+ {
+ addr = DecodeIDX(regs.RdMem(regs.pc++));
+ regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 6;
+ }
+static void Op10FE(void) // LDS ABS
+ {
+ addr = FetchW();
+ regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ regs.cc &= 0xFD; // CLV
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+ }
+static void Op10FF(void) // STS ABS
+{
+ addr = FetchW();
+ regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF);
+ regs.cc &= 0xFD; // CLV
+ (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ regs.clock += 7;
+}
+
+//
+// Page two opcodes' execute code
+//
+
+static void Op113F(void) // SWI3
+ {
+ regs.clock += 20;
+ }
+static void Op1183(void) // CMPU #
+ {
+ addr = FetchW();
+ uint16 dw = regs.u - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 5;
+ }
+static void Op118C(void) // CMPS #
+ {
+ addr = FetchW();
+ uint16 dw = regs.s - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 5;
+ }
+static void Op1193(void) // CMPU DP
+ {
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
+ uint16 dw = regs.u - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 7;
+ }
+static void Op119C(void) // CMPS DP
+ {
+ uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+ addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
+ uint16 dw = regs.s - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 7;
+ }
+static void Op11A3(void) // CMPU IDX
+ {
+ uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
+ addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
+ uint16 dw = regs.u - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 7;
+ }
+static void Op11AC(void) // CMPS IDX
+ {
+ uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
+ addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
+ uint16 dw = regs.s - addr;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 7;
+ }
+static void Op11B3(void) // CMPU ABS
+ {
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.u - addr2;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.u < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.u^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 8;
+ }
+
+static void Op11BC(void) // CMPS ABS
+{
+ addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+ uint16 dw = regs.s - addr2;
+ (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag
+ (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag
+ (regs.s < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag
+ (((regs.cc<<15)^regs.s^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+ regs.clock += 8;
+}
+
+//temp, for testing...
+/*static uint8 backTrace[256];
+static uint16 btPC[256];
+static int btPtr = 0;//*/
+static void Op__(void) // Illegal opcode
+{
+ regs.clock++;
+// illegal = true;
+ regs.cpuFlags |= V6809_STATE_ILLEGAL_INST;
+/*WriteLog("V6809: Executed illegal opcode %02X at PC=%04X...\n\nBacktrace:\n\n", regs.RdMem(regs.pc - 1), regs.pc - 1);
+for(int i=0; i<256; i++)
+{
+ dpc = btPC[(btPtr+i)&0xFF];
+ Decode_6809();
+}//*/
+}
+
+
+//
+// Internal "memcpy" (so we don't have to link with any external libraries!)
+//
+static void myMemcpy(void * dst, void * src, uint32 size)
+{
+ uint8 * d = (uint8 *)dst, * s = (uint8 *)src;
+
+ for(uint32 i=0; i<size; i++)
+ d[i] = s[i];
+}
+
+//
+// Function to execute 6809 instructions
+//
+void Execute6809(V6809REGS * context, uint32 cycles)
+{
+ myMemcpy(®s, context, sizeof(V6809REGS));
+
+ // Execute here...
+ while (regs.clock < cycles)
+ {
+/*static bool disasm = false;
+if (regs.pc == 0x15BA) disasm = true;
+if (disasm) { dpc = regs.pc; Decode_6809(); }
+if (regs.pc == 0x164A) disasm = false;//*/
+
+//temp, for testing...
+/*backTrace[btPtr] = regs.RdMem(regs.pc);
+btPC[btPtr] = regs.pc;
+btPtr = (btPtr++) & 0xFF;//*/
+ exec_op0[regs.RdMem(regs.pc++)]();
+
+ // Handle any pending interrupts
+
+ uint32 flags = context->cpuFlags;
+
+ if (flags & V6809_ASSERT_LINE_RESET) // *** RESET handler ***
+ {
+ regs.cc |= (FLAG_F | FLAG_I); // Set F, I
+ regs.dp = 0; // Reset direct page register
+ regs.pc = RdMemW(0xFFFE); // And load PC with the RESET vector
+ context->cpuFlags &= ~V6809_ASSERT_LINE_RESET;
+ regs.cpuFlags &= ~V6809_ASSERT_LINE_RESET;
+ }
+ else if (flags & V6809_ASSERT_LINE_NMI) // *** NMI handler ***
+ {
+ regs.cc |= FLAG_E; // Set the Entire flag
+
+ regs.WrMem(--regs.s, regs.pc & 0xFF); // Save all regs...
+ regs.WrMem(--regs.s, regs.pc >> 8);
+ regs.WrMem(--regs.s, regs.u & 0xFF);
+ regs.WrMem(--regs.s, regs.u >> 8);
+ regs.WrMem(--regs.s, regs.y & 0xFF);
+ regs.WrMem(--regs.s, regs.y >> 8);
+ regs.WrMem(--regs.s, regs.x & 0xFF);
+ regs.WrMem(--regs.s, regs.x >> 8);
+ regs.WrMem(--regs.s, regs.dp);
+ regs.WrMem(--regs.s, regs.b);
+ regs.WrMem(--regs.s, regs.a);
+ regs.WrMem(--regs.s, regs.cc);
+
+ regs.cc |= (FLAG_I | FLAG_F); // Set IRQ/FIRQ suppress flags
+ regs.pc = RdMemW(0xFFFC); // And load PC with the NMI vector
+ regs.clock += 19;
+ context->cpuFlags &= ~V6809_ASSERT_LINE_NMI;// Reset the asserted line (NMI)...
+ regs.cpuFlags &= ~V6809_ASSERT_LINE_NMI; // Reset the asserted line (NMI)...
+ }
+ else if (flags & V6809_ASSERT_LINE_FIRQ) // *** FIRQ handler ***
+ {
+ if (!(regs.cc & FLAG_F)) // Is the FIRQ masked (F == 1)?
+ {
+ regs.cc &= ~FLAG_E; // Clear the Entire flag
+
+ regs.WrMem(--regs.s, regs.pc & 0xFF); // Save PC, CC regs...
+ regs.WrMem(--regs.s, regs.pc >> 8);
+ regs.WrMem(--regs.s, regs.cc);
+
+ regs.cc |= (FLAG_I | FLAG_F); // Set IRQ/FIRQ suppress flags
+ regs.pc = RdMemW(0xFFF6); // And load PC with the IRQ vector
+ regs.clock += 10;
+ context->cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
+ regs.cpuFlags &= ~V6809_ASSERT_LINE_FIRQ; // Reset the asserted line (FIRQ)...
+ }
+ }
+ else if (flags & V6809_ASSERT_LINE_IRQ) // *** IRQ handler ***
+ {
+ if (!(regs.cc & FLAG_I)) // Is the IRQ masked (I == 1)?
+ {
+ regs.cc |= FLAG_E; // Set the Entire flag
+
+ regs.WrMem(--regs.s, regs.pc & 0xFF); // Save all regs...
+ regs.WrMem(--regs.s, regs.pc >> 8);
+ regs.WrMem(--regs.s, regs.u & 0xFF);
+ regs.WrMem(--regs.s, regs.u >> 8);
+ regs.WrMem(--regs.s, regs.y & 0xFF);
+ regs.WrMem(--regs.s, regs.y >> 8);
+ regs.WrMem(--regs.s, regs.x & 0xFF);
+ regs.WrMem(--regs.s, regs.x >> 8);
+ regs.WrMem(--regs.s, regs.dp);
+ regs.WrMem(--regs.s, regs.b);
+ regs.WrMem(--regs.s, regs.a);
+ regs.WrMem(--regs.s, regs.cc);
+
+ regs.cc |= FLAG_I; // Specs say that it doesn't affect FIRQ... or FLAG_F [WAS: Set IRQ/FIRQ suppress flags]
+ regs.pc = RdMemW(0xFFF8); // And load PC with the IRQ vector
+ regs.clock += 19;
+ context->cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
+ regs.cpuFlags &= ~V6809_ASSERT_LINE_IRQ; // Reset the asserted line (IRQ)...
+ }
+ }
+/*if (disasm) WriteLog("\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+ regs.a, regs.b, regs.cc, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
+ }
+
+ myMemcpy(context, ®s, sizeof(V6809REGS));
+}
+
+//
+// Get the clock of the currently executing CPU
+//
+uint32 GetCurrentV6809Clock(void)
+{
+ return regs.clock;
+}