--- /dev/null
+a0 136
+a1 137
+a2 138
+
+sp 143
+pc 145
+sr 146
+ccr 147
+
+r0 151
+r1 152
+r2 153
+r3 154
+r4 155
+r5 156
+r6 157
+r7 158
+
+x0 260
+x1 261
+y0 262
+y1 263
+b0 265
+b2 267
+b1 269
+a 270
+b 271
+n0 280
+n1 281
+n2 282
+n3 283
+n4 284
+n5 285
+n6 286
+n7 287
+m0 288
+m1 289
+m2 290
+m3 291
+m4 292
+m5 293
+m6 294
+m7 295
+
+mr 304
+omr 305
+la 306
+lc 307
+ssh 308
+ssl 309
+ss 310
+
+l 302
+p 303
+
+a10 312
+b10 313
+x 314
+y 315
+ab 318
+ba 319
+
#include "sect.h"
#include "token.h"
-#define DEF_KW
-#include "kwtab.h"
+#define DEF_REG65
+#define DECL_REG65
+#include "6502regs.h"
#define UPSEG_SIZE 0x10010L // size of 6502 code buffer, 64K+16bytes
{
SaveSection(); // Save curent section
SwitchSection(M6502); // Switch to 6502 section
+ regbase = reg65base; // Update register DFA tables
+ regtab = reg65tab;
+ regcheck = reg65check;
+ regaccept = reg65accept;
return 0;
}
amode = A65_IMPL;
break;
- case KW_A:
+ case REG65_A:
if (tok[1] != EOL)
goto badmode;
tok++;
amode = A65_INDY;
- if (tok[0] != KW_Y)
+ if (tok[0] != REG65_Y)
goto badmode;
tok++;
else
amode = A65_IND;
}
- else if ((tok[0] == ',') && (tok[1] == KW_X) && (tok[2] == ')'))
+ else if ((tok[0] == ',') && (tok[1] == REG65_X) && (tok[2] == ')'))
{
// (foo,x)
tok += 3;
if ((tok[1] != ')') || (tok[2] != EOL))
goto badmode;
- if (tok[0] == KW_X)
+ if (tok[0] == REG65_X)
amode = A65_INDX;
- else if (tok[0] == KW_Y)
+ else if (tok[0] == REG65_Y)
amode = A65_INDY;
else
goto badmode;
{
tok++;
- if (tok[0] == KW_X)
+ if (tok[0] == REG65_X)
{
tok++;
amode = A65_ABSX;
}
- else if (tok[0] == KW_Y)
+ else if (tok[0] == REG65_Y)
{
tok++;
amode = A65_ABSY;
--- /dev/null
+a 270
+x 314
+y 315
--- /dev/null
+d0 128
+d1 129
+d2 130
+d3 131
+d4 132
+d5 133
+d6 134
+d7 135
+
+a0 136
+a1 137
+a2 138
+a3 139
+a4 140
+a5 141
+a6 142
+a7 143
+
+sp 143
+usp 184
+ssp 144
+pc 145
+sr 146
+ccr 147
+
+ic40 185
+dc40 186
+bc40 187
+
+sfc 188
+dfc 189
+vbr 191
+
+cacr 192
+caar 193
+msp 194
+isp 195
+
+tc 196
+itt0 197
+itt1 198
+dtt0 199
+dtt1 200
+mmusr 201
+psr 201
+urp 202
+srp 203
+
+iacr0 204
+iacr1 205
+dacr0 206
+dacr1 207
+
+tt0 208
+tt1 209
+
+crp 210
+
+fpiar 220
+fpsr 221
+fpcr 222
+
+fp0 224
+fp1 225
+fp2 226
+fp3 227
+fp4 228
+fp5 229
+fp6 230
+fp7 231
+
#include "sect.h"
#include "token.h"
-#define DEF_KW
-#include "kwtab.h"
+#define DEF_REG68
+#include "68kregs.h"
#define DEF_MN
#include "mntab.h"
// TODO: protect this from combinations like Dx:FPx etc :)
tok++; //eat the colon
- if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
a2reg = (*tok++) & 7;
- else if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ else if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
a2reg = (*tok++) & 7;
else
return error("a data or FPU register must follow a :");
for(;;)
{
- if ((*tok >= KW_D0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_A7))
r = *tok++ & 0x0F;
else
break;
{
tok++;
- if ((*tok >= KW_D0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_A7))
cnt = *tok++ & 0x0F;
else
return error("register list syntax");
for(;;)
{
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
r = *tok++ & 0x07;
else
break;
{
tok++;
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
cnt = *tok++ & 0x07;
else
return error("register list syntax");
for(;;)
{
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
r = *tok++ & 0x07;
else
break;
{
tok++;
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
cnt = *tok++ & 0x07;
else
return error("register list syntax");
// Do=0, offset=immediate - shift it to place
bfparam1 = (0 << 11);
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
// Do=1, offset=data register - shift it to place
bfparam1 = (1 << 11);
// Do=0, offset=immediate - shift it to place
bfparam2 = (0 << 5);
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
// Do=1, offset=data register - shift it to place
bfval2 = (*(int *)tok - 128);
#define DEF_KW
#include "kwtab.h"
-
+#define DEF_REG56
+#define DECL_REG56
+#include "56kregs.h"
+#define DEF_REG68
+#define DECL_REG68
+#include "68kregs.h"
+#define DEF_REGRISC
+#define DECL_REGRISC
+#include "riscregs.h"
TOKEN exprbuf[128]; // Expression buffer
SYM * symbolPtr[1000000]; // Symbol pointers table
switch (tok[0])
{
- case KW_X:
+ case REG56_X:
dsp_currentorg->memtype = ORG_X;
sectionToSwitch = M56001X;
break;
- case KW_Y:
+ case REG56_Y:
dsp_currentorg->memtype = ORG_Y;
sectionToSwitch = M56001Y;
break;
- case KW_P:
+ case REG56_P:
dsp_currentorg->memtype = ORG_P;
sectionToSwitch = M56001P;
break;
- case KW_L:
+ case REG56_L:
dsp_currentorg->memtype = ORG_L;
sectionToSwitch = M56001L;
break;
formatting = 1;
// "X" & "L" get tokenized now... :-/ Probably should look into preventing this kind of thing from happening (was added with DSP56K code)
- if ((tok[1] != SYMBOL) && (tok[1] != KW_L) && (tok[1] != KW_X))
+ // Note (ggn): This is now much less severe as it's localised for 56k only
+ if ((tok[1] != SYMBOL) && (tok[1] != REG56_L) && (tok[1] != REG56_X))
goto token_err;
- if (tok[1] == KW_L)
+ if (tok[1] == REG56_L)
{
wordlong = 1;
tok += 2;
}
- else if (tok[1] == KW_X)
+ else if (tok[1] == REG56_X)
{
outtype = 0;
tok += 2;
SaveSection();
SwitchSection(TEXT);
activecpu = CPU_68000;
+ regbase = reg68base; // Update register DFA tables
+ regtab = reg68tab;
+ regcheck = reg68check;
+ regaccept = reg68accept;
return 0;
}
//
int d_68881(void)
{
- //d_68000();
activefpu = FPU_68881;
+ regbase = reg68base; // Update register DFA tables
+ regtab = reg68tab;
+ regcheck = reg68check;
+ regaccept = reg68accept;
return 0;
}
//
int d_68882(void)
{
- //d_68000();
activefpu = FPU_68882;
+ regbase = reg68base; // Update register DFA tables
+ regtab = reg68tab;
+ regcheck = reg68check;
+ regaccept = reg68accept;
return 0;
}
if ((obj_format == LOD) || (obj_format == P56))
SwitchSection(M56001P);
+ regbase = reg56base; // Update register DFA tables
+ regtab = reg56tab;
+ regcheck = reg56check;
+ regaccept = reg56accept;
return 0;
}
rdsp = 0; // Unset DSP assembly
robjproc = 0; // Unset OP assembly
dsp56001 = 0; // Unset 56001 assembly
+
+ regbase = regriscbase; // Update register DFA tables
+ regtab = regrisctab;
+ regcheck = regrisccheck;
+ regaccept = regriscaccept;
return 0;
}
rgpu = 0; // Unset GPU assembly
robjproc = 0; // Unset OP assembly
dsp56001 = 0; // Unset 56001 assembly
+
+ regbase = regriscbase; // Update register DFA tables
+ regtab = regrisctab;
+ regcheck = regrisccheck;
+ regaccept = regriscaccept;
return 0;
}
eval += 2;
}
- else if (*tok >= KW_D0 && *tok <= KW_A7)
+ else if (*tok >= REG68_D0 && *tok <= REG68_A7)
{
if (reglist(&rlist) < 0)
return 0;
{
switch ((int)*tok)
{
- case KW_USP:
- case KW_SSP:
- case KW_PC:
+ case REG68_USP:
+ case REG68_SSP:
+ case REG68_PC:
eval += 2;
// FALLTHROUGH
- case KW_SR:
- case KW_CCR:
+ case REG68_SR:
+ case REG68_CCR:
eval += 2;
tok++;
break;
tok++;
}
- else if (*tok >= KW_D0 && *tok <= KW_A7)
+ else if (*tok >= REG68_D0 && *tok <= REG68_A7)
{
if (reglist(&rlist) < 0)
return 0;
{
switch ((int)*tok)
{
- case KW_USP:
- case KW_SSP:
- case KW_PC:
+ case REG68_USP:
+ case REG68_SSP:
+ case REG68_PC:
eval += 2;
// FALLTHROUGH
- case KW_SR:
- case KW_CCR:
+ case REG68_SR:
+ case REG68_CCR:
eval += 2;
tok++;
break;
The expression has an undefined value because of a forward reference, or an
undefined or external symbol.
-**unimplemented addressing mode**
-
- You tried to use 68020 "square-bracket" notation for a 68020 addressing mode.
- RMAC does not support 68020 addressing modes.
-
**unimplemented directive**
You have found a directive that didn't appear in the documentation. It doesn't
#include "sect.h"
#include "math.h"
-#define DEF_KW
-#include "kwtab.h"
#define DEF_MN
#include "mntab.h"
+#define DEF_REG56
+#include "56kregs.h"
// Address-mode information
int dsp_am0; // Addressing mode
//
static inline int dsp_parmode(int *am, int *areg, TOKEN * AnEXPR, uint64_t * AnEXVAL, WORD * AnEXATTR, SYM ** AnESYM, LONG *memspace, LONG *perspace, const int operand)
{
- if (*tok == KW_A || *tok == KW_B)
+ if (*tok == REG56_A || *tok == REG56_B)
{
*am = M_ACC56;
*areg = *tok++;
return OK;
}
- else if (*tok >= KW_X0 && *tok <= KW_Y1)
+ else if (*tok >= REG56_X0 && *tok <= REG56_Y1)
{
*am = M_ALU24;
*areg = *tok++;
return OK;
}
- else if (*tok == KW_X && *(tok + 1) == ':')
+ else if (*tok == REG56_X && *(tok + 1) == ':')
{
tok = tok + 2;
else
return ERROR;
}
- else if (*tok == KW_Y && *(tok + 1) == ':')
+ else if (*tok == REG56_Y && *(tok + 1) == ':')
{
tok = tok + 2;
return ERROR;
// TODO: add absolute address checks
}
- else if ((*tok >= KW_X) && (*tok <= KW_Y))
+ else if ((*tok >= REG56_X) && (*tok <= REG56_Y))
{
*am = M_INP48;
*areg = *tok++;
return OK;
}
- else if ((*tok >= KW_M0) && (*tok <= KW_M7))
+ else if ((*tok >= REG56_M0) && (*tok <= REG56_M7))
{
*am = M_DSPM;
*areg = (*tok++) & 7;
return OK;
}
- else if ((*tok >= KW_R0) && (*tok <= KW_R7))
+ else if ((*tok >= REG56_R0) && (*tok <= REG56_R7))
{
*am = M_DSPR;
- *areg = (*tok++) - KW_R0;
+ *areg = (*tok++) - REG56_R0;
return OK;
}
- else if ((*tok >= KW_N0) && (*tok <= KW_N7))
+ else if ((*tok >= REG56_N0) && (*tok <= REG56_N7))
{
*am = M_DSPN;
*areg = (*tok++) & 7;
return OK;
}
- else if ((*tok == KW_A0) || (*tok == KW_A1) || (*tok == KW_B0)
- || (*tok == KW_B1))
+ else if ((*tok == REG56_A0) || (*tok == REG56_A1) || (*tok == REG56_B0)
+ || (*tok == REG56_B1))
{
*am = M_ACC24;
*areg = *tok++;
return OK;
}
- else if ((*tok == KW_A2) || (*tok == KW_B2))
+ else if ((*tok == REG56_A2) || (*tok == REG56_B2))
{
*am = M_ACC8;
*areg = *tok++;
return OK;
}
- else if ((*tok == '-') && (*(tok + 1) == KW_X0 || *(tok + 1) == KW_X1 || *(tok + 1) == KW_Y0 || *(tok + 1) == KW_Y1))
+ else if ((*tok == '-') && (*(tok + 1) == REG56_X0 || *(tok + 1) == REG56_X1 || *(tok + 1) == REG56_Y0 || *(tok + 1) == REG56_Y1))
{
// '-X0', '-Y0', '-X1' or '-Y1', used in multiplications
tok++;
dsp_k = 1 << 2;
return OK;
}
- else if (*tok == '+' && (*(tok + 1) == KW_X0 || *(tok + 1) == KW_X1 || *(tok + 1) == KW_Y0 || *(tok + 1) == KW_Y1))
+ else if (*tok == '+' && (*(tok + 1) == REG56_X0 || *(tok + 1) == REG56_X1 || *(tok + 1) == REG56_Y0 || *(tok + 1) == REG56_Y1))
{
// '+X0', '+Y0', '+X1' or '+Y1', used in multiplications
tok++;
// TODO: add absolute address checks
return error("internal assembler error: parmode checking for '(' and '-' does not have absolute address checks yet!");
}
- else if (*tok == KW_P && *(tok + 1) == ':')
+ else if (*tok == REG56_P && *(tok + 1) == ':')
{
tok = tok + 2;
*areg = DSP_EA_ABS;
return OK;
}
- else if (*tok == KW_PC || *tok == KW_CCR || *tok == KW_SR || *tok == KW_SP || (*tok >= KW_MR&&*tok <= KW_SS))
+ else if (*tok == REG56_PC || *tok == REG56_CCR || *tok == REG56_SR || *tok == REG56_SP || (*tok >= REG56_MR&&*tok <= REG56_SS))
{
*areg = *tok++;
*am = M_DSPPCU;
//
static inline int SDreg(int reg)
{
- if (reg >= KW_X0 && reg <= KW_N7)
+ if (reg >= REG56_X0 && reg <= REG56_N7)
return reg & 0xFF;
- else if (reg >= KW_A0&® <= KW_A2)
+ else if (reg >= REG56_A0&® <= REG56_A2)
return (8 >> (reg & 7)) | 8;
- else //if (reg>=KW_R0&®<=KW_R7)
- return reg - KW_R0 + 16;
+ else //if (reg>=REG56_R0&®<=REG56_R7)
+ return reg - REG56_R0 + 16;
// Handy map for the above:
// (values are of course taken from keytab)
// Register | Value | Return value
// Check for D1
switch (K_D1 = *tok++)
{
- case KW_X0: D1 = 0 << 10; break;
- case KW_X1: D1 = 1 << 10; break;
- case KW_A: D1 = 2 << 10; break;
- case KW_B: D1 = 3 << 10; break;
+ case REG56_X0: D1 = 0 << 10; break;
+ case REG56_X1: D1 = 1 << 10; break;
+ case REG56_A: D1 = 2 << 10; break;
+ case REG56_B: D1 = 3 << 10; break;
default: return error("unrecognised X:Y: parallel move syntax: expected x0, x1, a or b after 'X:eax,'");
}
}
}
}
- if (*tok == KW_Y)
+ if (*tok == REG56_Y)
{
tok++;
// 'X:eax,D1 Y:eay,D2' 'S1,X:eax Y:eay,D2'
if (*tok++ == '(')
{
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
- ea2 = (*tok++ - KW_R0);
+ ea2 = (*tok++ - REG56_R0);
if (((ea1 & 7) < 4 && ea2 < 4) || ((ea1 & 7) >= 4 && ea2 > 4))
return error("unrecognised X:Y: parallel move syntax: eax and eay register banks must be different in 'X:ea,D1/S1,X:ea Y:eay,D2'");
ea2 = 3 << 12;
tok++;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea2)
switch (K_D2 = *tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
- case KW_A: D2 = 2 << 8; break;
- case KW_B: D2 = 3 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
+ case REG56_A: D2 = 2 << 8; break;
+ case REG56_B: D2 = 3 << 8; break;
default: return error("unrecognised X:Y: parallel move syntax: expected y0, y1, a or b after 'X:ea,D1/S1,X:ea Y:eay,'");
}
else
return error("unrecognised X:Y: parallel move syntax: expected '(Rn)', '(Rn)+', '(Rn)-', '(Rn)+Nn' after 'X:ea,D1/S1,X:ea Y:'");
}
- else if (*tok == KW_Y0 || *tok == KW_Y1 || *tok == KW_A || *tok == KW_B)
+ else if (*tok == REG56_Y0 || *tok == REG56_Y1 || *tok == REG56_A || *tok == REG56_B)
{
// 'X:eax,D1 S2,Y:eay' 'S1,X:eax1 S2,Y:eay'
switch (*tok++)
{
- case KW_Y0: S2 = 0 << 8; break;
- case KW_Y1: S2 = 1 << 8; break;
- case KW_A: S2 = 2 << 8; break;
- case KW_B: S2 = 3 << 8; break;
+ case REG56_Y0: S2 = 0 << 8; break;
+ case REG56_Y1: S2 = 1 << 8; break;
+ case REG56_A: S2 = 2 << 8; break;
+ case REG56_B: S2 = 3 << 8; break;
default: return error("unrecognised X:Y: parallel move syntax: expected y0, y1, a or b after 'X:ea,D1/S1,X:ea Y:eay,'");
}
if (*tok++ != ',')
return error("unrecognised X:Y: parallel move syntax: expected ',' after 'X:ea,D1/S1,X:ea S2'");
- if (*tok++ == KW_Y)
+ if (*tok++ == REG56_Y)
{
// 'X:eax,D1 Y:eay,D2' 'S1,X:eax Y:eay,D2'
if (*tok++ != ':')
if (*tok++ == '(')
{
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
- ea2 = (*tok++ - KW_R0);
+ ea2 = (*tok++ - REG56_R0);
if (((ea1 & 7) < 4 && ea2 < 4) || ((ea1 & 7) >= 4 && ea2 > 4))
return error("unrecognised X:Y: parallel move syntax: eax and eay register banks must be different in 'X:ea,D1/S1,X:ea S2,Y:eay'");
if (*tok == EOL)
// (Rn)+
ea2 = 3 << 12;
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea2)
{
x_checkea_right:
// 'S1,X:ea S2,D2', 'A,X:ea X0,A', 'B,X:ea X0,B', 'S1,X:eax Y:eay,D2', 'S1,X:eax S2,Y:eay'
- if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_A)
+ if (*tok == REG56_X0 && tok[1] == ',' && tok[2] == REG56_A)
{
// 'A,X:ea X0,A'
if (ea1 == DSP_EA_ABS)
inst = 0b0000100000000000 | ea1 | (0 << 8);
return inst;
}
- else if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_B)
+ else if (*tok == REG56_X0 && tok[1] == ',' && tok[2] == REG56_B)
{
// 'B,X:ea X0,B'
if (ea1 == DSP_EA_ABS)
inst = 0b0000100100000000 | ea1 | (1 << 8);
return inst;
}
- else if (*tok == KW_A || *tok == KW_B)
+ else if (*tok == REG56_A || *tok == REG56_B)
{
// 'S1,X:ea S2,D2', 'S1,X:eax S2,Y:eay'
switch (S1)
default: return error("unrecognised X:R parallel move syntax: S1 can only be x0, x1, a or b in 'S1,X:ea S2,D2'");
}
- if (tok[1] == ',' && tok[2] == KW_Y)
+ if (tok[1] == ',' && tok[2] == REG56_Y)
{
// 'S1,X:eax S2,Y:eay'
return check_x_y(ea1, S1);
switch (*tok++)
{
- case KW_A: S2 = 0 << 9; break;
- case KW_B: S2 = 1 << 9; break;
+ case REG56_A: S2 = 0 << 9; break;
+ case REG56_B: S2 = 1 << 9; break;
default: return error("unrecognised X:R parallel move syntax: expected a or b after 'S1,X:eax'");
}
if (*tok++ != ',')
return error("unrecognised X:R parallel move syntax: expected ',' after 'S1,X:eax S2'");
- if (*tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
- if (*tok++ == KW_Y0)
+ if (*tok++ == REG56_Y0)
D2 = 0 << 8;
else
D2 = 1 << 8;
else
return error("unrecognised X:R parallel move syntax: expected y0 or y1 after 'X:eax,D1 S2,'");
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
// 'S1,X:eax Y:eay,D2'
return check_x_y(ea1, S1);
}
- else if (*tok == KW_Y0 || *tok == KW_Y1)
+ else if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
// 'S1,X:eax S2,Y:eay'
return check_x_y(ea1, S1);
// It might be X:aa but we're not 100% sure yet.
// If it is, the only possible syntax here is 'X:aa,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (*tok == ',' && ((*(tok + 1) >= KW_X0 && *(tok + 1) <= KW_N7) || (*(tok + 1) >= KW_R0 && *(tok + 1) <= KW_R7) || (*(tok + 1) >= KW_A0 && *(tok + 1) <= KW_A2)) && *(tok + 2) == EOL)
+ if (*tok == ',' && ((*(tok + 1) >= REG56_X0 && *(tok + 1) <= REG56_N7) || (*(tok + 1) >= REG56_R0 && *(tok + 1) <= REG56_R7) || (*(tok + 1) >= REG56_A0 && *(tok + 1) <= REG56_A2)) && *(tok + 2) == EOL)
{
// Yup, we're good to go - 'X:aa,D' it is
tok++;
if (*tok++ != ',')
return error("unrecognised X: parallel move syntax: expected ',' after 'X:ea'");
- if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))
+ if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2))
{
D1 = SDreg(*tok++);
else
{
// 'X:ea,D1 S2,D2'
- if (*tok == KW_A || *tok == KW_B)
+ if (*tok == REG56_A || *tok == REG56_B)
{
S2 = SDreg(*tok++);
if (*tok++ != ',')
return error("unrecognised X:R parallel move syntax: expected comma after X:ea,D1 S2");
- if (*tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
D2 = SDreg(*tok++);
// It might be 'X:(Rn..)..,D' but we're not 100% sure yet.
// If it is, the only possible syntax here is 'X:ea,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) && *(tok + 1) == EOL)
+ if (((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) && *(tok + 1) == EOL)
{
//'X:ea,D'
D1 = SDreg(*tok++);
// 'X:eax,D1 Y:eay,D2', 'X:eax,D1 S2,Y:eay' or 'X:ea,D1 S2,D2'
// Check ahead for S2,D2 - if that's true then we have 'X:ea,D1 S2,D2'
- if ((*tok == KW_X0 || *tok == KW_X1 || *tok == KW_A || *tok == KW_B) && (*(tok + 1) == KW_A || *(tok + 1) == KW_B) && (*(tok + 2) == ',') && (*(tok + 3) == KW_Y0 || (*(tok + 3) == KW_Y1)))
+ if ((*tok == REG56_X0 || *tok == REG56_X1 || *tok == REG56_A || *tok == REG56_B) && (*(tok + 1) == REG56_A || *(tok + 1) == REG56_B) && (*(tok + 2) == ',') && (*(tok + 3) == REG56_Y0 || (*(tok + 3) == REG56_Y1)))
{
// 'X:ea,D1 S2,D2'
// Check if D1 is x0, x1, a or b
switch (*tok++)
{
- case KW_X0: D1 = 0 << 10; break;
- case KW_X1: D1 = 1 << 10; break;
- case KW_A: D1 = 2 << 10; break;
- case KW_B: D1 = 3 << 10; break;
+ case REG56_X0: D1 = 0 << 10; break;
+ case REG56_X1: D1 = 1 << 10; break;
+ case REG56_A: D1 = 2 << 10; break;
+ case REG56_B: D1 = 3 << 10; break;
default: return error("unrecognised X:R parallel move syntax: expected x0, x1, a or b after 'X:eax,'");
}
switch (*tok++)
{
- case KW_A: S2 = 0 << 9; break;
- case KW_B: S2 = 1 << 9; break;
+ case REG56_A: S2 = 0 << 9; break;
+ case REG56_B: S2 = 1 << 9; break;
default: return error("unrecognised X:R parallel move syntax: expected a or b after 'X:eax,D1 '");
}
if (*tok++ != ',')
return error("unrecognised X:R parallel move syntax: expected ',' after 'X:eax,D1 S2'");
- if (*tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_Y0 || *tok == REG56_Y1)
{
- if (*tok++ == KW_Y0)
+ if (*tok++ == REG56_Y0)
D2 = 0 << 8;
else
D2 = 1 << 8;
return inst;
}
- if (*tok == ',' && ((*(tok + 1) >= KW_X0 && *(tok + 1) <= KW_N7) || (*(tok + 1) >= KW_R0 && *(tok + 1) <= KW_R7) || (*(tok + 1) >= KW_A0 && *(tok + 1) <= KW_A2)) && *(tok + 2) == EOL)
+ if (*tok == ',' && ((*(tok + 1) >= REG56_X0 && *(tok + 1) <= REG56_N7) || (*(tok + 1) >= REG56_R0 && *(tok + 1) <= REG56_R7) || (*(tok + 1) >= REG56_A0 && *(tok + 1) <= REG56_A2)) && *(tok + 2) == EOL)
{
// Yup, we're good to go - 'Y:aa,D' it is
tok++;
if (D1 == 0 && S1 == 0)
{
// 'Y:ea,D'
- if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))
+ if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2))
{
D1 = SDreg(*tok++);
else
{
// 'S1,D1 Y:ea,D2'
- if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1)
+ if (*tok == REG56_A || *tok == REG56_B || *tok == REG56_Y0 || *tok == REG56_Y1)
{
D2 = SDreg(*tok++);
inst |= ea1;
switch (*tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
- case KW_A: D2 = 2 << 8; break;
- case KW_B: D2 = 3 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
+ case REG56_A: D2 = 2 << 8; break;
+ case REG56_B: D2 = 3 << 8; break;
default: return error("unrecognised R:Y parallel move syntax: D2 can only be y0, y1, a or b after 'S1,D1 Y:ea'");
}
// It might be 'Y:(Rn..)..,D' but we're not 100% sure yet.
// If it is, the only possible syntax here is 'Y:ea,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)) && *(tok + 1) == EOL)
+ if (((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)) && *(tok + 1) == EOL)
{
//'Y:ea,D'
D1 = SDreg(*tok++);
if (dspImmedEXVAL < 0x40 && force_imm != NUM_FORCE_LONG)
{
// 'S,L:aa'
- if (S1 == KW_A)
+ if (S1 == REG56_A)
S1 = 4;
- else if (S1 == KW_B)
+ else if (S1 == REG56_B)
S1 = 5;
else
S1 &= 7;
else
{
// 'S,L:ea'
- if (S1 == KW_A)
+ if (S1 == REG56_A)
S1 = 4;
- else if (S1 == KW_B)
+ else if (S1 == REG56_B)
S1 = 5;
else
S1 &= 7;
return error("unrecognised L: parallel move syntax: expected ',' after 'L:ea/L:aa'");
// Check for allowed registers for D (a0, b0, x, y, a, b, ab or ba)
- if (!((*tok >= KW_A10 && *(tok + 1) <= KW_BA) || (*tok >= KW_A && *tok <= KW_B)))
+ if (!((*tok >= REG56_A10 && *(tok + 1) <= REG56_BA) || (*tok >= REG56_A && *tok <= REG56_B)))
return error("unrecognised L: parallel move syntax: expected a0, b0, x, y, a, b, ab or ba after 'L:ea/L:aa'");
if (dspImmedEXVAL < (1 << 6) && (dspImmedEXATTR&DEFINED))
l_aa:
immreg = *tok++;
- if (immreg == KW_A)
+ if (immreg == REG56_A)
immreg = 4;
- else if (immreg == KW_B)
+ else if (immreg == REG56_B)
immreg = 5;
else
immreg &= 7;
// 'L:ea,D'
D1 = *tok++;
- if (D1 == KW_A)
+ if (D1 == REG56_A)
D1 = 4;
- else if (D1 == KW_B)
+ else if (D1 == REG56_B)
D1 = 5;
else
D1 &= 7;
// 'S,L:ea'
inst = 0b0100000001000000;
- if (S1 == KW_A)
+ if (S1 == REG56_A)
S1 = 4;
- else if (S1 == KW_B)
+ else if (S1 == REG56_B)
S1 = 5;
else
S1 &= 7;
// It might be 'L:(Rn..)..,D' but we're not 100% sure yet.
// If it is, the only possible syntax here is 'L:ea,D'.
// So check ahead to see if EOL follows D, then we're good to go.
- if (((*tok >= KW_A10 && *tok <= KW_BA) || (*tok >= KW_A && *tok <= KW_B)) && *(tok + 1) == EOL)
+ if (((*tok >= REG56_A10 && *tok <= REG56_BA) || (*tok >= REG56_A && *tok <= REG56_B)) && *(tok + 1) == EOL)
{
//'L:ea,D'
D1 = *tok++;
- if (D1 == KW_A)
+ if (D1 == REG56_A)
D1 = 4;
- else if (D1 == KW_B)
+ else if (D1 == REG56_B)
D1 = 5;
else
D1 &= 7;
if (*tok++ != '(')
return error(ea_errors[strings][0]);
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
// We got '-(Rn' so mark it down
- ea = DSP_EA_PREDEC1 | (*tok++ - KW_R0);
+ ea = DSP_EA_PREDEC1 | (*tok++ - REG56_R0);
if (*tok++ != ')')
return error(ea_errors[strings][1]);
// Checking for ea of type (Rn)
tok++;
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
// We're in 'X:(Rn..)..,D', 'X:(Rn..)..,D1 Y:eay,D2', 'X:(Rn..)..,D1 S2,Y:eay'
- ea = *tok++ - KW_R0;
+ ea = *tok++ - REG56_R0;
if (*tok == '+')
{
// '(Rn+Nn)'
tok++;
- if (*tok < KW_N0 || *tok > KW_N7)
+ if (*tok < REG56_N0 || *tok > REG56_N7)
return error(ea_errors[strings][3]);
if ((*tok++ & 7) != ea)
ea |= DSP_EA_POSTINC1;
return ea;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea)
}
else
{
- if (*tok >= KW_N0 && *tok <= KW_N7)
+ if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea)
ea |= DSP_EA_POSTDEC1;
return ea;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)-Nn
if ((*tok++ & 7) != ea)
}
else
{
- if (*tok >= KW_N0 && *tok <= KW_N7)
+ if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)-Nn
if ((*tok++ & 7) != ea)
if (*tok++ != ',')
return error("expected comma");
- if (!((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2)))
+ if (!((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2)))
return error("expected x0,x1,y0,y1,a0,b0,a2,b2,a1,b1,a,b,r0-r7,n0-n7 after immediate");
immreg = SDreg(*tok++);
switch (*tok++)
{
- case KW_A: S2 = 0 << 9; break;
- case KW_B: S2 = 1 << 9; break;
+ case REG56_A: S2 = 0 << 9; break;
+ case REG56_B: S2 = 1 << 9; break;
default: return error("unrecognised X:R parallel move syntax: S2 can only be A or B in '#xxxxxx,D1 S2,D2'"); break;
}
switch (*tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
default: return error("unrecognised X:R parallel move syntax: D2 can only be Y0 or Y1 in '#xxxxxx,D1 S2,D2'"); break;
}
return inst;
}
}
- else if (*tok == KW_X)
+ else if (*tok == REG56_X)
{
if (tok[1] == ',')
// Hey look, it's just the register X and not the addressing mode - fall through to general case
// 'X:ea,D' or 'X:aa,D' or 'X:ea,D1 S2,D2' or 'X:eax,D1 Y:eay,D2' or 'X:eax,D1 S2,Y:eay'
return parse_x(1, 0b0100000000000000, 0, 1);
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
if (tok[1] == ',')
// Hey look, it's just the register y and not the addressing mode - fall through to general case
// 'Y:ea,D' or 'Y:aa,D'
return parse_y(0b0100100010000000, 0, 0, 0);
}
- else if (*tok == KW_L)
+ else if (*tok == REG56_L)
{
// 'L:ea,D' or 'L:aa,D'
tok++;
return parse_l(1, 0b0100000011000000, 0);
}
- else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2) || (*tok >= KW_A10 && *tok <= KW_BA))
+ else if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2) || (*tok >= REG56_A10 && *tok <= REG56_BA))
{
// Everything else - brace for impact!
// R: 'S,D'
if (*tok++ != ',')
return error("Comma expected after 'S')");
- if (*tok == KW_X)
+ if (*tok == REG56_X)
{
// 'S,X:ea' 'S,X:aa' 'S,X:ea S2,D2' 'S1,X:eax Y:eay,D2' 'S1,X:eax S2,Y:eay'
// 'A,X:ea X0,A' 'B,X:ea X0,B'
return parse_x(0, 0b0100000000000000, S1, 1);
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
// 'S,Y:ea' 'S,Y:aa'
tok++;
return parse_y(0b000000000000000, S1, 0, 0);
}
- else if (*tok == KW_L)
+ else if (*tok == REG56_L)
{
// 'S,L:ea' 'S,L:aa'
tok++;
return parse_l(1, 0b0000000000000000, L_S1);
}
- else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))
+ else if ((*tok >= REG56_X0 && *tok <= REG56_N7) || (*tok >= REG56_R0 && *tok <= REG56_R7) || (*tok >= REG56_A0 && *tok <= REG56_A2))
{
// 'S,D'
// 'S1,D1 Y:ea,D2' 'S1,D1 S2,Y:ea' 'S1,D1 #xxxxxx,D2'
inst |= (S1 << 5) | (D1);
return inst;
}
- else if (*tok == KW_Y)
+ else if (*tok == REG56_Y)
{
// 'S1,D1 Y:ea,D2'
tok++;
return parse_y(0b0001000001000000, S1, D1, 0);
}
- else if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1)
+ else if (*tok == REG56_A || *tok == REG56_B || *tok == REG56_Y0 || *tok == REG56_Y1)
{
// 'Y0,A A,Y:ea' 'Y0,B B,Y:ea' 'S1,D1 S2,Y:ea'
S2 = SDreg(*tok++);
if (*tok++ != ',')
return error("unrecognised Y: parallel move syntax: expected ',' after Y0,A A");
- if (*tok++ != KW_Y)
+ if (*tok++ != REG56_Y)
return error("unrecognised Y: parallel move syntax: expected 'Y' after Y0,A A,");
if (*tok++ != ':')
if (*tok++ != ',')
return error("unrecognised Y: parallel move syntax: expected ',' after Y0,B B");
- if (*tok++ != KW_Y)
+ if (*tok++ != REG56_Y)
return error("unrecognised Y: parallel move syntax: expected 'Y' after Y0,B B,");
if (*tok++ != ':')
if (*tok++ != ',')
return error("unrecognised Y: parallel move syntax: expected ',' after S1,D1 S2");
- if (*tok++ != KW_Y)
+ if (*tok++ != REG56_Y)
return error("unrecognised Y: parallel move syntax: expected 'Y' after S1,D1 S2,");
if (*tok++ != ':')
// S1 is a or b, D1 is x0 or x1 and d2 is y0, y1, a or b
switch (*tok++)
{
- case KW_Y0: D2 = 0 << 8; break;
- case KW_Y1: D2 = 1 << 8; break;
- case KW_A: D2 = 2 << 8; break;
- case KW_B: D2 = 3 << 8; break;
+ case REG56_Y0: D2 = 0 << 8; break;
+ case REG56_Y1: D2 = 1 << 8; break;
+ case REG56_A: D2 = 2 << 8; break;
+ case REG56_B: D2 = 3 << 8; break;
default: return error("unrecognised R:Y: parallel move syntax: D2 must be y0, y1, a or b in 'S1,D1 #xxxxxx,D2'");
}
// U 'ea' can only be '(Rn)-Nn', '(Rn)+Nn', '(Rn)-' or '(Rn)+'
tok++;
- if (*tok >= KW_R0 && *tok <= KW_R7)
+ if (*tok >= REG56_R0 && *tok <= REG56_R7)
{
- ea1 = (*tok++ - KW_R0);
+ ea1 = (*tok++ - REG56_R0);
}
else
return error("unrecognised U parallel move syntax: expected 'Rn' after '('");
if (*tok == EOL)
// (Rn)+
ea1 |= 3 << 3;
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)+Nn
if ((*tok++ & 7) != ea1)
ea1 |= 2 << 3;
tok++;
}
- else if (*tok >= KW_N0 && *tok <= KW_N7)
+ else if (*tok >= REG56_N0 && *tok <= REG56_N7)
{
// (Rn)-Nn
if ((*tok++ & 7) != ea1)
#include "sect.h"
#include "token.h"
-#define DEF_KW
-#include "kwtab.h"
+#define DEF_REG56
+#include "56kregs.h"
// Globals
switch (dsp_a0reg)
{
- case KW_X: inst |= 2 << 4; break;
- case KW_Y: inst |= 3 << 4; break;
- case KW_X0: inst |= 4 << 4;break;
- case KW_Y0: inst |= 5 << 4;break;
- case KW_X1: inst |= 6 << 4;break;
- case KW_Y1: inst |= 7 << 4;break;
+ case REG56_X: inst |= 2 << 4; break;
+ case REG56_Y: inst |= 3 << 4; break;
+ case REG56_X0: inst |= 4 << 4;break;
+ case REG56_Y0: inst |= 5 << 4;break;
+ case REG56_X1: inst |= 6 << 4;break;
+ case REG56_Y1: inst |= 7 << 4;break;
default: return error("dsp_acc48: shouldn't reach here!");
}
{
switch (dsp_a1reg)
{
- case KW_CCR: inst |= 1; break;
- case KW_MR:inst |= 0; break;
- case KW_OMR:inst |= 2; break;
+ case REG56_CCR: inst |= 1; break;
+ case REG56_MR:inst |= 0; break;
+ case REG56_OMR:inst |= 2; break;
default: return error("invalid destination register (only ccr, mr, omr allowed");
}
case 5:
case 6:
case 7: inst |= dsp_a1reg; break; // M0-M7
- case KW_SR: inst |= 25; break;
- case KW_OMR: inst |= 26; break;
- case KW_SP: inst |= 27; break;
- case KW_SSH: inst |= 28; break;
- case KW_SSL: inst |= 29; break;
- case KW_LA: inst |= 30; break;
- case KW_LC: inst |= 31; break;
+ case REG56_SR: inst |= 25; break;
+ case REG56_OMR: inst |= 26; break;
+ case REG56_SP: inst |= 27; break;
+ case REG56_SSH: inst |= 28; break;
+ case REG56_SSL: inst |= 29; break;
+ case REG56_LA: inst |= 30; break;
+ case REG56_LC: inst |= 31; break;
default: return error("invalid destination register (only m0-m7, SR, OMR, SP, SSH, SSL, LA, LC allowed");
}
case M_ACC56:
case M_ACC24:
case M_ACC8:
- if (*reg == KW_A1)
+ if (*reg == REG56_A1)
return 4;
else
return (*reg & 7);
case M_DSPPCU:
switch (*reg)
{
- case KW_SR: return 1; break;
- case KW_OMR: return 2; break;
- case KW_SP: return 3; break;
- case KW_SSH: return 4; break;
- case KW_SSL: return 5; break;
- case KW_LA: return 6; break;
- case KW_LC: return 7; break;
+ case REG56_SR: return 1; break;
+ case REG56_OMR: return 2; break;
+ case REG56_SP: return 3; break;
+ case REG56_SSH: return 4; break;
+ case REG56_SSL: return 5; break;
+ case REG56_LA: return 6; break;
+ case REG56_LC: return 7; break;
default:
return error("specified control register not allowed as destination");
break;
}
// Abort if unsupported registers are requested
- if (reg == KW_PC || reg == KW_MR || reg == KW_CCR)
+ if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR)
return error("illegal registers for instruction.");
if (dsp_am0 & C_DSPIM)
}
// Abort if unsupported registers are requested
- if (reg == KW_PC || reg == KW_MR || reg == KW_CCR)
+ if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR)
return error("PC, MR, CCR are illegal registers for this instruction.");
if (memspace == -1)
int am1 = dsp_am1;
// Abort if unsupported registers are requested
- if (dsp_a0reg == KW_PC || dsp_a0reg == KW_MR || dsp_a0reg == KW_CCR ||
- dsp_a1reg == KW_PC || dsp_a1reg == KW_MR || dsp_a1reg == KW_CCR)
+ if (dsp_a0reg == REG56_PC || dsp_a0reg == REG56_MR || dsp_a0reg == REG56_CCR ||
+ dsp_a1reg == REG56_PC || dsp_a1reg == REG56_MR || dsp_a1reg == REG56_CCR)
return error("PC, MR, CCR are illegal registers for this instruction.");
int reg1 = tab_A18(&dsp_am0, &dsp_a0reg);
return error("x0/y0/x1/y1 combination not allowed for multiplication.");
}
- if (dsp_a2reg == KW_B)
+ if (dsp_a2reg == REG56_B)
inst |= 1 << 3;
inst |= dsp_k;
}
// Abort if unsupported registers are requested
- if (reg == KW_PC || reg == KW_MR || reg == KW_CCR)
+ if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR)
return error("illegal registers for instruction.");
if (memspace != -1)
}
// Abort if unsupported registers are requested
- if (reg == KW_PC || reg == KW_MR || reg == KW_CCR)
+ if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR)
return error("PC, MR, CCR are illegal registers for this instruction.");
if (memspace != -1)
}
// Abort if unsupported registers are requested
- if (reg == KW_PC || reg == KW_MR || reg == KW_CCR)
+ if (reg == REG56_PC || reg == REG56_MR || reg == REG56_CCR)
return error("illegal registers for instruction.");
reg2 = tab_A18(&am, ®2);
-d0 128
-d1 129
-d2 130
-d3 131
-d4 132
-d5 133
-d6 134
-d7 135
-
-a0 136
-a1 137
-a2 138
-a3 139
-a4 140
-a5 141
-a6 142
-a7 143
-
-sp 143
-usp 184
-ssp 144
-pc 145
-sr 146
-ccr 147
-
-ic40 185
-dc40 186
-bc40 187
-
-sfc 188
-dfc 189
-vbr 191
-
-cacr 192
-caar 193
-msp 194
-isp 195
-
-tc 196
-itt0 197
-itt1 198
-dtt0 199
-dtt1 200
-mmusr 201
-psr 201
-urp 202
-srp 203
-
-iacr0 204
-iacr1 205
-dacr0 206
-dacr1 207
-
-tt0 208
-tt1 209
-
-crp 210
-
-fpiar 220
-fpsr 221
-fpcr 222
-
-fp0 224
-fp1 225
-fp2 226
-fp3 227
-fp4 228
-fp5 229
-fp6 230
-fp7 231
-
.equ 61
equ 61
.reg 82
.regundef 50
regundef 50
set 149
-
-r0 151
-r1 152
-r2 153
-r3 154
-r4 155
-r5 156
-r6 157
-r7 158
-r8 159
-r9 160
-r10 161
-r11 162
-r12 163
-r13 164
-r14 165
-r15 166
-r16 167
-r17 168
-r18 169
-r19 170
-r20 171
-r21 172
-r22 173
-r23 174
-r24 175
-r25 176
-r26 177
-r27 178
-r28 179
-r29 180
-r30 181
-r31 182
-.ccdef 183
-ccdef 183
-defined 112
-referenced 113
-streq 118
-macdef 119
-time 120
-date 121
-abscount 122
-filesize 70
-
-x0 260
-x1 261
-y0 262
-y1 263
-b0 265
-b2 267
-b1 269
-a 270
-b 271
-n0 280
-n1 281
-n2 282
-n3 283
-n4 284
-n5 285
-n6 286
-n7 287
-m0 288
-m1 289
-m2 290
-m3 291
-m4 292
-m5 293
-m6 294
-m7 295
-
-mr 304
-omr 305
-la 306
-lc 307
-ssh 308
-ssl 309
-ss 310
-
-l 302
-p 303
-
-a10 312
-b10 313
-x 314
-y 315
-ab 318
-ba 319
#include "sect.h"
#include "token.h"
-#define DEF_KW
-#include "kwtab.h"
+#define DEF_REG68
+#include "68kregs.h"
// Exported variables
int movep = 0; // Global flag to indicate we're generating a movep instruction
goto immed1;
}
- if ((*tok >= KW_D0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_A7))
{
// <rlist>, ea
if (reglist(&rmask) < 0)
}
// Dc
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS accepts only data registers");
inst2 = (*tok++) & 7;
return error("missing comma");
// Du
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS accepts only data registers");
inst2 |= ((*tok++) & 7) << 6;
}
// Dc1
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst2 = (*tok++) & 7;
return error("missing colon");
// Dc2
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst3 = (*tok++) & 7;
return error("missing comma");
// Du1
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst2 |= ((*tok++) & 7) << 6;
return error("missing colon");
// Du2
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst3 |= ((*tok++) & 7) << 6;
// Rn1
if (*tok++ != '(')
return error("missing (");
- if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
inst2 |= (((*tok++) & 7) << 12) | (0 << 15);
- else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
inst2 |= (((*tok++) & 7) << 12) | (1 << 15);
else
return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
// Rn2
if (*tok++ != '(')
return error("missing (");
- if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
inst3 |= (((*tok++) & 7) << 12) | (0 << 15);
- else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
inst3 |= (((*tok++) & 7) << 12) | (1 << 15);
else
return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
if (siz != SIZN)
return error("bad size suffix");
- if (*tok >= KW_D0 && *tok <= KW_D7)
+ if (*tok >= REG68_D0 && *tok <= REG68_D7)
{
// Dx,Dy,#<adjustment>
inst |= (0 << 3); // R/M
if (*tok != ',' && tok[2] != ',')
return error("missing comma");
- if (tok[1] < KW_D0 && tok[1] > KW_D7)
+ if (tok[1] < REG68_D0 && tok[1] > REG68_D7)
return error(syntax_error);
inst |= ((tok[1] & 7)<<9);
if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ','))
return error(syntax_error);
- if (tok[1] < KW_A0 && tok[1] > KW_A7)
+ if (tok[1] < REG68_A0 && tok[1] > REG68_A7)
return error(syntax_error);
- if (tok[5] < KW_A0 && tok[6] > KW_A7)
+ if (tok[5] < REG68_A0 && tok[6] > REG68_A7)
return error(syntax_error);
inst |= ((tok[1] & 7) << 0);
inst |= (0 << 6) | (a1reg);
switch (a0reg)
{
- case 0: // KW_IC40
+ case 0: // REG68_IC40
inst |= (2 << 6) | (a1reg);
break;
- case 1: // KW_DC40
+ case 1: // REG68_DC40
inst |= (1 << 6) | (a1reg);
break;
- case 2: // KW_BC40
+ case 2: // REG68_BC40
inst |= (3 << 6) | (a1reg);
break;
}
fc = (uint16_t)a0exval;
break;
- case KW_D0:
- case KW_D1:
- case KW_D2:
- case KW_D3:
- case KW_D4:
- case KW_D5:
- case KW_D6:
- case KW_D7:
+ case REG68_D0:
+ case REG68_D1:
+ case REG68_D2:
+ case REG68_D3:
+ case REG68_D4:
+ case REG68_D5:
+ case REG68_D6:
+ case REG68_D7:
fc = (1 << 4) | (*tok++ & 7);
break;
- case KW_SFC:
+ case REG68_SFC:
fc = 0;
tok++;
break;
- case KW_DFC:
+ case REG68_DFC:
fc = 1;
tok++;
break;
if (*tok != '(' && tok[2] != ')')
return error(syntax_error);
- if (tok[1] < KW_A0 && tok[1] > KW_A7)
+ if (tok[1] < REG68_A0 && tok[1] > REG68_A7)
return error("expected (An)");
if ((inst & 7) == 7)
switch (am0)
{
case CREG:
- if (a0reg == KW_SFC - KW_SFC)
+ if (a0reg == REG68_SFC - REG68_SFC)
inst = 0;
- else if (a0reg == KW_DFC - KW_SFC)
+ else if (a0reg == REG68_DFC - REG68_SFC)
inst = 1;
else
return error("illegal control register specified");
// and the transparent translation registers(TT0 and TT1).
// It is a word operation for the MMU status register.
- if (((reg == (KW_URP - KW_SFC)) || (reg == (KW_SRP - KW_SFC)))
+ if (((reg == (REG68_URP - REG68_SFC)) || (reg == (REG68_SRP - REG68_SFC)))
&& ((siz != SIZD) && (siz != SIZN)))
return error(siz_error);
- if (((reg == (KW_TC - KW_SFC)) || (reg == (KW_TT0 - KW_SFC)) || (reg == (KW_TT1 - KW_SFC)))
+ if (((reg == (REG68_TC - REG68_SFC)) || (reg == (REG68_TT0 - REG68_SFC)) || (reg == (REG68_TT1 - REG68_SFC)))
&& ((siz != SIZL) && (siz != SIZN)))
return error(siz_error);
- if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN)))
+ if ((reg == (REG68_MMUSR - REG68_SFC)) && ((siz != SIZW) && (siz != SIZN)))
return error(siz_error);
if (am0 == CREG)
D_word(inst);
}
- switch (reg + KW_SFC)
+ switch (reg + REG68_SFC)
{
- case KW_TC:
+ case REG68_TC:
inst2 |= (0 << 10) + (1 << 14); break;
- case KW_SRP:
+ case REG68_SRP:
inst2 |= (2 << 10) + (1 << 14); break;
- case KW_CRP:
+ case REG68_CRP:
inst2 |= (3 << 10) + (1 << 14); break;
- case KW_TT0:
+ case REG68_TT0:
inst2 |= (2 << 10) + (0 << 13); break;
- case KW_TT1:
+ case REG68_TT1:
inst2 |= (3 << 10) + (0 << 13); break;
- case KW_MMUSR:
+ case REG68_MMUSR:
if (am0 == CREG)
inst2 |= (1 << 9) + (3 << 13);
else
switch (am0)
{
case CREG:
- if (a0reg == KW_SFC - KW_SFC)
+ if (a0reg == REG68_SFC - REG68_SFC)
extension |= 0;
- else if (a0reg == KW_DFC - KW_SFC)
+ else if (a0reg == REG68_DFC - REG68_SFC)
extension |= 1;
else
return error("illegal control register specified");
{
CHECK_COMMA
- if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{
extension |= (1 << 8) | ((*tok++ & 7) << 4);
}
if (siz == SIZX || siz == SIZN)
{
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
{
// fmovem.x <rlist>,ea
if (fpu_reglist_left(®mask) < 0)
ea0gen(siz);
return OK;
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
// fmovem.x Dn,ea
datareg = (*tok++ & 7) << 10;
if (*tok++ != ',')
return error("missing comma");
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
{
// fmovem.x ea,<rlist>
if (fpu_reglist_right(®mask) < 0)
}
else if (siz == SIZL)
{
- if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR))
+ if ((*tok == REG68_FPCR) || (*tok == REG68_FPSR) || (*tok == REG68_FPIAR))
{
// fmovem.l <rlist>,ea
regmask = (1 << 15) | (1 << 13);
int no_control_regs = 0;
fmovem_loop_1:
- if (*tok == KW_FPCR)
+ if (*tok == REG68_FPCR)
{
regmask |= (1 << 12);
tok++;
goto fmovem_loop_1;
}
- if (*tok == KW_FPSR)
+ if (*tok == REG68_FPSR)
{
regmask |= (1 << 11);
tok++;
goto fmovem_loop_1;
}
- if (*tok == KW_FPIAR)
+ if (*tok == REG68_FPIAR)
{
regmask |= (1 << 10);
tok++;
regmask = (1 << 15) | (0 << 13);
fmovem_loop_2:
- if (*tok == KW_FPCR)
+ if (*tok == REG68_FPCR)
{
regmask |= (1 << 12);
tok++;
goto fmovem_loop_2;
}
- if (*tok == KW_FPSR)
+ if (*tok == REG68_FPSR)
{
regmask |= (1 << 11);
tok++;
goto fmovem_loop_2;
}
- if (*tok == KW_FPIAR)
+ if (*tok == REG68_FPIAR)
{
regmask |= (1 << 10);
tok++;
opkw.h: op.tab kwgen
./kwgen mo <op.tab >opkw.h
+68kregs.h: 68kregs.tab kwgen
+ ./kwgen reg68 <68kregs.tab >68kregs.h
+
+56kregs.h: 56kregs.tab kwgen
+ ./kwgen reg56 <56kregs.tab >56kregs.h
+
+6502regs.h: 6502regs.tab kwgen
+ ./kwgen reg65 <6502regs.tab >6502regs.h
+
+riscregs.h: riscregs.tab kwgen
+ ./kwgen regrisc <riscregs.tab >riscregs.h
+
+unarytab.h: unary.tab kwgen
+ ./kwgen unary <unary.tab >unarytab.h
+
# Looks like this is not needed...
dsp56kkw.h: dsp56k.tab kwgen
./kwgen dsp <dsp56k.tab >dsp56kkw.h
#
clean:
- $(RM) $(OBJS) kwgen.o 68kgen.o rmac kwgen 68kgen 68k.tab kwtab.h 68ktab.h mntab.h risckw.h 6502kw.h opkw.h dsp56kgen dsp56kgen.o dsp56k.tab dsp56kkw.h dsp56ktab.h
+ $(RM) $(OBJS) kwgen.o 68kgen.o rmac kwgen 68kgen 68k.tab kwtab.h 68ktab.h mntab.h risckw.h 6502kw.h opkw.h dsp56kgen dsp56kgen.o dsp56k.tab dsp56kkw.h dsp56ktab.h 68kregs.h 56kregs.h 6502regs.h riscregs.h unarytab.h
#
# Dependencies
#
6502.o: 6502.c direct.h rmac.h symbol.h token.h expr.h error.h mach.h \
- procln.h riscasm.h sect.h kwtab.h
+ procln.h riscasm.h sect.h kwtab.h 6502regs.h
68kgen: 68kgen.c
amode.o: amode.c amode.h rmac.h symbol.h error.h expr.h mach.h procln.h \
- token.h sect.h riscasm.h kwtab.h mntab.h parmode.h
+ token.h sect.h riscasm.h kwtab.h mntab.h parmode.h 68kregs.h
debug.o: debug.c debug.h rmac.h symbol.h amode.h direct.h token.h expr.h \
mark.h sect.h riscasm.h
direct.o: direct.c direct.h rmac.h symbol.h token.h 6502.h amode.h \
error.h expr.h fltpoint.h listing.h mach.h macro.h mark.h procln.h \
- riscasm.h sect.h kwtab.h
+ riscasm.h sect.h kwtab.h 56kregs.h riscregs.h
dsp56k.o: dsp56k.c rmac.h symbol.h dsp56k.h sect.h riscasm.h
dsp56k_amode.o: dsp56k_amode.c dsp56k_amode.h rmac.h symbol.h amode.h \
error.h token.h expr.h procln.h sect.h riscasm.h kwtab.h mntab.h
expr.h listing.h mark.h macro.h object.h procln.h riscasm.h sect.h \
version.h
sect.o: sect.c sect.h rmac.h symbol.h riscasm.h 6502.h direct.h token.h \
- error.h expr.h listing.h mach.h mark.h
+ error.h expr.h listing.h mach.h mark.h riscregs.h
symbol.o: symbol.c symbol.h error.h rmac.h listing.h object.h procln.h \
token.h
token.o: token.c token.h rmac.h symbol.h direct.h error.h macro.h \
- procln.h sect.h riscasm.h kwtab.h
-
+ procln.h sect.h riscasm.h kwtab.h unarytab.h
for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i
if %NEWEST%==%FILE1% GOTO BUILD
+SET FILE1=68kregs.tab
+SET FILE2=68kregs.h
+if not exist %FILE2% GOTO BUILD
+for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i
+if %NEWEST%==%FILE1% GOTO BUILD
+
+SET FILE1=56kregs.tab
+SET FILE2=56kregs.h
+if not exist %FILE2% GOTO BUILD
+for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i
+if %NEWEST%==%FILE1% GOTO BUILD
+
+SET FILE1=6502regs.tab
+SET FILE2=6502regs.h
+if not exist %FILE2% GOTO BUILD
+for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i
+if %NEWEST%==%FILE1% GOTO BUILD
+
+SET FILE1=riscregs.tab
+SET FILE2=riscregs.h
+if not exist %FILE2% GOTO BUILD
+for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i
+if %NEWEST%==%FILE1% GOTO BUILD
+
+SET FILE1=unary.tab
+SET FILE2=unarytab.h
+if not exist %FILE2% GOTO BUILD
+for /F %%i IN ('dir /b /OD %FILE1% %FILE2% ^| more +1') DO SET NEWEST=%%i
+if %NEWEST%==%FILE1% GOTO BUILD
+
GOTO END
:BUILD
kwgen mp <6502.tab >6502kw.h
kwgen mp <6502.tab >6502kw.h
kwgen mo <op.tab >opkw.h
-
+kwgen reg68 <68kregs.tab >68kregs.h
+kwgen reg56 <56kregs.tab >56kregs.h
+kwgen reg65 <6502regs.tab >6502regs.h
+kwgen regrisc <riscregs.tab >riscregs.h
+kwgen unary <unary.tab >unarytab.h
rem touch files that include these header files so they'll recompile
echo Generating tables...
// Dn
// An
// # expression
- if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
AMn = DREG;
AnREG = *tok++ & 7;
}
- else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{
AMn = AREG;
AnREG = *tok++ & 7;
int ea_PC = 0; // Flag that let us know if we have PC or An relative ea
tok++;
- if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{
AnREG = *tok++ & 7;
AMn = AINDEXED;
goto AMn_IX0; // Handle ",Xn[.siz][*scale])"
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
// Since index register isn't used here, store register number in this field
AnIXREG = *tok++ & 7; // (Dn)
else
return error("unhandled so far");
}
- else if (*tok == KW_PC)
+ else if (*tok == REG68_PC)
{ // (PC,Xn[.siz][*scale])
tok++;
AMn = PCINDEXED;
if (*tok++ != ',')
goto badmode;
- if (*tok < KW_D0 || *tok > KW_A7)
+ if (*tok < REG68_D0 || *tok > REG68_A7)
goto badmode;
AnIXREG = *tok++ & 15;
// Check for address register or PC, suppress base register
// otherwise
- if (*tok == KW_PC)
+ if (*tok == REG68_PC)
{ // ([bd,PC,...
ea_PC = 3; // Set flag in order to set proper value to AMn below when we can make a decision on ea
// (why "3"? Well, MEMPOST is 3 away from PCMPOST, etc. Have a look at amode.h)
AnREG = (7 << 3) | 3; // PC is special case - stuff 011 to register field and 111 to the mode field
tok++;
}
- else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{ // ([bd,An,...
AnREG = (6 << 3) | (*tok & 7);
tok++;
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
// ([bd,Dn,...
AnREG = (6 << 3);
else
tok++; // eat the comma
- if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{
AnIXREG = ((*tok & 7) << 12);
AnEXTEN |= EXT_A;
tok++;
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
AnEXTEN |= ((*tok & 7) << 12);
AnEXTEN |= EXT_D;
tok++; // ([bd,An,Xn.size*scale],od)
// Check for Xn
- if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{
AnEXTEN |= ((*tok & 7) << 12);
AnEXTEN |= EXT_A;
tok++;
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
AnEXTEN |= ((*tok & 7) << 12);
AnEXTEN |= EXT_D;
if (*tok++ != ',')
goto badmode;
- if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{
AnREG = *tok & 7;
tok++;
AnBEXVAL = AnEXVAL;
AnBEXATTR = AnEXATTR;
- if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
AnEXTEN |= ((*tok++) & 7) << 12;
// Check for size
else
goto badmode;
}
- else if (*tok == KW_PC)
+ else if (*tok == REG68_PC)
{
if (*++tok == ',')
{ // expr(PC,Xn...)
goto badmode;
}
}
- else if (*tok == '-' && tok[1] == '(' && ((tok[2] >= KW_A0) && (tok[2] <= KW_A7)) && tok[3] == ')')
+ else if (*tok == '-' && tok[1] == '(' && ((tok[2] >= REG68_A0) && (tok[2] <= REG68_A7)) && tok[3] == ')')
{
AMn = APREDEC;
AnREG = tok[2] & 7;
tok += 4;
}
- else if (*tok == KW_CCR)
+ else if (*tok == REG68_CCR)
{
AMn = AM_CCR;
tok++;
goto AnOK;
}
- else if (*tok == KW_SR)
+ else if (*tok == REG68_SR)
{
AMn = AM_SR;
tok++;
goto AnOK;
}
- else if (*tok == KW_USP)
+ else if (*tok == REG68_USP)
{
AMn = AM_USP;
tok++;
AnREG = 2; // Added this for the case of USP used in movec (see CREGlut in mach.c). Hopefully nothing gets broken!
goto AnOK;
}
- else if ((*tok >= KW_IC40) && (*tok <= KW_BC40))
+ else if ((*tok >= REG68_IC40) && (*tok <= REG68_BC40))
{
AMn = CACHES;
- AnREG = *tok++ - KW_IC40;
+ AnREG = *tok++ - REG68_IC40;
// After a cache keyword only a comma or EOL is allowed
if ((*tok != ',') && (*tok != EOL))
return ERROR;
goto AnOK;
}
- else if ((*tok >= KW_SFC) && (*tok <= KW_CRP))
+ else if ((*tok >= REG68_SFC) && (*tok <= REG68_CRP))
{
AMn = CREG;
- AnREG = (*tok++) - KW_SFC;
+ AnREG = (*tok++) - REG68_SFC;
goto AnOK;
}
- else if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ else if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
{
AMn = FREG;
AnREG = (*tok++ & 7);
}
- else if ((*tok >= KW_FPIAR) && (*tok <= KW_FPCR))
+ else if ((*tok >= REG68_FPIAR) && (*tok <= REG68_FPCR))
{
AMn = FPSCR;
- AnREG = (1 << ((*tok++) - KW_FPIAR + 10));
+ AnREG = (1 << ((*tok++) - REG68_FPIAR + 10));
}
// expr
// expr.w
tok++;
- if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
{
AnREG = *tok++ & 7;
AMn = AINDEXED;
goto AMn_IXN;
}
- else if (*tok == KW_PC)
+ else if (*tok == REG68_PC)
{
if (*++tok == ')')
{
#define DEF_MN // Incl 68k keyword definitions
#define DECL_MN // Incl 68k keyword state machine tables
#include "mntab.h"
+#define DEF_REG68 // Incl 68k register definitions
+#include "68kregs.h"
#define DEF_MR
#define DECL_MR
#define DEF_DSP // Include DSP56K keywords definitions
#define DECL_DSP // Include DSP56K keyword state machine tables
#include "dsp56kkw.h"
-
+#define DEF_REG56 // Include DSP56K register definitions
+#include "56kregs.h"
IFENT * ifent; // Current ifent
static IFENT ifent0; // Root ifent
// First token MUST be a symbol (Shamus: not sure why :-/)
if (*tok != SYMBOL)
{
- if ((*tok >= KW_D0) && (*tok <= KW_R31))
- error("cannot use reserved keyword as label name or .equ");
- else
- error("syntax error; expected symbol");
+ error("syntax error; expected symbol");
goto loop;
}
// Check for register to equate to
// This check will change once we split the registers per architecture into their own tables
// and out of kw.tab. But for now it'll do...
- if ((*tok >= KW_D0) && (*tok <= KW_BA))
+ if ((*tok >= REG68_D0) && (*tok <= REG56_BA))
{
sy->sattre = EQUATEDREG; // Mark as equated register
equreg = *tok;
#define DEF_MR // Declare keyword values
#include "risckw.h" // Incl. generated risc keywords
-#define DEF_KW // Declare keyword values
-#include "kwtab.h" // Incl. generated keyword tables & defs
+#define DEF_REGRISC
+#include "riscregs.h" // Incl. generated keyword tables & defs
#define MAXINTERNCC 26 // Maximum internal condition codes
//
static inline int IllegalIndexedRegister(int reg)
{
- return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0);
+ return error("Attempted index reference with non-indexable register (r%d)", reg - REGRISC_R0);
}
//
// Firstly, check to see if it's a register token and return that. No
// need to invoke expr() for easy cases like this.
int reg = *tok & 255;
- if (reg >= KW_R0 && reg <= KW_R31)
+ if (reg >= REGRISC_R0 && reg <= REGRISC_R31)
{
- reg -= KW_R0;
+ reg -= REGRISC_R0;
tok++;
return reg;
}
// We shouldn't get here, that should not be legal
interror(9);
+ return 0; // Not that this will ever execute, but let's be nice and pacify gcc warnings
}
//
// PC,Rd or Rs,Rd
case RI_MOVE:
- if (*tok == KW_PC)
+ if (*tok == REGRISC_PC)
{
parm = 51;
reg1 = 0;
if ((tok[1] == '+') || (tok[1] == '-'))
{
// Trying to make indexed call
- if ((*tok == KW_R14) || (*tok == KW_R15))
- indexed = (*tok - KW_R0);
+ if ((*tok == REGRISC_R14) || (*tok == REGRISC_R15))
+ indexed = (*tok - REGRISC_R0);
else
return IllegalIndexedRegister(*tok);
}
parm = (WORD)(reg1 - 14 + 58);
tok++;
- if ((*tok >= KW_R0) && (*tok <= KW_R31))
+ if ((*tok >= REGRISC_R0) && (*tok <= REGRISC_R31))
indexed = 1;
if (*tok == SYMBOL)
tok++;
indexed = 0;
- if (((*tok == KW_R14) || (*tok == KW_R15)) && (tok[1] != ')'))
- indexed = *tok - KW_R0;
+ if (((*tok == REGRISC_R14) || (*tok == REGRISC_R15)) && (tok[1] != ')'))
+ indexed = *tok - REGRISC_R0;
if (!indexed)
{
parm = (WORD)(reg2 - 14 + 60);
tok++;
- if ((*tok >= KW_R0) && (*tok <= KW_R31))
+ if ((*tok >= REGRISC_R0) && (*tok <= REGRISC_R31))
indexed = 1;
if (*tok == SYMBOL)
--- /dev/null
+pc 145
+
+r0 151
+r1 152
+r2 153
+r3 154
+r4 155
+r5 156
+r6 157
+r7 158
+r8 159
+r9 160
+r10 161
+r11 162
+r12 163
+r13 164
+r14 165
+r15 166
+r16 167
+r17 168
+r18 169
+r19 170
+r20 171
+r21 172
+r22 173
+r23 174
+r24 175
+r25 176
+r26 177
+r27 178
+r28 179
+r29 180
+r30 181
+r31 182
+
int list_fd; // File to write listing to
int segpadsize; // Segment padding size
int endian; // Host processor endianess (0 = LE, 1 = BE)
+int *regbase; // Points to current DFA register table (base)
+int *regtab; // Points to current DFA register table (tab)
+int *regcheck; // Points to current DFA register table (check)
+int *regaccept; // Points to current DFA register table (accept)
char * objfname; // Object filename pointer
char * firstfname; // First source filename
char * cmdlnexec; // Executable name, pointer to ARGV[0]
return OK;
}
+extern int reg68base[53];
+extern int reg68tab[222];
+extern int reg68check[222];
+extern int reg68accept[222];
+
//
// Process command line arguments and do an assembly
//
dsp_orgmap[0].start = 0; // Initialize 56001 org initial address
dsp_orgmap[0].memtype = ORG_P; // Initialize 56001 org start segment
m6502 = 0; // 6502 mode off by default
+ regbase = reg68base; // Initialise DFA register tables
+ regtab = reg68tab; // Idem
+ regcheck = reg68check; // Idem
+ regaccept = reg68accept; // Idem
// Initialize modules
InitSymbolTable(); // Symbol table
extern int activefpu;
extern uint32_t org68k_address;
extern int org68k_active;
+extern int *regbase;
+extern int *regtab;
+extern int *regcheck;
+extern int *regaccept;
// Exported functions
void strtoupper(char * s);
#include "riscasm.h"
#include "symbol.h"
#include "token.h"
-#define DEF_KW
-#include "kwtab.h"
-#undef DEF_KW
+#define DEF_REGRISC
+#include "riscregs.h"
// Function prototypes
void MakeSection(int, uint16_t);
}
else if ((dw & FUMASKRISC) == FU_REGONE)
{
- eval -= KW_R0;
+ eval -= REGRISC_R0;
if (eval > 31)
{
error("register one value out of range");
}
else if ((dw & FUMASKRISC) == FU_REGTWO)
{
- eval -= KW_R0;
+ eval -= REGRISC_R0;
if (eval > 31)
{
error("register two value out of range");
#define DECL_KW // Declare keyword arrays
#define DEF_KW // Declare keyword values
#include "kwtab.h" // Incl generated keyword tables & defs
+#define DEF_REG68 // Incl 68k register definitions
+#include "68kregs.h"
+#define DEF_REGRISC // Include GPU/DSP register definitions
+#include "riscregs.h"
+#define DEF_UNARY // Declare unary values
+#define DECL_UNARY // Incl uanry keyword state machine tables
+#include "unarytab.h" // Incl generated unary tables & defs
int lnsave; // 1; strcpy() text of current line
"a10","b10","x","y","","","ab","ba" // 312,319
};
+WARNING("We should get rid of this table, it's a subset of the table above")
static char * riscregname[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
// This is a hack. It might be better table-driven.
d = NULL;
- if ((*tk >= KW_D0) && !rdsp && !rgpu)
+ if ((*tk >= REG68_D0) && !rdsp && !rgpu)
{
- d = regname[(int)*tk++ - KW_D0];
+ d = regname[(int)*tk++ - REG68_D0];
goto strcopy;
}
- else if ((*tk >= KW_R0) && (*tk <= KW_R31))
+ else if ((*tk >= REGRISC_R0) && (*tk <= REGRISC_R31))
{
- d = riscregname[(int)*tk++ - KW_R0];
+ d = riscregname[(int)*tk++ - REGRISC_R0];
goto strcopy;
}
else
// If the symbol is small, check to see if it's really the name of
// a register.
- if (j <= KWSIZE)
+ uint8_t *p2 = p;
+ if (j <= 5)
{
- for(state=0; state>=0;)
+ for (state = 0; state >= 0;)
{
j = (int)tolowertab[*p++];
- j += kwbase[state];
+ j += regbase[state];
- if (kwcheck[j] != state)
+ if (regcheck[j] != state)
{
j = -1;
break;
if (*p == EOS || p == ln)
{
- j = kwaccept[j];
+ j = regaccept[j];
+ goto skip_keyword;
break;
}
- state = kwtab[j];
+ state = regtab[j];
}
}
- else
- {
- j = -1;
- }
- // Make j = -1 if user tries to use a RISC register while in 68K mode
- if (!(rgpu || rdsp || dsp56001) && ((TOKEN)j >= KW_R0 && (TOKEN)j <= KW_R31))
+ // Scan for keywords
+ if ((j <= 0 || state <= 0) || p==p2)
{
- j = -1;
+ if (j <= KWSIZE)
+ {
+ for (state = 0; state >= 0;)
+ {
+ j = (int)tolowertab[*p2++];
+ j += kwbase[state];
+
+ if (kwcheck[j] != state)
+ {
+ j = -1;
+ break;
+ }
+
+ if (*p == EOS || p2 == ln)
+ {
+ j = kwaccept[j];
+ break;
+ }
+
+ state = kwtab[j];
+ }
+ }
+ else
+ {
+ j = -1;
+ }
}
- // Make j = -1 if time, date etc with no preceeding ^^
- // defined, referenced, streq, macdef, date and time
- switch ((TOKEN)j)
- {
- case 112: // defined
- case 113: // referenced
- case 118: // streq
- case 119: // macdef
- case 120: // time
- case 121: // date
- case KW_FILESIZE: // filesize
- j = -1;
- }
-
+ skip_keyword:
+
// If we detected equrundef/regundef set relevant flag
if (j == KW_EQURUNDEF)
{
for(state=0; state>=0;)
{
// Get char, convert to lowercase
- j = *p++;
+ j = (int)tolowertab[*p++];
- if (j >= 'A' && j <= 'Z')
- j += 0x20;
+ //if (j >= 'A' && j <= 'Z')
+ // j += 0x20;
- j += kwbase[state];
+ j += unarybase[state];
- if (kwcheck[j] != state)
+ if (unarycheck[j] != state)
{
j = -1;
break;
if (*p == EOS || p == ln)
{
- j = kwaccept[j];
+ j = unaryaccept[j];
break;
}
- state = kwtab[j];
+ state = unarytab[j];
}
if (j < 0 || state < 0)
--- /dev/null
+.ccdef 183
+ccdef 183
+defined 112
+referenced 113
+
+streq 118
+macdef 119
+time 120
+date 121
+filesize 70
+abscount 122
projects / rmac / commitdiff