if (K_D1 == K_D2)
return error("unrecognised X:Y: parallel move syntax: D1 and D2 cannot be the same in 'X:ea,D1 Y:eay,D2'");
- inst = B16(11000000, 00000000) | w;
+ inst = 0b1100000000000000 | w;
inst |= ea1 | D1 | ea2 | D2;
return inst;
}
ea2 |= eay_temp; //OR eay back from temp
- inst = B16(10000000, 00000000) | w;
+ inst = 0b1000000000000000 | w;
inst |= (ea1 & 0x1f) | D1 | S2 | ea2;
return inst;
}
if (ea1 == -1)
return error("unrecognised X:R parallel move syntax: absolute address not allowed in 'a,X:ea x0,a'");
- if (ea1 == B8(00110100))
+ if (ea1 == 0b00110100)
return error("unrecognised X:R parallel move syntax: immediate data not allowed in 'a,X:ea x0,a'");
- inst = B16(00001000, 00000000) | ea1 | (0 << 8);
+ inst = 0b0000100000000000 | ea1 | (0 << 8);
return inst;
}
else if (*tok == KW_X0 && tok[1] == ',' && tok[2] == KW_B)
if (ea1 == -1)
return error("unrecognised X:R parallel move syntax: absolute address not allowed in 'b,X:ea x0,b'");
- if (ea1 == B8(00110100))
+ if (ea1 == 0b00110100)
return error("unrecognised X:R parallel move syntax: immediate data not allowed in 'b,X:ea x0,b'");
- inst = B16(00001001, 00000000) | ea1 | (1 << 8);
+ inst = 0b0000100100000000 | ea1 | (1 << 8);
return inst;
}
else if (*tok == KW_A || *tok == KW_B)
if (*tok != EOL)
return error("unrecognised X:R parallel move syntax: unexpected text after 'X:eax,D1 S2,S2'");
- inst = B16(00010000, 00000000) | (0 << 7);
+ inst = 0b0001000000000000 | (0 << 7);
inst |= ea1 | D1 | S2 | D2;
return inst;
}
if (*tok == EOL)
{
// 'X:ea,D'
- inst = inst | B8(01000000) | (1 << 7);
+ inst = inst | 0b01000000 | (1 << 7);
inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8);
inst |= ea1;
if (*tok != EOL)
return error("unrecognised X:R parallel move syntax: expected EOL after X:ea,D1 S2,D2");
- inst = B16(00010000, 00000000) | (1 << 7);
+ inst = 0b0001000000000000 | (1 << 7);
inst |= ((D1 & 0x8) << (12 - 4)) + ((D1 & 1) << 10);
inst |= (S2 & 1) << 9;
inst |= (D2 & 1) << 8;
if (*tok == EOL)
{
// 'S,X:ea'
- inst = inst | B8(01000000) | (0 << 7);
+ inst = inst | 0b01000000 | (0 << 7);
inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8);
inst |= ea1;
//'X:ea,D'
D1 = SDreg(*tok++);
- inst = inst | B8(01000000) | (1 << 7);
+ inst = inst | 0b01000000 | (1 << 7);
inst |= ea1;
inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8);
return inst;
if (*tok == EOL)
{
//'S,X:ea'
- inst = inst | B8(01000000) | (0 << 7);
+ inst = inst | 0b01000000 | (0 << 7);
inst |= ea1;
inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8);
return inst;
if (*tok != EOL)
return error("unrecognised X:R parallel move syntax: unexpected text after 'X:eax,D1 S2,S2'");
- inst = B16(00010000, 00000000) | (W << 7);
+ inst = 0b0001000000000000 | (W << 7);
inst |= ea1 | D1 | S2 | D2;
return inst;
}
if (*tok == EOL && S1 != 0)
{
// 'S,Y:aa'
- inst = B16(01001000, 00000000);
+ inst = 0b0100100000000000;
inst |= dspImmedEXVAL;
inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8);
return inst;
if (*tok == EOL && S1 != 0)
{
// 'S,Y:ea'
- inst = B16(01001000, 01110000);
+ inst = 0b0100100001110000;
inst |= ea1;
inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8);
if (ea1 == DSP_EA_ABS)
if (*tok != EOL)
return error("unrecognised Y: parallel move syntax: expected EOL after 'Y:ea,D'");
- inst |= B16(00000000, 01110000);
+ inst |= 0b0000000001110000;
inst |= ea1;
inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8);
if (ea1 == DSP_EA_ABS)
if (S1 != 0 && *tok == EOL)
{
// 'S,Y:ea'
- inst = B16(01001000, 01000000);
+ inst = 0b0100100001000000;
inst |= ea1;
inst |= ((S1 & 0x18) << (12 - 3)) + ((S1 & 7) << 8);
return inst;
default: return error("unrecognised R:Y parallel move syntax: D2 can only be y0, y1, a or b after 'S1,D1 Y:ea'");
}
- inst = B16(00010000, 11000000);
+ inst = 0b0001000011000000;
inst |= S1 | D1 | D2;
inst |= ea1;
return inst;
{
//'Y:ea,D'
D1 = SDreg(*tok++);
- inst |= B16(00000000, 01000000);
+ inst |= 0b0000000001000000;
inst |= ea1;
inst |= ((D1 & 0x18) << (12 - 3)) + ((D1 & 7) << 8);
return inst;
else
S1 &= 7;
- inst = B16(01000000, 00000000);
+ inst = 0b0100000000000000;
inst |= dspImmedEXVAL;
inst |= ((S1 & 0x4) << (11 - 2)) + ((S1 & 3) << 8);
return inst;
if (ea1 == DSP_EA_ABS)
deposit_extra_ea = DEPOSIT_EXTRA_WORD;
- inst |= B16(01000000, 01110000);
+ inst |= 0b0100000001110000;
inst |= ((S1 & 0x4) << (11 - 2)) + ((S1 & 3) << 8);
inst |= ea1;
return inst;
if (*tok != EOL)
return error("unrecognised L: parallel move syntax: expected End-Of-Line after L:aa,D");
- inst &= B16(11111111, 10111111);
+ inst &= 0b1111111110111111;
inst |= dspImmedEXVAL;
inst |= ((immreg & 0x4) << (11 - 2)) + ((immreg & 3) << 8);
return inst;
if (*tok != EOL)
return error("unrecognised L: parallel move syntax: expected End-Of-Line after L:ea,D");
- inst |= B16(00000000, 00110000);
+ inst |= 0b0000000000110000;
inst |= ((D1 & 0x4) << (11 - 2)) + ((D1 & 3) << 8);
return inst;
}
if (*tok == EOL)
{
// 'S,L:ea'
- inst = B16(01000000, 01000000);
+ inst = 0b0100000001000000;
if (S1 == KW_A)
S1 = 4;
if (*tok == EOL)
{
// No parallel move
- return B16(00100000, 00000000);
+ return 0b0010000000000000;
}
if (*tok == '#')
{
// '#xx,D'
// value fits in 8 bits - immediate move
- inst = B16(00100000, 00000000) + (immreg << 8) + (uint32_t)dspImmedEXVAL;
+ inst = 0b0010000000000000 + (immreg << 8) + (uint32_t)dspImmedEXVAL;
return inst;
}
else
// X or Y Data move. I don't think it matters much
// which of the two it will be, so let's use X.
deposit_immediate_long_with_register:
- inst = B16(01000000, 11110100);
+ inst = 0b0100000011110100;
inst |= ((immreg & 0x18) << (12 - 3)) + ((immreg & 7) << 8);
deposit_extra_ea = DEPOSIT_EXTRA_WORD;
return inst;
{
// value fits in 8 bits - immediate move
deposit_immediate_short_with_register:
- inst = B16(00100000, 00000000) + (immreg << 8) + (uint32_t)dspImmedEXVAL;
+ inst = 0b0010000000000000 + (immreg << 8) + (uint32_t)dspImmedEXVAL;
return inst;
}
else
// '#xx,D' - I mode
// No visibility of the number so let's add a fixup for this
AddFixup(FU_DSPIMM8, sloc, dspImmedEXPR);
- inst = B16(00100000, 00000000);
+ inst = 0b0010000000000000;
inst |= ((immreg & 0x18) << (11 - 3)) + ((immreg & 7) << 8);
return inst;
}
{
// Just deposit a float fixup
AddFixup(FU_DSPIMMFL8, sloc, dspImmedEXPR);
- inst = B16(00100000, 00000000);
+ inst = 0b0010000000000000;
inst |= ((immreg & 0x18) << (12 - 3)) + ((immreg & 7) << 8);
return inst;
}
if (*tok != EOL)
return error("unrecognised X:R parallel move syntax: expected end-of-line after '#xxxxxx,D1 S2,D2'");
- inst = B16(00010000, 10110100) | D1 | S2 | D2;
+ inst = 0b0001000010110100 | D1 | S2 | D2;
deposit_extra_ea = DEPOSIT_EXTRA_WORD;
return inst;
}
return error("expected ':' after 'X' in parallel move (i.e. X:)");
// 'X:ea,D' or 'X:aa,D' or 'X:ea,D1 S2,D2' or 'X:eax,D1 Y:eay,D2' or 'X:eax,D1 S2,Y:eay'
- return parse_x(1, B16(01000000, 00000000), 0, 1);
+ return parse_x(1, 0b0100000000000000, 0, 1);
}
else if (*tok == KW_Y)
{
return error("expected ':' after 'Y' in parallel move (i.e. Y:)");
// 'Y:ea,D' or 'Y:aa,D'
- return parse_y(B16(01001000, 10000000), 0, 0, 0);
+ return parse_y(0b0100100010000000, 0, 0, 0);
}
else if (*tok == KW_L)
{
if (*tok++ != ':')
return error("expected ':' after 'L' in parallel move (i.e. L:)");
- return parse_l(1, B16(01000000, 11000000), 0);
+ return parse_l(1, 0b0100000011000000, 0);
}
else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2) || (*tok >= KW_A10 && *tok <= KW_BA))
{
if (*tok++ != ':')
return error("unrecognised X: parallel move syntax: expected ':' after 'S,X'");
- return parse_x(0, B16(01000000, 00000000), S1, 1);
+ return parse_x(0, 0b0100000000000000, S1, 1);
}
else if (*tok == KW_Y)
{
if (*tok++ != ':')
return error("unrecognised Y: parallel move syntax: expected ':' after 'S,Y'");
- return parse_y(B16(0000000, 00000000), S1, 0, 0);
+ return parse_y(0b000000000000000, S1, 0, 0);
}
else if (*tok == KW_L)
{
if (*tok++ != ':')
return error("unrecognised L: parallel move syntax: expected ':' after 'S,L'");
- return parse_l(1, B16(00000000, 00000000), L_S1);
+ return parse_l(1, 0b0000000000000000, L_S1);
}
else if ((*tok >= KW_X0 && *tok <= KW_N7) || (*tok >= KW_R0 && *tok <= KW_R7) || (*tok >= KW_A0 && *tok <= KW_A2))
{
if (*tok == EOL)
{
// R 'S,D'
- inst = B16(00100000, 00000000);
+ inst = 0b0010000000000000;
inst |= (S1 << 5) | (D1);
return inst;
}
tok++;
if (*tok++ != ':')
return error("expected ':' after 'Y' in parallel move (i.e. Y:)");
- return parse_y(B16(00010000, 01000000), S1, D1, 0);
+ return parse_y(0b0001000001000000, S1, D1, 0);
}
else if (*tok == KW_A || *tok == KW_B || *tok == KW_Y0 || *tok == KW_Y1)
if (ea1 == ERROR)
return ERROR;
- inst = B16(00001000, 10000000);
+ inst = 0b0000100010000000;
inst |= 0 << 8;
inst |= ea1;
return inst;
if (ea1 == ERROR)
return ERROR;
- inst = B16(00001000, 10000000);
+ inst = 0b0000100010000000;
inst |= 1 << 8;
inst |= ea1;
return inst;
if (ea1 == ERROR)
return ERROR;
- inst = B16(00010000, 01000000);
+ inst = 0b0001000001000000;
inst |= (S1 & 1) << 11;
inst |= (D1 & 1) << 10;
inst |= ((S2 & 8) << (10 - 4)) | ((S2 & 1) << 8);
{
if (D1 == 4 || D1 == 5)
{
- inst = B16(00010000, 11110100);
+ inst = 0b0001000011110100;
inst |= (S1 & 1) << 11;
inst |= (D1 & 1) << 10;
inst |= D2;
}
}
- inst = B16(00100000, 01000000);
+ inst = 0b0010000001000000;
inst |= ea1;
return inst;
}
&& ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED))
&& ((a0exval > 0) && (a0exval <= 8)))
{
- inst = B16(01010000, 01001000) | (((uint16_t)a0exval & 7) << 9) | (a0reg);
+ inst = 0b0101000001001000 | (((uint16_t)a0exval & 7) << 9) | (a0reg);
D_word(inst);
if (optim_warn_flag)
if ((a0exval > 1) && (a0exval <= 8))
{
// Immediate is between 1 and 8 so let's convert to addq
- return m_addq(B16(01010000, 00000000), siz);
+ return m_addq(0b0101000000000000, siz);
if (optim_warn_flag)
warn("o8: adda/suba size(An),An converted to addq/subq #size,An");
int return_value;
int temp_flag = optim_flags[OPT_LEA_ADDQ];
optim_flags[OPT_LEA_ADDQ] = 1; // Temporarily save switch state
- return_value = m_lea(B16(01000001, 11011000), SIZW);
+ return_value = m_lea(0b0100000111011000, SIZW);
optim_flags[OPT_LEA_ADDQ] = temp_flag; // Restore switch state
if (optim_warn_flag)
warn("o9: adda.w/l #x,Ay converted to lea x(Dy),Ay");
inst |= a0reg;
else
{
- inst = (a0reg << 9) | B16(01110000, 00000000);
+ inst = (a0reg << 9) | 0b0111000000000000;
if (optim_warn_flag)
warn("o7: clr.l Dx converted to moveq #0,Dx");
}
bfparam1 = bfval1 << 12;
//D_word((inst | am0 | a0reg | am1 | a1reg));
- if (inst == B16(11101111, 11000000))
+ if (inst == 0b1110111111000000)
{
// bfins special case
D_word((inst | am1 | a1reg));
ea0gen(siz); // Generate EA
// Second instruction word - Dest register (if exists), Do, Offset, Dw, Width
- if (inst == B16(11101111, 11000000))
+ if (inst == 0b1110111111000000)
{
// bfins special case
inst = bfparam1 | bfparam2;
}
else if (activecpu == CPU_68040)
{
- inst = B16(11110101, 00011000);
+ inst = 0b1111010100011000;
D_word(inst);
return OK;
}
ea1gen(siz);
}
- D_word(B16(10100000, 00000000));
+ D_word(0b1010000000000000);
return OK;
}
int m_fabs(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00011000, FPU_NOWARN);
}
{
CHECKNO40;
if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011000, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdabs(WORD inst, WORD siz)
{
if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011100, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_facos(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011100, FPU_FPSP);
}
int m_fadd(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00100010, FPU_NOWARN);
}
int m_fsadd(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100010, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdadd(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100110), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100110, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fasin(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001100, FPU_FPSP);
}
int m_fatan(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001010), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001010, FPU_FPSP);
}
int m_fatanh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001101, FPU_FPSP);
}
int m_fcmp(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00111000), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00111000, FPU_FPSP);
}
int m_fcos(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011101, FPU_FPSP);
}
int m_fcosh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011001, FPU_FPSP);
}
int m_fdiv(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00100000, FPU_NOWARN);
}
int m_fsdiv(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100000, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fddiv(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100100, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fetox(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010000), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010000, FPU_FPSP);
}
int m_fetoxm1(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001000), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001000, FPU_FPSP);
}
int m_fgetexp(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011110, FPU_FPSP);
}
int m_fgetman(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011111), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011111, FPU_FPSP);
}
if (activefpu == FPU_68040)
warn("Instruction is emulated in 68040");
- return gen_fpu(inst, siz, B8(00000001), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00000001, FPU_NOWARN);
}
if (activefpu == FPU_68040)
warn("Instruction is emulated in 68040");
- return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00000011, FPU_NOWARN);
}
int m_flog10(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010101, FPU_FPSP);
}
int m_flog2(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010110, FPU_FPSP);
}
int m_flogn(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010100, FPU_FPSP);
}
int m_flognp1(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00000110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00000110, FPU_FPSP);
}
int m_fmod(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100001, FPU_FPSP);
}
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return gen_fpu(inst, siz, B8(01100100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b01100100, FPU_FPSP);
}
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return gen_fpu(inst, siz, B8(01100100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b01100100, FPU_FPSP);
}
int m_fmul(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100011), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00100011, FPU_NOWARN);
}
int m_fsmul(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100011, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdmul(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100111), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100111, FPU_NOWARN);
return error("Unsupported in current FPU");
}
if (am1 == AM_NONE)
{
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00011010, FPU_NOWARN);
}
- return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00011010, FPU_NOWARN);
}
if (am1 == AM_NONE)
{
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011010, FPU_NOWARN);
}
- return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011010, FPU_NOWARN);
}
return error("Unsupported in current FPU");
if (am1 == AM_NONE)
{
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011110, FPU_NOWARN);
}
- return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011110, FPU_NOWARN);
}
return error("Unsupported in current FPU");
int m_fnop(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00000000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00000000, FPU_NOWARN);
}
int m_frem(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100101, FPU_FPSP);
}
int m_fscale(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100110, FPU_FPSP);
}
int m_fsgldiv(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100100, FPU_FPSP);
}
int m_fsglmul(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100111), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100111, FPU_FPSP);
}
int m_fsin(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001110, FPU_FPSP);
}
a2reg = a1reg;
a1reg = temp;
- if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK)
+ if (gen_fpu(inst, siz, 0b00110000, FPU_FPSP) == OK)
{
chptr[-1] |= a2reg;
return OK;
int m_fsinh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00000010), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00000010, FPU_FPSP);
}
int m_fsqrt(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00000100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00000100, FPU_NOWARN);
}
int m_fsfsqrt(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01000001, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdfsqrt(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01000101), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01000101, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fsub(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00101000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00101000, FPU_NOWARN);
}
int m_fsfsub(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01101000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01101000, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdsub(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01101100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01101100, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_ftan(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001111), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001111, FPU_FPSP);
}
int m_ftanh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001001, FPU_FPSP);
}
int m_ftentox(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010010), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010010, FPU_FPSP);
}
int m_ftst(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00111010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00111010, FPU_NOWARN);
}
int m_ftwotox(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010001, FPU_FPSP);
}
int m_lpstop(WORD inst, WORD siz)
{
CHECKNO60;
- D_word(B16(00000001, 11000000));
+ D_word(0b0000000111000000);
if (a0exattr & DEFINED)
{