+// Adjust location to a PHRASE value
+//
+// N.B.: We have to handle the GPU/DSP cases separately because you can embed
+// RISC code in the middle of a regular 68K section. Also note that all
+// of the alignment pseudo-ops will have to be fixed this way.
+//
+// This *must* behave differently when in a RISC section, as following sloc
+// (instead of orgaddr) will fuck things up royally. Note that we do it this
+// way because you can embed RISC code in a 68K section, and have the origin
+// pointing to a different alignment in the RISC section than the 68K section.