+++ /dev/null
-//
-// Alternate GPU core... Testing purposes only!
-//
-
-//#include "gpu.h"
-
-// Random stuff from GPU.CPP
-
-/*static uint8 * gpu_ram_8;
-extern uint32 gpu_pc;
-static uint32 gpu_acc;
-static uint32 gpu_remain;
-static uint32 gpu_hidata;
-static uint32 gpu_flags;
-static uint32 gpu_matrix_control;
-static uint32 gpu_pointer_to_matrix;
-static uint32 gpu_data_organization;
-static uint32 gpu_control;
-static uint32 gpu_div_control;
-static uint8 gpu_flag_z, gpu_flag_n, gpu_flag_c;
-static uint8 gpu_alternate_flag_z, gpu_alternate_flag_n, gpu_alternate_flag_c;
-static uint32 * gpu_reg;
-static uint32 * gpu_alternate_reg;
-static uint32 * gpu_reg_bank_0;
-static uint32 * gpu_reg_bank_1;
-
-static uint32 gpu_opcode_first_parameter;
-static uint32 gpu_opcode_second_parameter;*/
-
-//
-
-const INT32 qtable[32] =
-{ 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
- 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 };
-
-const INT32 sqtable[32] =
-{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
- -16, -15, -14, -13, -12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1 };
-
-const UINT8 gpu_opcode_times[64] =
-{ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 1, 3, 1,18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 2, 2, 2, 2, 3, 6, 6, 4, 6, 6, 6, 1, 1, 1,
- 1, 2, 2, 2, 1, 1,20, 3, 3, 1, 6, 6, 2, 2, 3, 3 };
-
-UINT8 jump_condition[32][8];
-
-void gpu2_init(void)
-{
- memset(jump_condition, 0, 32 * 8 * sizeof(UINT8));
-
- for(int j=0; j<32; j++)
- {
- for(int i=0; i<8; i++)
- {
- UINT8 r = 1;
- if(j & 0x1) {
- if(i & 0x1)
- r = 0;
- }
- if(j & 0x2) {
- if(!(i & 0x1))
- r = 0;
- }
- if(j & 0x4) {
- if(i & (0x2 << (j >> 4)))
- r = 0;
- }
- if(j & 0x8) {
- if(!(i & (0x2 << (j >> 4))))
- r = 0;
- }
- jump_condition[j][i] = r;
- }
- }
-}
-
-// case 22: // ABS
-void opcode_abs(void)
-{
- int d = RN;
- if(d & 0x80000000) {
- d = abs(d);
- gpu_flag_c = 1;
- } else {
- gpu_flag_c = 0;
- }
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = 0;
-}
-
-// case 0: // ADD
-void opcode_add(void)
-{
- int s = RM;
- int d = RN;
- INT64 r = s + d;
- gpu_flag_c = r & 0x100000000 ? 1 : 0;
- RN = r;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 1: // ADDC
-void opcode_addc(void)
-{
- int s = RM;
- int d = RN;
- int c = gpu_flag_c;
- INT64 r = s + d + c;
- gpu_flag_c = r & 0x100000000 ? 1 : 0;
- RN = r;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 2: // ADDQ
-void opcode_addq(void)
-{
- int s = qtable[IMM_1];
- int d = RN;
- INT64 r = s + d;
- gpu_flag_c = r & 0x100000000 ? 1 : 0;
- RN = r;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 3: // ADDQT
-void opcode_addqt(void)
-{
- RN += qtable[IMM_1];
-}
-// break;
-// case 9: // AND
-void opcode_and(void)
-{
- RN &= RM;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 15: // BLCR
-void opcode_bclr(void)
-{
- RN &= ~(1 << IMM_1);
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 14: // BSET
-void opcode_bset(void)
-{
- RN |= 1 << IMM_1;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 13: // BTST
-void opcode_btst(void)
-{
- gpu_flag_z = RN & (1 << IMM_1) ? 0 : 1;
-}
-// break;
-// case 30: // CMP
-void opcode_cmp(void)
-{
- int s = RM;
- int d = RN;
- gpu_flag_c = (unsigned int)d < (unsigned int)s;
- d -= s;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 31: // CMPQ
-void opcode_cmpq(void)
-{
- int s = sqtable[IMM_1];
- int d = RN;
- gpu_flag_c = (unsigned int)d < (unsigned int)s;
- d -= s;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 21: // DIV
-void opcode_div(void)
-{
- if(RM != 0) {
- if(gpu_div_control == 0) {
- UINT32 q = RN;
- UINT32 d = RM;
- UINT32 r = q / d;
- UINT32 r2 = q % d;
- RN = r;
- gpu_remain = r2;
- } else {
- UINT64 q = (UINT64)(RN)<<16;
- UINT64 d = (UINT64)(RM);
- UINT32 r = (UINT64)(q / d);
- UINT32 r2 = (UINT64)(q % d);
- RN = r;
- gpu_remain = r2;
- }
- }
-}
-// break;
-// case 20: // IMACN
-void opcode_imacn(void)
-{
- short s = RM;
- short d = RN;
- int r = s * d;
- gpu_acc += r;
-}
-// break;
-// case 17: // IMULT
-void opcode_imult(void)
-{
- short s = RM;
- short d = RN;
- int r = s * d;
- RN = r;
- gpu_flag_z = r == 0 ? 1 : 0;
- gpu_flag_n = r & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 18: // IMULTN
-void opcode_imultn(void)
-{
- short s = RM;
- short d = RN;
- int r = s * d;
- gpu_acc = r;
- gpu_flag_z = r == 0 ? 1 : 0;
- gpu_flag_n = r & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 53: // JR;
-void opcode_jr(void)
-{
- UINT32 dw = (gpu_flag_z & 0x1) | ((gpu_flag_n & 0x1) << 2) | ((gpu_flag_c & 0x1) << 1);
- if (jump_condition[IMM_2][dw])
- {
-if (gpu_start_log)
- fprintf(log_get(), " --> JR: Branch taken. ");
- signed int offset = IMM_1 & 0x10 ? (0xFFFFFFF0 | (IMM_1 & 0xF)) : (IMM_1 & 0xF);
- UINT32 delayed_jump_address = gpu_pc + 2 + (offset * 2);
-// delayed_jump = 1;
- gpu_pc += 2;
- gpu_exec(1);
-// gpu_pc = delayed_jump_address;
- gpu_pc = delayed_jump_address - 2;
- }
-}
-// break;
-// case 52: // JUMP
-void opcode_jump(void)
-{
- UINT32 dw = (gpu_flag_z & 0x1) | ((gpu_flag_n & 0x1) << 2) | ((gpu_flag_c & 0x1) << 1);
- if (jump_condition[IMM_2][dw])
- {
-if (gpu_start_log)
- fprintf(log_get(), " --> JUMP: Branch taken. ");
- UINT32 delayed_jump_address = RM & 0xFFFFFE;
-// delayed_jump = 1;
- gpu_pc += 2;
- gpu_exec(1);
-// gpu_pc = delayed_jump_address;
- gpu_pc = delayed_jump_address - 2;
- }
-}
-// break;
-// case 41: // LOAD
-void opcode_load(void)
-{
- UINT32 address = RM;
- if(address >= 0xF03000 && address < 0xF04000) {
-// RN = _rotl(*(UINT32*)(&MEM[address]),16);
- RN = gpu_long_read(address);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// RN = _rotl(*(UINT32*)(&MEM[address-0x8000]),16);
- RN = gpu_long_read(address-0x8000);
- } else {
-// RN = ReadMem32(address);
- RN = jaguar_long_read(address);
- }
-}
-// break;
-// case 43: // LOAD (R14+m)
-void opcode_load_r14_indexed(void)
-{
- UINT32 address = gpu_reg[14] + (qtable[IMM_1] << 2);
- if(address >= 0xF03000 && address < 0xF04000) {
-// RN = _rotl(*(UINT32*)(&MEM[address]),16);
- RN = gpu_long_read(address);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// RN = _rotl(*(UINT32*)(&MEM[address-0x8000]),16);
- RN = gpu_long_read(address-0x8000);
- } else {
-// RN = ReadMem32(address);
- RN = jaguar_long_read(address);
- }
-}
-// break;
-// case 44: // LOAD (R15+m)
-void opcode_load_r15_indexed(void)
-{
- UINT32 address = gpu_reg[15] + (qtable[IMM_1] << 2);
- if(address >= 0xF03000 && address < 0xF04000) {
-// RN = _rotl(*(UINT32*)(&MEM[address]),16);
- RN = gpu_long_read(address);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// RN = _rotl(*(UINT32*)(&MEM[address-0x8000]),16);
- RN = gpu_long_read(address-0x8000);
- } else {
-// RN = ReadMem32(address);
- RN = jaguar_long_read(address);
- }
-}
-// break;
-// case 58: // LOAD (R14+Rm)
-void opcode_load_r14_ri(void)
-{
- UINT32 address = gpu_reg[14] + RM;
- if(address >= 0xF03000 && address < 0xF04000) {
-// RN = _rotl(*(UINT32*)(&MEM[address]),16);
- RN = gpu_long_read(address);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// RN = _rotl(*(UINT32*)(&MEM[address-0x8000]),16);
- RN = gpu_long_read(address-0x8000);
- } else {
-// RN = ReadMem32(address);
- RN = jaguar_long_read(address);
- }
-}
-// break;
-// case 59: // LOAD (R15+Rm)
-void opcode_load_r15_ri(void)
-{
- UINT32 address = gpu_reg[15] + RM;
- if(address >= 0xF03000 && address < 0xF04000) {
-// RN = _rotl(*(UINT32*)(&MEM[address]),16);
- RN = gpu_long_read(address);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// RN = _rotl(*(UINT32*)(&MEM[address-0x8000]),16);
- RN = gpu_long_read(address-0x8000);
- } else {
-// RN = ReadMem32(address);
- RN = jaguar_long_read(address);
- }
-}
-// break;
-// case 39: // LOADB
-void opcode_loadb(void)
-{
- if(RM >= 0xF03000 && RM < 0xF04000) {
-// RN = ReadMem32(RM);
- RN = gpu_long_read(RM);
- } else {
-// RN = ReadMem8(RM);
- RN = jaguar_byte_read(RM);
- }
-}
-// break;
-// case 40: // LOADW
-void opcode_loadw(void)
-{
- if(RM >= 0xF03000 && RM < 0xF04000) {
-// RN = ReadMem32(RM);
- RN = gpu_long_read(RM);
- } else {
-// RN = ReadMem16(RM);
- RN = jaguar_word_read(RM);
- }
-}
-// break;
-// case 42: // LOADP
-void opcode_loadp(void)
-{
- if(RM >= 0xF03000 && RM < 0xF04000) {
-// RN = ReadMem32(RM);
- RN = gpu_long_read(RM);
- } else {
-// RN = ReadMem32(RM);
-// gpu_hidata = ReadMem32(RM+4);
- RN = gpu_long_read(RM);
- gpu_hidata = gpu_long_read(RM + 4);
- }
-}
-// break;
-// case 34: // MOVE
-void opcode_move(void)
-{
- RN = RM;
-}
-// break;
-// case 51: // MOVE PC,Rn
-void opcode_move_pc(void)
-{
- RN = gpu_pc;
-}
-// break;
-// case 37: // MOVEFA
-void opcode_movefa(void)
-{
- RN = gpu_alternate_reg[IMM_1];
-}
-// break;
-// case 38: // MOVEI
-void opcode_movei(void)
-{
- // This instruction is followed by 32-bit value in LSW / MSW format...
-// RN = (uint32)gpu_word_read(gpu_pc) | ((uint32)gpu_word_read(gpu_pc + 2) << 16);
-// gpu_pc += 4;
-// RN = _rotl(*(UINT32*)(&MEM[address]),16);
-// RN = *(UINT32*)(&MEM[gpu_pc+2]);
- RN = _rotl(gpu_long_read(gpu_pc + 2), 16);
- gpu_pc += 4;
-}
-// break;
-// case 35: // MOVEQ
-void opcode_moveq(void)
-{
- RN = IMM_1;
-}
-// break;
-// case 36: // MOVETA
-void opcode_moveta(void)
-{
- gpu_alternate_reg[IMM_2] = RM;
-}
-// break;
-// case 55: // MTOI
-void opcode_mtoi(void)
-{
- int d = RN & 0x7FFFFF;
- if(RN & 0x80000000) {
- d |= 0xFF800000;
- }
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 16: // MULT
-void opcode_mult(void)
-{
- unsigned short s = RM;
- unsigned short d = RN;
- int r = s * d;
- RN = r;
- gpu_flag_z = r == 0 ? 1 : 0;
- gpu_flag_n = r & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 54: // MMULT
-void opcode_mmult(void)
-{
- int size = gpu_matrix_control & 0xF;
- int address = gpu_pointer_to_matrix;
- int add;
- if (gpu_matrix_control & 0x10)
- add = size * 4;
- else
- add = 4;
- int result = 0;
- for(int i=0; i<size; i++)
- {
- short m, r;
-// m = ReadMem16(address+2);
- m = gpu_word_read(address + 2);
- if (i & 0x1)
- r = gpu_alternate_reg[IMM_1+(i>>1)] >> 16;
- else
- r = (gpu_alternate_reg[IMM_1+(i>>1)] & 0xFFFF);
- result += (int)(r * m);
-/* int mult = r*m;
- __asm {
- mov eax,[result]
- mov edx,[mult]
- add eax,edx
- setc [gpu_flag_c]
- mov [result],eax
- }*/
-
- address += add;
- }
- RN = result;
- gpu_flag_n = (result < 0) ? 1 : 0;
- gpu_flag_z = (result == 0) ? 1 : 0;
-}
-// break;
-// case 8: // NEG
-void opcode_neg(void)
-{
- int s = 0;
- int d = RN;
- gpu_flag_c = d - s < d;
- d = s - d;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 57: // NOP
-void opcode_nop(void)
-{
-}
-// break;
-// case 56: // NORMI
-void opcode_normi(void)
-{
- /*unsigned int d = RN;
- int r = 0;
- while ((d & 0xffc00000) == 0)
- {
- d <<= 1;
- r--;
- }
- while ((d & 0xff800000) != 0)
- {
- d >>= 1;
- r++;
- }
- RN = r;
- gpu_flag_z = r == 0 ? 1 : 0;
- gpu_flag_n = r & 0x80000000 ? 1 : 0;*/
- RN = 0;
-}
-// break;
-// case 12: // NOT
-void opcode_not(void)
-{
- int d = RN;
- d ^= 0xFFFFFFFF;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 10: // OR
-void opcode_or(void)
-{
- int s = RM;
- int d = RN;
- d |= s;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 63: // PACK / UNPACK
-void opcode_pack(void)
-{
- if (IMM_1 == 0)
- {
- int c1 = (RN & 0x3C00000) >> 10;
- int c2 = (RN & 0x1E000) >> 5;
- int y = (RN & 0xFF);
- RN = c1 | c2 | y;
- }
- else
- {
- int c1 = (RN & 0xF000) << 10;
- int c2 = (RN & 0xF00) << 5;
- int y = (RN & 0xFF);
- RN = c1 | c2 | y;
- }
-}
-// break;
-// case 19: // RESMAC
-void opcode_resmac(void)
-{
- RN = gpu_acc;
-}
-// break;
-// case 28: // ROR
-void opcode_ror(void)
-{
- unsigned int d = RN;
- int shift = RM;
- gpu_flag_c = d & 0x80000000 ? 1 : 0;
- d = _rotr(d, shift);
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 29: // RORQ
-void opcode_rorq(void)
-{
- unsigned int d = RN;
- int shift = qtable[IMM_1];
- gpu_flag_c = d & 0x80000000 ? 1 : 0;
- d = _rotr(d, shift);
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 32: // SAT8
-void opcode_sat8(void)
-{
- int d = RN;
- if(d < 0)
- d = 0;
- if(d > 255)
- d = 255;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = 0;
-}
-// break;
-// case 33: // SAT16
-void opcode_sat16(void)
-{
- int d = RN;
- if(d < 0)
- d = 0;
- if(d > 65535)
- d = 65535;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = 0;
-}
-// break;
-// case 62: // SAT24
-void opcode_sat24(void)
-{
- int d = RN;
- if (d < 0)
- d = 0;
- if (d > 16777215)
- d = 16777215;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = 0;
-}
-// break;
-// case 23: // SH
-void opcode_sh(void)
-{
- int shift = RM;
- if (shift & 0x80000000)
- {
- gpu_flag_c = RN & 0x80000000 ? 1 : 0;
- UINT32 d = RN;
- d <<= 0-shift;
- RN = d;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
- }
- else
- {
- gpu_flag_c = RN & 0x1 ? 1 : 0;
- UINT32 d = RN;
- d >>= shift;
- RN = d;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
- }
-}
-// break;
-// case 26: // SHA
-void opcode_sha(void)
-{
- int shift = RM;
- if(shift & 0x80000000) {
- gpu_flag_c = RN & 0x80000000 ? 1 : 0;
- INT32 d = RN;
- d <<= 0-shift;
- RN = d;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
- } else {
- gpu_flag_c = RN & 0x1 ? 1 : 0;
- INT32 d = RN;
- d >>= shift;
- RN = d;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
- }
-}
-// break;
-// case 27: // SHARQ
-void opcode_sharq(void)
-{
- INT32 d = RN;
- int shift = qtable[IMM_1];
- gpu_flag_c = d & 0x1 ? 1 : 0;
- d >>= shift;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 24: // SHLQ
-void opcode_shlq(void)
-{
- UINT32 d = RN;
- int shift = 32 - IMM_1;
- gpu_flag_c = d & 0x80000000 ? 1 : 0;
- d <<= shift;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
- // case 25: // SHRQ
-void opcode_shrq(void)
-{
- UINT32 d = RN;
- int shift = qtable[IMM_1];
- gpu_flag_c = d & 0x1 ? 1 : 0;
- d >>= shift;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 47: // STORE
-void opcode_store(void)
-{
- UINT32 address = RM;
- if(address >= 0xF03000 && address < 0xF04000) {
-// *(UINT32*)(&MEM[address]) = _rotl(RN,16);
- gpu_long_write(address, RN);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// *(UINT32*)(&MEM[address-0x8000]) = _rotl(RN,16);
- gpu_long_write(address-0x8000, RN);
- } else {
-// WriteMem32(address,RN);
- jaguar_long_write(address, RN);
- }
-}
-// break;
-// case 49: // STORE (R14+m)
-void opcode_store_r14_indexed(void)
-{
- UINT32 address = gpu_reg[14] + (qtable[IMM_1] << 2);
- if(address >= 0xF03000 && address < 0xF04000) {
-// *(UINT32*)(&MEM[address]) = _rotl(RN,16);
- gpu_long_write(address, RN);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// *(UINT32*)(&MEM[address-0x8000]) = _rotl(RN,16);
- gpu_long_write(address-0x8000, RN);
- } else {
-// WriteMem32(address,RN);
- jaguar_long_write(address, RN);
- }
-}
-// break;
-// case 50: // STORE (R15+m)
-void opcode_store_r15_indexed(void)
-{
- UINT32 address = gpu_reg[15] + (qtable[IMM_1] << 2);
- if(address >= 0xF03000 && address < 0xF04000) {
-// *(UINT32*)(&MEM[address]) = _rotl(RN,16);
- gpu_long_write(address, RN);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// *(UINT32*)(&MEM[address-0x8000]) = _rotl(RN,16);
- gpu_long_write(address-0x8000, RN);
- } else {
-// WriteMem32(address,RN);
- jaguar_long_write(address, RN);
- }
-}
-// break;
-// case 60: // STORE (R14+Rm)
-void opcode_store_r14_ri(void)
-{
- UINT32 address = gpu_reg[14] + RM;
- if(address >= 0xF03000 && address < 0xF04000) {
-// *(UINT32*)(&MEM[address]) = _rotl(RN,16);
- gpu_long_write(address, RN);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// *(UINT32*)(&MEM[address-0x8000]) = _rotl(RN,16);
- gpu_long_write(address-0x8000, RN);
- } else {
-// WriteMem32(address,RN);
- jaguar_long_write(address, RN);
- }
-}
-// break;
-// case 61: // STORE (R15+Rm)
-void opcode_store_r15_ri(void)
-{
- UINT32 address = gpu_reg[15] + RM;
- if(address >= 0xF03000 && address < 0xF04000) {
-// *(UINT32*)(&MEM[address]) = _rotl(RN,16);
- gpu_long_write(address, RN);
- } else if(address >= 0xF0B000 && address < 0xF0C000) {
-// *(UINT32*)(&MEM[address-0x8000]) = _rotl(RN,16);
- gpu_long_write(address-0x8000, RN);
- } else {
-// WriteMem32(address,RN);
- jaguar_long_write(address, RN);
- }
-}
-// break;
-// case 45: // STOREB
-void opcode_storeb(void)
-{
- if(RM>0xF03000 && RM<0xF04000) {
-// WriteMem32(RM,RN);
- gpu_long_write(RM, RN);
- } else {
-// WriteMem8(RM,(UINT8)RN);
- jaguar_byte_write(RM, (UINT8)RN);
- }
-}
-// break;
-// case 46: // STOREW
-void opcode_storew(void)
-{
- if(RM>0xF03000 && RM<0xF04000) {
-// WriteMem32(RM,RN);
- gpu_long_write(RM, RN);
- } else {
-// WriteMem16(RM,(WORD)RN);
- jaguar_word_write(RM, (UINT16)RN);
- }
-}
-// break;
-// case 48: // STOREP
-void opcode_storep(void)
-{
- if (RM>0xF03000 && RM<0xF04000)
- {
-// WriteMem32(RM,RN);
- gpu_long_write(RM, RN);
- }
- else
- {
-// WriteMem32(RM,RN);
-// WriteMem32(RM+4,gpu_hidata);
- jaguar_long_write(RM, RN);
- jaguar_long_write(RM + 4, gpu_hidata);
- }
-}
-// break;
-// case 4: // SUB
-void opcode_sub(void)
-{
- int s = RM;
- int d = RN;
- INT64 r = d - s;
- gpu_flag_c = r & 0x100000000 ? 1 : 0;
- RN = r;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 5: // SUBC
-void opcode_subc(void)
-{
- int s = RM;
- int d = RN;
- int c = gpu_flag_c;
- INT64 r = d - s - c;
- gpu_flag_c = r & 0x100000000 ? 1 : 0;
- RN = r;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 6: // SUBQ
-void opcode_subq(void)
-{
- int s = qtable[IMM_1];
- int d = RN;
- INT64 r = d - s;
- gpu_flag_c = r & 0x100000000 ? 1 : 0;
- RN = r;
- gpu_flag_z = RN == 0 ? 1 : 0;
- gpu_flag_n = RN & 0x80000000 ? 1 : 0;
-}
-// break;
-// case 7: // SUBQT
-void opcode_subqt(void)
-{
- RN -= qtable[IMM_1];
-}
-// break;
-// case 11: // XOR
-void opcode_xor(void)
-{
- int s = RM;
- int d = RN;
- d ^= s;
- RN = d;
- gpu_flag_z = d == 0 ? 1 : 0;
- gpu_flag_n = d & 0x80000000 ? 1 : 0;
-}
+++ /dev/null
-//
-// Aaron Giles GPU core
-//
-
-static UINT8 * condition_table = NULL;
-static UINT16 * mirror_table = NULL;
-static const UINT32 convert_zero[32] =
-{ 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 };
-
-// Initialization
-
-void gpu3_init(void)
-{
- int i, j;
-
- /* allocate the mirror table */
- if (!mirror_table)
- mirror_table = (UINT16 *)malloc(65536 * sizeof(mirror_table[0]));
-
- /* fill in the mirror table */
- if (mirror_table)
- for (i = 0; i < 65536; i++)
- mirror_table[i] = ((i >> 15) & 0x0001) | ((i >> 13) & 0x0002) |
- ((i >> 11) & 0x0004) | ((i >> 9) & 0x0008) |
- ((i >> 7) & 0x0010) | ((i >> 5) & 0x0020) |
- ((i >> 3) & 0x0040) | ((i >> 1) & 0x0080) |
- ((i << 1) & 0x0100) | ((i << 3) & 0x0200) |
- ((i << 5) & 0x0400) | ((i << 7) & 0x0800) |
- ((i << 9) & 0x1000) | ((i << 11) & 0x2000) |
- ((i << 13) & 0x4000) | ((i << 15) & 0x8000);
-
- /* allocate the condition table */
- if (!condition_table)
- condition_table = (UINT8 *)malloc(32 * 8 * sizeof(condition_table[0]));
-
- /* fill in the condition table */
- if (condition_table)
- for (i = 0; i < 8; i++)
- for (j = 0; j < 32; j++)
- {
- int result = 1;
- if (j & 1)
- if (i & ZERO_FLAG) result = 0;
- if (j & 2)
- if (!(i & ZERO_FLAG)) result = 0;
- if (j & 4)
- if (i & (CARRY_FLAG << (j >> 4))) result = 0;
- if (j & 8)
- if (!(i & (CARRY_FLAG << (j >> 4)))) result = 0;
- condition_table[i * 32 + j] = result;
- }
-}
-
-/*###################################################################################################
-** OPCODES
-**#################################################################################################*/
-
-void abs_rn(void)
-{
- int dreg = IMM_2;
- UINT32 res = gpu_reg[dreg];
- CLR_ZNC;
- if (res & 0x80000000)
- {
- gpu_reg[dreg] = res = -res;
- gpu_flag_c = 1;
- }
- SET_Z(res);
-}
-
-void add_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 + r1;
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_ADD(r2,r1,res);
-}
-
-void addc_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 + r1 + (gpu_flag_c);
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_ADD(r2,r1,res);
-}
-
-void addq_n_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 + r1;
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_ADD(r2,r1,res);
-}
-
-void addqmod_n_rn(void) /* DSP only */
-{
-/* int dreg = IMM_2;
- UINT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 + r1;
- res = (res & ~jaguar.ctrl[D_MOD]) | (r2 & ~jaguar.ctrl[D_MOD]);
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_ADD(r2,r1,res);*/
-}
-
-void addqt_n_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 + r1;
- gpu_reg[dreg] = res;
-}
-
-void and_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 & r1;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void bclr_n_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = IMM_1;
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 & ~(1 << r1);
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void bset_n_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = IMM_1;
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 | (1 << r1);
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void btst_n_rn(void)
-{
- UINT32 r1 = IMM_1;
- UINT32 r2 = gpu_reg[IMM_2];
- CLR_Z; gpu_flag_z = (~r2 >> r1) & 1;
-}
-
-void cmp_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[IMM_2];
- UINT32 res = r2 - r1;
- CLR_ZNC; SET_ZNC_SUB(r2,r1,res);
-}
-
-void cmpq_n_rn(void)
-{
- UINT32 r1 = (INT8)(gpu_instruction >> 2) >> 3;
- UINT32 r2 = gpu_reg[IMM_2];
- UINT32 res = r2 - r1;
- CLR_ZNC; SET_ZNC_SUB(r2,r1,res);
-}
-
-void div_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- if (r1)
- {
- if (gpu_div_control & 1)
- {
- gpu_reg[dreg] = ((UINT64)r2 << 16) / r1;
- gpu_remain = ((UINT64)r2 << 16) % r1;
- }
- else
- {
- gpu_reg[dreg] = r2 / r1;
- gpu_remain = r2 % r1;
- }
- }
- else
- gpu_reg[dreg] = 0xffffffff;
-}
-
-void illegal(void)
-{
-}
-
-void imacn_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[IMM_2];
- gpu_acc += (INT64)((INT16)r1 * (INT16)r2);
-// logerror("Unexpected IMACN instruction!\n");
-}
-
-void imult_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = (INT16)r1 * (INT16)r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void imultn_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = (INT16)r1 * (INT16)r2;
- gpu_acc = (INT32)res;
- CLR_ZN; SET_ZN(res);
-
-// gpu_instruction = ROPCODE(gpu_pc);
- gpu_instruction = gpu_word_read(gpu_pc);
- while ((gpu_instruction >> 10) == 20)
- {
- r1 = gpu_reg[IMM_1];
- r2 = gpu_reg[IMM_2];
- gpu_acc += (INT64)((INT16)r1 * (INT16)r2);
- gpu_pc += 2;
-// gpu_instruction = ROPCODE(gpu_pc);
- gpu_instruction = gpu_word_read(gpu_pc);
- }
- if ((gpu_instruction >> 10) == 19)
- {
- gpu_pc += 2;
- gpu_reg[IMM_2] = (UINT32)gpu_acc;
- }
-}
-
-void jr_cc_n(void)
-{
-// if (CONDITION(IMM_2))
- uint32 jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z;
- if (BRANCH_CONDITION(IMM_2))
- {
- INT32 r1 = (INT8)((gpu_instruction >> 2) & 0xf8) >> 2;
- UINT32 newpc = gpu_pc + r1;
-/* CALL_MAME_DEBUG;
- gpu_instruction = ROPCODE(gpu_pc);
- gpu_pc = newpc;
- (*jaguar.table[gpu_instruction >> 10])();
-
- jaguar_icount -= 3; // 3 wait states guaranteed*/
- gpu_exec(1);
- gpu_pc = newpc;
- }
-}
-
-void jump_cc_rn(void)
-{
-// if (CONDITION(IMM_2))
- uint32 jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z;
- if (BRANCH_CONDITION(IMM_2))
- {
- UINT8 reg = IMM_1;
-
- // special kludge for risky code in the cojag DSP interrupt handlers
-/* UINT32 newpc = (jaguar_icount == bankswitch_icount) ? gpu_alternate_reg[reg] : gpu_reg[reg];
- CALL_MAME_DEBUG;
- gpu_instruction = ROPCODE(gpu_pc);
- gpu_pc = newpc;
- (*jaguar.table[gpu_instruction >> 10])();
-
- jaguar_icount -= 3; // 3 wait states guaranteed*/
- UINT32 newpc = gpu_reg[reg];
- gpu_exec(1);
- gpu_pc = newpc;
- }
-}
-
-void load_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// gpu_reg[IMM_2] = READLONG(r1);
- gpu_reg[IMM_2] = gpu_long_read(r1);
-}
-
-void load_r14n_rn(void)
-{
- UINT32 r1 = convert_zero[IMM_1];
-// gpu_reg[IMM_2] = READLONG(gpu_reg[14] + 4 * r1);
- gpu_reg[IMM_2] = gpu_long_read(gpu_reg[14] + 4 * r1);
-}
-
-void load_r15n_rn(void)
-{
- UINT32 r1 = convert_zero[IMM_1];
-// gpu_reg[IMM_2] = READLONG(gpu_reg[15] + 4 * r1);
- gpu_reg[IMM_2] = gpu_long_read(gpu_reg[15] + 4 * r1);
-}
-
-void load_r14rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// gpu_reg[IMM_2] = READLONG(gpu_reg[14] + r1);
- gpu_reg[IMM_2] = gpu_long_read(gpu_reg[14] + r1);
-}
-
-void load_r15rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// gpu_reg[IMM_2] = READLONG(gpu_reg[15] + r1);
- gpu_reg[IMM_2] = gpu_long_read(gpu_reg[15] + r1);
-}
-
-void loadb_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// gpu_reg[IMM_2] = READBYTE(r1);
- gpu_reg[IMM_2] = gpu_byte_read(r1);
-}
-
-void loadw_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// gpu_reg[IMM_2] = READWORD(r1);
- gpu_reg[IMM_2] = gpu_word_read(r1);
-}
-
-void loadp_rn_rn(void) /* GPU only */
-{
- UINT32 r1 = gpu_reg[IMM_1];
- // Is this a bug? I'm sure he meant to read DWORDs here, not just WORDs...
-// gpu_hidata = READWORD(r1);
-// gpu_reg[IMM_2] = READWORD(r1+4);
- gpu_hidata = gpu_long_read(r1);
- gpu_reg[IMM_2] = gpu_long_read(r1+4);
-}
-
-void mirror_rn(void) /* DSP only */
-{
-/* int dreg = IMM_2;
- UINT32 r1 = gpu_reg[dreg];
- UINT32 res = (mirror_table[r1 & 0xffff] << 16) | mirror_table[r1 >> 16];
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);*/
-}
-
-void mmult_rn_rn(void)
-{
- int count = gpu_matrix_control & 15, i;
- int sreg = IMM_1;
- int dreg = IMM_2;
- UINT32 addr = gpu_pointer_to_matrix;
- INT64 accum = 0;
- UINT32 res;
-
- if (!(gpu_matrix_control & 0x10))
- {
- for (i = 0; i < count; i++)
- {
-// accum += (INT16)(gpu_reg_bank_1[sreg + i/2] >> (16 * ((i & 1) ^ 1))) * (INT16)READWORD(addr);
- accum += (INT16)(gpu_reg_bank_1[sreg + i/2] >> (16 * ((i & 1) ^ 1))) * (INT16)gpu_word_read(addr);
- addr += 2;
- }
- }
- else
- {
- for (i = 0; i < count; i++)
- {
-// accum += (INT16)(gpu_reg_bank_1[sreg + i/2] >> (16 * ((i & 1) ^ 1))) * (INT16)READWORD(addr);
- accum += (INT16)(gpu_reg_bank_1[sreg + i/2] >> (16 * ((i & 1) ^ 1))) * (INT16)gpu_word_read(addr);
- addr += 2 * count;
- }
- }
- gpu_reg[dreg] = res = (UINT32)accum;
- CLR_ZN; SET_ZN(res);
-}
-
-void move_rn_rn(void)
-{
- gpu_reg[IMM_2] = gpu_reg[IMM_1];
-}
-
-void move_pc_rn(void)
-{
-// gpu_reg[IMM_2] = jaguar.ppc;
- gpu_reg[IMM_2] = gpu_pc - 2;
-}
-
-void movefa_rn_rn(void)
-{
- gpu_reg[IMM_2] = gpu_alternate_reg[IMM_1];
-}
-
-void movei_n_rn(void)
-{
-// UINT32 res = ROPCODE(gpu_pc) | (ROPCODE(gpu_pc + 2) << 16);
- UINT32 res = gpu_word_read(gpu_pc) | (gpu_word_read(gpu_pc + 2) << 16);
- gpu_pc += 4;
- gpu_reg[IMM_2] = res;
-}
-
-void moveq_n_rn(void)
-{
- gpu_reg[IMM_2] = IMM_1;
-}
-
-void moveta_rn_rn(void)
-{
- gpu_alternate_reg[IMM_2] = gpu_reg[IMM_1];
-}
-
-void mtoi_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
- gpu_reg[IMM_2] = (((INT32)r1 >> 8) & 0xff800000) | (r1 & 0x007fffff);
-}
-
-void mult_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = (UINT16)r1 * (UINT16)r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void neg_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = -r2;
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_SUB(0,r2,res);
-}
-
-void nop(void)
-{
-}
-
-void normi_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 res = 0;
- while ((r1 & 0xffc00000) == 0)
- {
- r1 <<= 1;
- res--;
- }
- while ((r1 & 0xff800000) != 0)
- {
- r1 >>= 1;
- res++;
- }
- gpu_reg[IMM_2] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void not_rn(void)
-{
- int dreg = IMM_2;
- UINT32 res = ~gpu_reg[dreg];
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void or_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r1 | r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void pack_rn(void) /* GPU only */
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res;
- if (r1 == 0) /* PACK */
- res = ((r2 >> 10) & 0xf000) | ((r2 >> 5) & 0x0f00) | (r2 & 0xff);
- else /* UNPACK */
- res = ((r2 & 0xf000) << 10) | ((r2 & 0x0f00) << 5) | (r2 & 0xff);
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void resmac_rn(void)
-{
- gpu_reg[IMM_2] = (UINT32)gpu_acc;
-}
-
-void ror_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1] & 31;
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = (r2 >> r1) | (r2 << (32 - r1));
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZN(res); gpu_flag_c = (r2 >> 31) & 0x01;
-}
-
-void rorq_n_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = (r2 >> r1) | (r2 << (32 - r1));
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZN(res); gpu_flag_c = (r2 >> 31) & 0x01;
-}
-
-void sat8_rn(void) /* GPU only */
-{
- int dreg = IMM_2;
- INT32 r2 = gpu_reg[dreg];
- UINT32 res = (r2 < 0) ? 0 : (r2 > 255) ? 255 : r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void sat16_rn(void) /* GPU only */
-{
- int dreg = IMM_2;
- INT32 r2 = gpu_reg[dreg];
- UINT32 res = (r2 < 0) ? 0 : (r2 > 65535) ? 65535 : r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void sat16s_rn(void) /* DSP only */
-{
-/* int dreg = IMM_2;
- INT32 r2 = gpu_reg[dreg];
- UINT32 res = (r2 < -32768) ? -32768 : (r2 > 32767) ? 32767 : r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);*/
-}
-
-void sat24_rn(void) /* GPU only */
-{
- int dreg = IMM_2;
- INT32 r2 = gpu_reg[dreg];
- UINT32 res = (r2 < 0) ? 0 : (r2 > 16777215) ? 16777215 : r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
-
-void sat32s_rn(void) /* DSP only */
-{
-/* int dreg = IMM_2;
- INT32 r2 = (UINT32)gpu_reg[dreg];
- INT32 temp = gpu_acc >> 32;
- UINT32 res = (temp < -1) ? (INT32)0x80000000 : (temp > 0) ? (INT32)0x7fffffff : r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);*/
-}
-
-void sh_rn_rn(void)
-{
- int dreg = IMM_2;
- INT32 r1 = (INT32)gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res;
-
- CLR_ZNC;
- if (r1 < 0)
- {
- res = (r1 <= -32) ? 0 : (r2 << -r1);
- gpu_flag_c = (r2 >> 31) & 0x01;
- }
- else
- {
- res = (r1 >= 32) ? 0 : (r2 >> r1);
- gpu_flag_c = r2 & 0x01;
- }
- gpu_reg[dreg] = res;
- SET_ZN(res);
-}
-
-void sha_rn_rn(void)
-{
- int dreg = IMM_2;
- INT32 r1 = (INT32)gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res;
-
- CLR_ZNC;
- if (r1 < 0)
- {
- res = (r1 <= -32) ? 0 : (r2 << -r1);
- gpu_flag_c = (r2 >> 31) & 0x01;
- }
- else
- {
- res = (r1 >= 32) ? ((INT32)r2 >> 31) : ((INT32)r2 >> r1);
-// jaguar.FLAGS |= (r2 << 1) & 2;
- gpu_flag_c = r2 & 0x01;
- }
- gpu_reg[dreg] = res;
- SET_ZN(res);
-}
-
-void sharq_n_rn(void)
-{
- int dreg = IMM_2;
- INT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = (INT32)r2 >> r1;
- gpu_reg[dreg] = res;
-// CLR_ZNC; SET_ZN(res); jaguar.FLAGS |= (r2 << 1) & 2;
- CLR_ZNC; SET_ZN(res); gpu_flag_c = r2 & 0x01;
-}
-
-void shlq_n_rn(void)
-{
- int dreg = IMM_2;
- INT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 << (32 - r1);
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZN(res); gpu_flag_c = (r2 >> 31) & 0x01;
-}
-
-void shrq_n_rn(void)
-{
- int dreg = IMM_2;
- INT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 >> r1;
- gpu_reg[dreg] = res;
-// CLR_ZNC; SET_ZN(res); jaguar.FLAGS |= (r2 << 1) & 2;
- CLR_ZNC; SET_ZN(res); gpu_flag_c = r2 & 0x01;
-}
-
-void store_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// WRITELONG(r1, gpu_reg[IMM_2]);
- gpu_long_write(r1, gpu_reg[IMM_2]);
-}
-
-void store_rn_r14n(void)
-{
- UINT32 r1 = convert_zero[IMM_1];
-// WRITELONG(gpu_reg[14] + r1 * 4, gpu_reg[IMM_2]);
- gpu_long_write(gpu_reg[14] + r1 * 4, gpu_reg[IMM_2]);
-}
-
-void store_rn_r15n(void)
-{
- UINT32 r1 = convert_zero[IMM_1];
-// WRITELONG(gpu_reg[15] + r1 * 4, gpu_reg[IMM_2]);
- gpu_long_write(gpu_reg[15] + r1 * 4, gpu_reg[IMM_2]);
-}
-
-void store_rn_r14rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// WRITELONG(gpu_reg[14] + r1, gpu_reg[IMM_2]);
- gpu_long_write(gpu_reg[14] + r1, gpu_reg[IMM_2]);
-}
-
-void store_rn_r15rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// WRITELONG(gpu_reg[15] + r1, gpu_reg[IMM_2]);
- gpu_long_write(gpu_reg[15] + r1, gpu_reg[IMM_2]);
-}
-
-void storeb_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// WRITEBYTE(r1, gpu_reg[IMM_2]);
- gpu_byte_write(r1, gpu_reg[IMM_2]);
-}
-
-void storew_rn_rn(void)
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// WRITEWORD(r1, gpu_reg[IMM_2]);
- gpu_word_write(r1, gpu_reg[IMM_2]);
-}
-
-void storep_rn_rn(void) /* GPU only */
-{
- UINT32 r1 = gpu_reg[IMM_1];
-// WRITELONG(r1, gpu_hidata);
-// WRITELONG(r1+4, gpu_reg[IMM_2]);
- gpu_long_write(r1, gpu_hidata);
- gpu_long_write(r1+4, gpu_reg[IMM_2]);
-}
-
-void sub_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 - r1;
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_SUB(r2,r1,res);
-}
-
-void subc_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 - r1 - (gpu_flag_c);
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_SUB(r2,r1,res);
-}
-
-void subq_n_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 - r1;
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_SUB(r2,r1,res);
-}
-
-void subqmod_n_rn(void) /* DSP only */
-{
-/* int dreg = IMM_2;
- UINT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 - r1;
- res = (res & ~jaguar.ctrl[D_MOD]) | (r2 & ~jaguar.ctrl[D_MOD]);
- gpu_reg[dreg] = res;
- CLR_ZNC; SET_ZNC_SUB(r2,r1,res);*/
-}
-
-void subqt_n_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = convert_zero[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r2 - r1;
- gpu_reg[dreg] = res;
-}
-
-void xor_rn_rn(void)
-{
- int dreg = IMM_2;
- UINT32 r1 = gpu_reg[IMM_1];
- UINT32 r2 = gpu_reg[dreg];
- UINT32 res = r1 ^ r2;
- gpu_reg[dreg] = res;
- CLR_ZN; SET_ZN(res);
-}
+++ /dev/null
-#include "core.h"
-
-//#define DEBUG_GPU
-
-#define J_ALWAYS 0x00
-#define J_NZ 0x01
-#define J_Z 0x02
-#define J_NC 0x04
-#define J_NC_NZ 0x05
-#define J_NC_Z 0x06
-#define J_C 0x08
-#define J_C_NZ 0x09
-#define J_C_Z 0x0A
-#define J_NN 0x14
-#define J_NN_NZ 0x15
-#define J_NN_Z 0x16
-#define J_N 0x18
-#define J_N_NZ 0x19
-#define J_N_Z 0x1A
-#define J_NEVER 0x1F
-
- // Opcode Function Prototypes
-
- void G_ADD( void ); void G_ADDC( void );
- void G_ADDQ( void ); void G_ADDQT( void );
- void G_SUB( void ); void G_SUBC( void );
- void G_SUBQ( void ); void G_SUBQT( void );
- void G_NEG( void ); void G_AND( void );
- void G_OR( void ); void G_XOR( void );
- void G_NOT( void ); void G_BTST( void );
- void G_BSET( void ); void G_BCLR( void );
- void G_MULT( void ); void G_IMULT( void );
- void G_IMULTN( void ); void G_RESMAC( void );
- void G_IMACN( void ); void G_DIV( void );
- void G_ABS( void ); void G_SH( void );
- void G_SHLQ( void ); void G_SHRQ( void );
- void G_SHA( void ); void G_SHARQ( void );
- void G_ROR( void ); void G_RORQ( void );
- void G_CMP( void ); void G_CMPQ( void );
- void G_SAT8( void ); void G_SAT16( void );
- void G_MOVE( void ); void G_MOVEQ( void );
- void G_MOVETA( void ); void G_MOVEFA( void );
- void G_MOVEI( void ); void G_LOADB( void );
- void G_LOADW( void ); void G_LOAD( void );
- void G_LOADP( void ); void G_STORE_14I( void );
- void G_LOAD_14I( void ); void G_LOAD_15I( void );
- void G_STOREB( void ); void G_STOREW( void );
- void G_STORE( void ); void G_STOREP( void );
- void G_STORE_15I( void ); void G_MOVE_PC( void );
- void G_JUMP( void ); void G_JR( void );
- void G_MMULT( void ); void G_MTOI( void );
- void G_NORMI( void ); void G_NOP( void );
- void G_LOAD_14R( void ); void G_LOAD_15R( void );
- void G_STORE_14R( void ); void G_STORE_15R( void );
- void G_SAT24( void ); void G_PACK_UNPACK( void );
-
- // Other Prototypes
-
- unsigned mem_readword( unsigned );
- unsigned mem_readbyte( unsigned );
- void mem_writeword( unsigned, unsigned );
- void mem_writebyte( unsigned, unsigned );
-
- // CPU Cycles for Each GPU Opcode
-
- byte gpuCycles[64] = {
- 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 1, 3, 1, 18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
- 3, 3, 2, 2, 2, 2, 3, 4, 5, 4, 5, 6, 6, 1, 1, 1,
- 1, 2, 2, 2, 1, 1, 9, 3, 3, 0, 6, 6, 2, 2, 3, 3
-
- };
-
- // GPU Opcode Function Table
-
- void (*gpuOp[64])()= {
- G_ADD, G_ADDC, G_ADDQ, G_ADDQT,
- G_SUB, G_SUBC, G_SUBQ, G_SUBQT,
- G_NEG, G_AND, G_OR, G_XOR,
- G_NOT, G_BTST, G_BSET, G_BCLR,
- G_MULT, G_IMULT, G_IMULTN, G_RESMAC,
- G_IMACN, G_DIV, G_ABS, G_SH,
- G_SHLQ, G_SHRQ, G_SHA, G_SHARQ,
- G_ROR, G_RORQ, G_CMP, G_CMPQ,
- G_SAT8, G_SAT16, G_MOVE, G_MOVEQ,
- G_MOVETA, G_MOVEFA, G_MOVEI, G_LOADB,
- G_LOADW, G_LOAD, G_LOADP, G_LOAD_14I,
- G_LOAD_15I, G_STOREB, G_STOREW, G_STORE,
- G_STOREP, G_STORE_14I, G_STORE_15I, G_MOVE_PC,
- G_JUMP, G_JR, G_MMULT, G_MTOI,
- G_NORMI, G_NOP, G_LOAD_14R, G_LOAD_15R,
- G_STORE_14R, G_STORE_15R, G_SAT24, G_PACK_UNPACK
- };
-
- GPUSTATE gst; // GPU State Information
- dword GincPC; // PC Increment Flag
- dword GjmpPC; // PC Jump gdstination
- dword Gbranch; // Branch Flag
-
-#ifdef DEBUG_GPU
- FILE *oo;
-#endif
-/*
- sdword arb[32]; // GPU Active Register Bank
- sdword srb[32]; // GPU Secondary Register Bank
- dword acc; // Accumulator
- dword pc; // Program Counter
- dword src; // Source Register
- dword dst; // Destination Register
- BOOL z; // Zero Flag
- BOOL n; // Negative Flag
- BOOL c; // Carry Flag
- dword ctrl; // GPU Control Word (0xF02114 RW)
- BOOL div16; // 16.16 Division Flag (0xF0211C WO)
- dword divrem; // Division Remainder (0xF0211C RO)
-*/
-
- dword gpc; // Program Counter
- dword gsrc; // Instruction Word Source
- dword gdst; // Instruction Word Destination
- BOOL gz; // Zero Flag
- BOOL gn; // Negative Flag
- BOOL gc; // Carry Flag
-
-
- // GPU Processor Emulation
-
- DWORD gpu_exec( LPVOID lpParam )
- {
- dword iw; // Instruction Word
-
-#ifdef DEBUG_GPU
- oo = fopen( "gpudbg.out", "w" );
-
- {
- FILE *f;
- int i;
-
- f = fopen( "gpudump.bin", "wb" );
- for( i = 0x3000; i < 0x4000; i += 2 ) // Dump GPU RAM
- {
- fwrite( &st.tom[i+1], 1, 1, f );
- fwrite( &st.tom[i], 1, 1, f );
- }
- fclose( f );
- }
-#endif
-
- // Counter = InterruptPeriod;
-
- while( gst.gpuActive )
- {
- if( gst.step ) // While Single Step Enabled
- {
- while( !gst.stepgo ) ; // Wait Until StepGo Issued
- printf( " GPU Released for One Instruction (SINGLE STEP)\n" );
- }
-
- iw = mem_readword( gpc ); // Get Instruction Word
- gsrc = (iw & 0x03E0) >> 5; // Get Source
- gdst = (iw & 0x001F); // Get Destination
-
- gpuOp[iw >> 10](); // Jump to and Execute Opcode Routine
-
-#ifdef DEBUG_GPU
- fflush( oo );
-#endif
-
- // Counter -= Cycles[Opcode];
-
- // if( Counter <= 0 )
- // {
- // /* Check for Interrupts and do Other Cyclic tasks here
- // Counter += InterruptPeriod
- // }
-
- switch( Gbranch ) // Increment Program Counter
- {
- case 2: // Next Instruction is the Branch Address
- Gbranch = 0;
- gpc = GjmpPC;
- break;
-
- // A Branch Address was Stored in the Branch Program Counter.
- // The Next Instruction is a PC + 4 (Case 0 is Executed).
- // The Next Instruction is at the Branch Program Counter
-
- case 1:
- Gbranch = 2;
- case 0: // Normal Execution
- switch( GincPC )
- {
- case 1: // Opcode Used a 32-Bit Word
- gpc += 6;
- GincPC = 0;
- break;
- case 0: // Normal Execution
- gpc += 2;
- break;
- }
- break;
- }
-
- if( gst.step ) // If Single Step Mode Enabled
- {
- gst.stepgo = 0; // Reset StepGo Flag
- printf( " GPU Paused Until New SINGLE_GO (SINGLE STEP)\n" );
- }
- }
-
- #ifdef DEBUG_GPU
- fclose( oo );
- #endif
-
- return( TRUE );
- }
-
- void G_ABS( void )
- {
- if( gst.arb[gdst] == 0x80000000 )
- gn = 1;
- else
- if( gst.arb[gdst] < 0 )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- neg eax
- mov [ecx*4+gst.arb],eax
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = 0;
- gc = 1;
- }
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X ABS R%i\t\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_ADD( void )
- {
- __asm {
- mov ecx,[gsrc]
- mov edx,[ecx*4+gst.arb]
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- add eax,edx
- mov [ecx*4+gst.arb],eax
- mov ecx,1
- jc addend
- mov ecx,0
- addend:
- mov [gc],ecx
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X ADD R%i,R%i\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_ADDC( void )
- {
- __asm {
- clc
- mov ecx,[gc]
- jcxz addc
- stc
- addc:
- mov ecx,[gsrc]
- mov edx,[ecx*4+gst.arb]
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- adc eax,edx
- mov [ecx*4+gst.arb],eax
- mov ecx,1
- jc addcend
- mov ecx,0
- addcend:
- mov [gc],ecx
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X ADDC R%i,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_ADDQ( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov edx,[gsrc]
- add eax,edx
- mov [ecx*4+gst.arb],eax
- mov ecx,1
- jc addqend
- mov ecx,0
- addqend:
- mov [gc],ecx
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X ADDQ 0x%02X,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_ADDQT( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov edx,[gsrc]
- add eax,edx
- mov [ecx*4+gst.arb],eax
- };
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X ADDQT 0x%02X,R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_AND( void )
- {
- gst.arb[gdst] &= gst.arb[gsrc];
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X AND R%i,R%i\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_BCLR( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov edx,[gsrc]
- btr eax,edx
- mov [ecx*4+gst.arb],eax
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X BCLR 0x%04X,R%i\t\t\t "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gz, gn, gc );
- #endif
- }
-
- void G_BSET( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov edx,[gsrc]
- bts eax,edx
- mov [ecx*4+gst.arb],eax
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X BSET 0x%04X,R%i\t\t\t "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gz, gn, gc );
- #endif
- }
-
- void G_BTST( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov ecx,[gsrc]
- bt eax,ecx
- mov ecx,1
- jc btstend
- mov ecx,0
- btstend:
- mov [gz],ecx
- };
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X BTST 0x%04X,R%i\t\t\t "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gz, gn, gc );
- #endif
- }
-
- void G_CMP( void )
- {
- sdword tmpW;
-
- __asm {
- mov ecx,[gsrc]
- mov edx,[ecx*4+gst.arb]
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- sub eax,edx
- lahf
- mov [tmpW],eax
- };
-
- gc = (tmpW & 0x0100) ? 1 : 0;
- gz = (tmpW & 0x4000) ? 1 : 0;
- gn = (tmpW & 0x8000) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X CMP R%i,R%i\t\t "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gz, gn, gc );
- #endif
- }
-
- void G_CMPQ( void )
- {
- sdword tmpW;
-
- __asm {
- mov edx,[gsrc]
- bt edx,4
- jnc cmpq
- bts edx,31
- cmpq:
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- sub eax,edx
- lahf
- mov [tmpW],eax
- };
-
- gc = (tmpW & 0x0100) ? 1 : 0;
- gz = (tmpW & 0x4000) ? 1 : 0;
- gn = (tmpW & 0x8000) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X CMPQ 0x%02X,R%i\t\t "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gz, gn, gc );
- #endif*/
- }
-
- void G_DIV( void )
- {
- if( gst.div16 )
- printf( "GPU DIVIDE 16.16 REQUIRED !!!!\n" );
- else
- {
- (dword)gst.arb[gdst] = (dword)gst.arb[gdst] /
- (dword)gst.arb[gsrc];
-
- gst.divrem = (dword)gst.arb[gdst] % (dword)gst.arb[gsrc];
- }
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X DIV R%i,R%i\t\tR%02i = 0x%08X ",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_IMACN( void )
- {
- // Like IMULT but product is added to the previous arithmetic operation.
- // Intended to be used after IMULTN.
-
- gst.acc += (sdword)((sword)gst.arb[gsrc] *
- (sword)gst.arb[gdst] );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X IMACN R%i,R%i\t\tACC = 0x%08X\n",
- gpc, gsrc, gdst, gst.acc );
- #endif
- }
-
- void G_IMULT( void )
- {
- gst.arb[gdst] = (sdword)((sword)gst.arb[gsrc] *
- (sword)gst.arb[gdst] );
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X IMULT R%i,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_IMULTN( void )
- {
- // Like IMULT but result not written back to gst.arb[gdst]
- // but to an accumulator. Used as first part of multiply/accumulate group.
-
- gst.acc = (sdword)((sword)gst.arb[gsrc] *
- (sword)gst.arb[gdst] );
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X IMULTN R%i,R%i\t\tACC = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gst.acc,
- gz, gn, gc );
- #endif
- }
-
- void G_JR( void )
- {
- if( gsrc >= 16 ) // Set Jump Direction
- gsrc -= 32;
-
- GjmpPC = (gpc + 2) + (gsrc * 2);
-
- switch( gdst )
- {
- case 0x00: // No Conditions
- Gbranch = 1;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JR 0x%08X\n", gpc, GjmpPC );
- #endif
- break;
-
- case 0x01: // NE - Not Equal
- if( !gz ) // Zero Flag Unset
- Gbranch = 1;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JR NE,0x%08X\n",gpc, GjmpPC );
- #endif
- break;
-
- case 0x02: // EQ - Equal
- if( gz) // Zero Flag Set
- Gbranch = 1;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JR EQ,0x%08X\n", gpc, GjmpPC );
- #endif
- break;
-
- case 0x04: // Flag Selected Cleared to Jump
- if( !gc ) Gbranch = 1; else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JR CC,0x%08X\n", gpc, GjmpPC );
- #endif
- break;
-
- case 0x08: // Flag Selected Set to Jump
- if( gc ) Gbranch = 1; else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JR CS,0x%08X\n", gpc, GjmpPC );
- #endif
- break;
-
- case 0x14:
- if( !gn ) Gbranch = 1; else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JR NN,0x%08X\n", gpc, GjmpPC );
- #endif
- break;
-
- case 0x18:
- if( gn ) Gbranch = 1; else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JR N,0x%08X\n", gpc, GjmpPC );
- #endif
- break;
-
- default:
- #ifdef DEBUG_GPU
- fprintf( oo, "Unknown JR Condition at 0x%08X\n", gpc );
- #endif
- break;
-
- }
- }
-
- void G_JUMP( void )
- {
- GjmpPC = gst.arb[gsrc];
-
- switch( gdst )
- {
- case J_ALWAYS:
- Gbranch = 1;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP (R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NZ:
- if( !gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NZ,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_Z:
- if( gz) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP Z,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NC:
- if( !gc ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NC,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NC_NZ:
- if( !gc && !gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NC_NZ,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NC_Z:
- if( !gc && gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NC_Z,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_C:
- if( gc ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP C,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_C_NZ:
- if( gc && !gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP C_NZ,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_C_Z:
- if( gc && gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP C_Z,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NN:
- if( !gn ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NN,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NN_NZ:
- if( !gn && !gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NN_NZ,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NN_Z:
- if( !gn && gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NN_Z,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_N:
- if( gn ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP N,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_N_NZ:
- if( gn && !gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP N_NZ,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_N_Z:
- if( gn && gz ) Gbranch = 1;
- else Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP N_Z,(R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- case J_NEVER:
- Gbranch = 0;
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X JUMP NEVER (R%02i) DEST = 0x%08X\n",
- gpc, gsrc, GjmpPC );
- #endif
- break;
-
- default:
- #ifdef DEBUG_GPU
- fprintf( oo, "Unknown JUMP Condition\n" );
- #endif
- break;
- }
- }
-
- void G_LOAD( void )
- {
- gst.arb[gdst] = mem_readword( gst.arb[gsrc] ) << 16;
- gst.arb[gdst] |= mem_readword( gst.arb[gsrc] + 2 );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X LOAD (R%i),R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_LOAD_14I( void )
- {
- sdword tmpW;
-
- tmpW = gst.arb[0x0E] + (gsrc * 4);
- gst.arb[gdst] = mem_readword( tmpW ) << 16;
- gst.arb[gdst] |= mem_readword( tmpW + 2 );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X LOAD (R14+%02i),R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_LOAD_15I( void )
- {
- sdword tmpW;
-
- tmpW = gst.arb[0x0F] + (gsrc * 4);
- gst.arb[gdst] = mem_readword( tmpW ) << 16;
- gst.arb[gdst] |= mem_readword( tmpW + 2 );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X LOAD (R15+%02i),R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_LOAD_14R( void )
- {
- sdword tmpW;
-
- tmpW = gst.arb[0x0E] + gst.arb[gsrc];
- gst.arb[gdst] = mem_readword( tmpW ) << 16;
- gst.arb[gdst] |= mem_readword( tmpW + 2 );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X LOAD (R14+R%i),R%i\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_LOAD_15R( void )
- {
- sdword tmpW;
-
- // NOTE: Manual seems to indicate that this opcode
- // uses Register 14 as the base offset address.
-
- tmpW = gst.arb[0x0E] + gst.arb[gsrc];
- gst.arb[gdst] = mem_readword( tmpW ) << 16;
- gst.arb[gdst] |= mem_readword( tmpW + 2 );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X LOAD (R15+R%i),R%i\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_LOADB( void )
- {
- if( gst.arb[gsrc] >= 0xF03000 && gst.arb[gsrc] < 0xF04000 )
- {
- gst.arb[gdst] = mem_readword( gst.arb[gsrc] ) << 16;
- gst.arb[gdst] |= mem_readword( gst.arb[gsrc] + 2 );
- }
- else
- gst.arb[gdst] = mem_readbyte( gst.arb[gsrc] );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X LOADB (R%i),R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_LOADW( void )
- {
- if( gst.arb[gsrc] >= 0xF03000 && gst.arb[gsrc] < 0xF04000 )
- {
- gst.arb[gdst] = mem_readword( gst.arb[gsrc] ) << 16;
- gst.arb[gdst] |= mem_readword( gst.arb[gsrc] + 2 );
- }
- else
- gst.arb[gdst] = mem_readword( gst.arb[gsrc] );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X LOADW (R%i),R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_LOADP( void )
- {/*
- phr.hi = mem_readword( tolp ) << 16;
- phr.hi |= mem_readword( tolp + 0x02 );
- phr.lo = mem_readword( tolp + 0x04 ) << 16;
- phr.lo |= mem_readword( tolp + 0x06 );
-*/
- #ifdef DEBUG_GPU
- fprintf( oo, "GPU - Unimplemented Opcode (LOADP)\n" );
- #endif
-
- gst.gpuActive = FALSE;
- }
-
- void G_MMULT( void )
- {
- #ifdef DEBUG_GPU
- fprintf( oo, "GPU - Unimplemented Opcode (MMULT)\n" );
- #endif
- gst.gpuActive = FALSE;
- }
-
- void G_MOVE( void )
- {
- gst.arb[gdst] = gst.arb[gsrc];
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X MOVE R%i,R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_MOVE_PC( void )
- {
- gst.arb[gdst] = gpc;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X MOVE PC,R%i\t\tR%02i = 0x%08X\n",
- gpc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_MOVEFA( void )
- {
- gst.arb[gdst] = gst.srb[gsrc];
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X MOVEFA R%i,R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_MOVEI( void )
- {
- gst.arb[gdst] = mem_readword(gpc + 2);
- gst.arb[gdst] |= mem_readword(gpc + 4) << 16;
-
- GincPC = 1;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X MOVEI 0x%08X,R%i\tR%02i = 0x%08X\n",
- gpc, gst.arb[gdst], gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_MOVEQ( void )
- {
- gst.arb[gdst] = gsrc;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X MOVEQ 0x%02X,R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_MOVETA( void )
- {
- gst.srb[gdst] = gst.arb[gsrc];
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X MOVETA R%i,R%i\t\tR%02i = 0x%08X(0)\n",
- gpc, gsrc, gdst, gdst, gst.srb[gdst] );
- #endif
- }
-
- void G_MTOI( void )
- {
- #ifdef DEBUG_GPU
- fprintf( oo, "GPU - Unimplemented Opcode (MTOI)\n" );
- #endif
- gst.gpuActive = FALSE;
- }
-
- void G_MULT( void )
- {
- gst.arb[gdst] = (sdword)((word)gst.arb[gsrc] *
- (word)gst.arb[gdst] );
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X MULT R%i,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_NEG( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- neg eax
- mov [ecx*4+gst.arb],eax
- mov ecx,1
- jc negend
- mov ecx,0
- negend:
- mov [gc],ecx
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X NEG R%i\t\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_NOP( void )
- {
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X NOP\n", gpc );
- #endif
- }
-
- void G_NORMI( void )
- {
- #ifdef DEBUG_GPU
- fprintf( oo, "GPU - Unimplemented Opcode (NORMI)\n" );
- #endif
- gst.gpuActive = FALSE;
- }
-
- void G_NOT( void ) // Fix donated by YaK
- {
- gst.arb[gdst] = gst.arb[gdst] ^ 0xFFFFFFFF;
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X NOT R%i\t\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_OR( void )
- {
- gst.arb[gdst] |= gst.arb[gsrc];
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X OR R%i,R%i\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_PACK_UNPACK( void )
- {
- dword tmpW;
-
- tmpW = gst.arb[gdst];
-
- if( gsrc ) // UNPACK
- {
- gst.arb[gdst] = (tmpW & 0x000000FF);
- gst.arb[gdst] |= (tmpW & 0x00000F00) << 5;
- gst.arb[gdst] |= (tmpW & 0x0000F000) << 10;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X UNPACK R%i\t\t\tR%02i = 0x%08X\n",
- gpc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
- else // PACK
- {
- gst.arb[gdst] = (tmpW & 0x000000FF);
- gst.arb[gdst] |= (tmpW & 0x0001E000) >> 5;
- gst.arb[gdst] |= (tmpW & 0x03C00000) >> 10;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X PACK R%i\t\t\tR%02i = 0x%08X\n",
- gpc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
- }
-
- void G_RESMAC( void )
- {
- // Write result register to Register Rn
- // Used as last part of multiply/accumulate group.
-
- gst.arb[gdst] = gst.acc;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X RESMAC R%i\t\tR%02X = 0x%08X\n",
- gpc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_ROR( void )
- {
- gc = (gst.arb[gdst] >> 31) & 0x01;
-
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov edx,[gsrc]
- mov ecx,[edx*4+gst.arb]
- and ecx,0x1F
- ror eax,cl
- mov ecx,[gdst]
- mov [ecx*4+gst.arb],eax
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X ROR R%i,R%i\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_RORQ( void )
- {
- sdword tmpW;
-
- gc = (gst.arb[gdst] >> 31) & 0x01;
- tmpW = gst.arb[gdst];
-
- __asm {
- mov eax,[tmpW]
- mov ecx,[gsrc]
- ror eax,cl
- mov [tmpW],eax
- };
-
- gst.arb[gdst] = tmpW;
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X RORQ 0x%02X,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_SAT8( void )
- {
- if( gst.arb[gdst] < 0 ) gst.arb[gdst] =0x00000000;
- if( gst.arb[gdst] > 255 ) gst.arb[gdst] =0x000000FF;
-
- gn = 0;
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SAT8 R%02i\t\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n",
- gpc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_SAT16( void )
- {
- if( gst.arb[gdst] < 0 ) gst.arb[gdst] =0x00000000;
- if( gst.arb[gdst] > 65535 ) gst.arb[gdst] =0x0000FFFF;
-
- gn = 0;
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SAT16 R%02i\t\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n",
- gpc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_SAT24( void )
- {
- if( gst.arb[gdst] < 0 ) gst.arb[gdst] =0x00000000;
- if( gst.arb[gdst] > 16777215 ) gst.arb[gdst] =0x00FFFFFF;
-
- gn = 0;
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SAT24 R%02i\t\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n",
- gpc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_SH( void )
- {
- sdword tmpW;
-
- // NOTE: Watch the values here carefully
-
- if( gst.arb[gsrc] >= 0 ) // Shift Right
- {
- gc = gst.arb[gdst] & 0x01;
- tmpW = gst.arb[gsrc];
- __asm {
- mov edx,[gdst]
- mov eax,[edx*4+gst.arb]
- mov ecx,[tmpW]
- shr eax,cl
- mov [edx*4+gst.arb],eax
- };
- }
- else // Shift Left
- {
- gc = (gst.arb[gdst] >> 31) & 0x01;
- // Fix donated by YaK
- tmpW = (0xFFFFFFFF - gst.arb[gsrc]) + 1;
- __asm {
- mov edx,[gdst]
- mov eax,[edx*4+gst.arb]
- mov ecx,[tmpW]
- shl eax,cl
- mov [edx*4+gst.arb],eax
- };
- }
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SH R%i,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif*/
- }
-
- void G_SHA( void )
- {
- sdword tmpW;
-
- // NOTE: Watch the values here carefully
-
- if( gst.arb[gsrc] >= 0 ) // Shift Right
- {
- gc = gst.arb[gdst] & 0x01;
- tmpW = gst.arb[gsrc];
- __asm {
- mov edx,[gdst]
- mov eax,[edx*4+gst.arb]
- mov ecx,[tmpW]
- sar eax,cl
- mov [edx*4+gst.arb],eax
- };
- }
- else // Shift Left
- {
- gc = (gst.arb[gdst] >> 31) & 0x01;
- // Fix donated by YaK
- tmpW = (0xFFFFFFFF - gst.arb[gsrc]) + 1;
- __asm {
- mov edx,[gdst]
- mov eax,[edx*4+gst.arb]
- mov ecx,[tmpW]
- shl eax,cl
- mov [edx*4+gst.arb],eax
- };
- }
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SHA R%i,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif*/
- }
-
- void G_SHARQ( void )
- {
- sdword tmpW;
-
- gc = (gst.arb[gdst] & 0x01);
- tmpW = gst.arb[gdst];
-
- __asm {
- mov eax,[tmpW]
- mov ecx,[gsrc]
- sar eax,cl
- mov [tmpW],eax
- };
-
- gst.arb[gdst] = tmpW;
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SHARQ 0x%02X,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_SHLQ( void )
- {
- gc = (gst.arb[gdst] >> 31) & 0x01;
- gst.arb[gdst] <<= (32 - gsrc);
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SHLQ 0x%02X,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_SHRQ( void )
- {
- gc = gst.arb[gdst] & 0x01;
- gst.arb[gdst] >>= (32 - gsrc);
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SHRQ 0x%02X,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_STORE( void )
- {
- mem_writeword( gst.arb[gsrc], (gst.arb[gdst] >> 16) );
- mem_writeword( gst.arb[gsrc] + 2, (gst.arb[gdst] & 0xFFFF) );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X STORE R%i,(R%i)\t\tgdst = 0x%08X\n",
- gpc, gdst, gsrc, gst.arb[gsrc] );
- #endif
- }
-
- void G_STORE_14I( void )
- {
- sdword tmpW;
-
- tmpW = gst.arb[0x0E] + (gsrc * 4);
-
- mem_writeword( tmpW, (gst.arb[gdst] >> 16) );
- mem_writeword( tmpW + 2, (gst.arb[gdst] & 0xFFFF) );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X STORE R%i,(R14+%02i)\t\tgdst = 0x%08X\n",
- gpc, gsrc, gdst, tmpW );
- #endif
- }
-
- void G_STORE_15I( void )
- {
- sdword tmpW;
-
- tmpW = gst.arb[0x0F] + (gsrc * 4);
-
- mem_writeword( tmpW, (gst.arb[gdst] >> 16) );
- mem_writeword( tmpW + 2, (gst.arb[gdst] & 0xFFFF) );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X STORE R%i,(R15+%02i)\t\tgdst = 0x%08X\n",
- gpc, gsrc, gdst, tmpW );
- #endif
- }
-
- void G_STORE_14R( void )
- {
- sdword tmpW;
-
- tmpW = gst.arb[0x0E] + gst.arb[gsrc];
- mem_writeword( tmpW, (gst.arb[gdst] >> 16) );
- mem_writeword( tmpW + 2, (gst.arb[gdst] & 0xFFFF) );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X STORE R%i,(R14+R%i)\tgdst = 0x%08X\n",
- gpc, gdst, gsrc, tmpW );
- #endif
- }
-
- void G_STORE_15R( void )
- {
- sdword tmpW;
-
- // NOTE: Manual seems to indicate that this opcode
- // uses Register 14 as the base offset address.
-
- tmpW = gst.arb[0x0E] + gst.arb[gsrc];
- mem_writeword( tmpW, (gst.arb[gdst] >> 16) );
- mem_writeword( tmpW + 2, (gst.arb[gdst] & 0xFFFF) );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X STORE R%i,(R14+R%i)\tgdst = 0x%08X\n",
- gpc, gdst, gsrc, tmpW );
- #endif
- }
-
- void G_STOREB( void )
- {
- if( gst.arb[gsrc] >= 0xF03000 && gst.arb[gsrc] < 0xF04000 )
- {
- mem_writeword( gst.arb[gsrc], (gst.arb[gdst] >> 16) );
- mem_writeword( gst.arb[gsrc] + 2, (gst.arb[gdst] & 0xFFFF) );
- }
- else
- mem_writebyte( gst.arb[gsrc], (gst.arb[gdst] & 0xFF) );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X STOREB R%i,(R%i)\tgdst = 0x%08X\n",
- gpc, gdst, gsrc, gsrc );
- #endif
- }
-
- void G_STOREW( void )
- {
- if( gst.arb[gsrc] >= 0xF03000 && gst.arb[gsrc] < 0xF04000 )
- {
- mem_writeword( gst.arb[gsrc], (gst.arb[gdst] >> 16) );
- mem_writeword( gst.arb[gsrc] + 2, (gst.arb[gdst] & 0xFFFF) );
- }
- else
- mem_writeword( gst.arb[gsrc], (gst.arb[gdst] & 0xFFFF) );
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X STOREW R%i,(R%i)\tgdst = 0x%08X\n",
- gpc, gdst, gsrc, gsrc );
- #endif
- }
-
- void G_STOREP( void )
- {
- #ifdef DEBUG_GPU
- fprintf( oo, "GPU - Unimplemented Opcode (STOREP)\n" );
- #endif
- gst.gpuActive = FALSE;
- }
-
- void G_SUB( void )
- {
- __asm {
- mov ecx,[gsrc]
- mov edx,[ecx*4+gst.arb]
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- sub eax,edx
- mov [ecx*4+gst.arb],eax
- mov ecx,1
- jc subend
- mov ecx,0
- subend:
- mov [gc],ecx
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SUB R%i,R%i\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
-
- void G_SUBC( void )
- {
- __asm {
- clc
- mov ecx,[gc]
- jcxz subc
- stc
- subc:
- mov ecx,[gsrc]
- mov edx,[ecx*4+gst.arb]
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- sbb eax,edx
- mov [ecx*4+gst.arb],eax
- mov ecx,1
- jc subcend
- mov ecx,0
- subcend:
- mov [gc],ecx
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SUBC R%i,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_SUBQ( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov edx,[gsrc]
- sub eax,edx
- mov [ecx*4+gst.arb],eax
- mov ecx,1
- jc subqend
- mov ecx,0
- subqend:
- mov [gc],ecx
- };
-
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SUBQ 0x%02X,R%i\t\tR%02i = 0x%08X "
- "Z:%i N:%i C:%i\n", gpc, gsrc, gdst, gdst,
- gst.arb[gdst], gz, gn, gc );
- #endif
- }
-
- void G_SUBQT( void )
- {
- __asm {
- mov ecx,[gdst]
- mov eax,[ecx*4+gst.arb]
- mov edx,[gsrc]
- sub eax,edx
- mov [ecx*4+gst.arb],eax
- };
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X SUBQT 0x%02X,R%i\t\tR%02i = 0x%08X\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst] );
- #endif
- }
-
- void G_XOR( void )
- {
- gst.arb[gdst] ^= gst.arb[gsrc];
- gz = (gst.arb[gdst] == 0) ? 1 : 0;
- gn = (gst.arb[gdst] < 0) ? 1 : 0;
-
- #ifdef DEBUG_GPU
- fprintf( oo, "0x%06X XOR R%i,R%i\t\tR%02i = 0x%08X Z:%i N:%i C:%i\n",
- gpc, gsrc, gdst, gdst, gst.arb[gdst],
- gz, gn, gc );
- #endif
- }
projects / virtualjaguar / commitdiff