Shamusworld >> Repos - virtualjaguar/blob - src/m68kcpu.c

   1 /* ======================================================================== */\r
   2 /* ========================= LICENSING & COPYRIGHT ======================== */\r
   3 /* ======================================================================== */\r
   4 \r
   5 #if 0\r
   6 static const char* copyright_notice =\r
   7 "MUSASHI\n"\r
   8 "Version 3.3 (2001-01-29)\n"\r
   9 "A portable Motorola M680x0 processor emulation engine.\n"\r
  10 "Copyright 1998-2001 Karl Stenerud.  All rights reserved.\n"\r
  11 "\n"\r
  12 "This code may be freely used for non-commercial purpooses as long as this\n"\r
  13 "copyright notice remains unaltered in the source code and any binary files\n"\r
  14 "containing this code in compiled form.\n"\r
  15 "\n"\r
  16 "All other lisencing terms must be negotiated with the author\n"\r
  17 "(Karl Stenerud).\n"\r
  18 "\n"\r
  19 "The latest version of this code can be obtained at:\n"\r
  20 "http://kstenerud.cjb.net\n"\r
  21 ;\r
  22 #endif\r
  23 \r
  24 \r
  25 /* ======================================================================== */\r
  26 /* ================================= NOTES ================================ */\r
  27 /* ======================================================================== */\r
  28 \r
  29 \r
  30 \r
  31 /* ======================================================================== */\r
  32 /* ================================ INCLUDES ============================== */\r
  33 /* ======================================================================== */\r
  34 \r
  35 #include "m68kops.h"\r
  36 #include "m68kcpu.h"\r
  37 \r
  38 /* ======================================================================== */\r
  39 /* ================================= DATA ================================= */\r
  40 /* ======================================================================== */\r
  41 \r
  42 int  m68ki_initial_cycles;\r
  43 int  m68ki_remaining_cycles = 0;                     /* Number of clocks remaining */\r
  44 uint m68ki_tracing = 0;\r
  45 uint m68ki_address_space;\r
  46 \r
  47 #ifdef M68K_LOG_ENABLE\r
  48 char* m68ki_cpu_names[9] =\r
  49 {\r
  50         "Invalid CPU",\r
  51         "M68000",\r
  52         "M68010",\r
  53         "Invalid CPU",\r
  54         "M68EC020"\r
  55         "Invalid CPU",\r
  56         "Invalid CPU",\r
  57         "Invalid CPU",\r
  58         "M68020"\r
  59 };\r
  60 #endif /* M68K_LOG_ENABLE */\r
  61 \r
  62 /* The CPU core */\r
  63 m68ki_cpu_core m68ki_cpu = {0};\r
  64 \r
  65 #if M68K_EMULATE_ADDRESS_ERROR\r
  66 jmp_buf m68ki_address_error_trap;\r
  67 #endif /* M68K_EMULATE_ADDRESS_ERROR */\r
  68 \r
  69 /* Used by shift & rotate instructions */\r
  70 uint8 m68ki_shift_8_table[65] =\r
  71 {\r
  72         0x00, 0x80, 0xc0, 0xe0, 0xf0, 0xf8, 0xfc, 0xfe, 0xff, 0xff, 0xff, 0xff,\r
  73         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
  74         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
  75         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
  76         0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,\r
  77         0xff, 0xff, 0xff, 0xff, 0xff\r
  78 };\r
  79 uint16 m68ki_shift_16_table[65] =\r
  80 {\r
  81         0x0000, 0x8000, 0xc000, 0xe000, 0xf000, 0xf800, 0xfc00, 0xfe00, 0xff00,\r
  82         0xff80, 0xffc0, 0xffe0, 0xfff0, 0xfff8, 0xfffc, 0xfffe, 0xffff, 0xffff,\r
  83         0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\r
  84         0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\r
  85         0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\r
  86         0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\r
  87         0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,\r
  88         0xffff, 0xffff\r
  89 };\r
  90 uint m68ki_shift_32_table[65] =\r
  91 {\r
  92         0x00000000, 0x80000000, 0xc0000000, 0xe0000000, 0xf0000000, 0xf8000000,\r
  93         0xfc000000, 0xfe000000, 0xff000000, 0xff800000, 0xffc00000, 0xffe00000,\r
  94         0xfff00000, 0xfff80000, 0xfffc0000, 0xfffe0000, 0xffff0000, 0xffff8000,\r
  95         0xffffc000, 0xffffe000, 0xfffff000, 0xfffff800, 0xfffffc00, 0xfffffe00,\r
  96         0xffffff00, 0xffffff80, 0xffffffc0, 0xffffffe0, 0xfffffff0, 0xfffffff8,\r
  97         0xfffffffc, 0xfffffffe, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,\r
  98         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,\r
  99         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,\r
 100         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,\r
 101         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,\r
 102         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff\r
 103 };\r
 104 \r
 105 \r
 106 /* Number of clock cycles to use for exception processing.\r
 107  * I used 4 for any vectors that are undocumented for processing times.\r
 108  */\r
 109 uint8 m68ki_exception_cycle_table[3][256] =\r
 110 {\r
 111         { /* 000 */\r
 112                   4, /*  0: Reset - Initial Stack Pointer                      */\r
 113                   4, /*  1: Reset - Initial Program Counter                    */\r
 114                  50, /*  2: Bus Error                             (unemulated) */\r
 115                  50, /*  3: Address Error                         (unemulated) */\r
 116                  34, /*  4: Illegal Instruction                                */\r
 117                  38, /*  5: Divide by Zero -- ASG: changed from 42             */\r
 118                  40, /*  6: CHK -- ASG: chanaged from 44                       */\r
 119                  34, /*  7: TRAPV                                              */\r
 120                  34, /*  8: Privilege Violation                                */\r
 121                  34, /*  9: Trace                                              */\r
 122                   4, /* 10: 1010                                               */\r
 123                   4, /* 11: 1111                                               */\r
 124                   4, /* 12: RESERVED                                           */\r
 125                   4, /* 13: Coprocessor Protocol Violation        (unemulated) */\r
 126                   4, /* 14: Format Error                                       */\r
 127                  44, /* 15: Uninitialized Interrupt                            */\r
 128                   4, /* 16: RESERVED                                           */\r
 129                   4, /* 17: RESERVED                                           */\r
 130                   4, /* 18: RESERVED                                           */\r
 131                   4, /* 19: RESERVED                                           */\r
 132                   4, /* 20: RESERVED                                           */\r
 133                   4, /* 21: RESERVED                                           */\r
 134                   4, /* 22: RESERVED                                           */\r
 135                   4, /* 23: RESERVED                                           */\r
 136                  44, /* 24: Spurious Interrupt                                 */\r
 137                  44, /* 25: Level 1 Interrupt Autovector                       */\r
 138                  44, /* 26: Level 2 Interrupt Autovector                       */\r
 139                  44, /* 27: Level 3 Interrupt Autovector                       */\r
 140                  44, /* 28: Level 4 Interrupt Autovector                       */\r
 141                  44, /* 29: Level 5 Interrupt Autovector                       */\r
 142                  44, /* 30: Level 6 Interrupt Autovector                       */\r
 143                  44, /* 31: Level 7 Interrupt Autovector                       */\r
 144                  34, /* 32: TRAP #0 -- ASG: chanaged from 38                   */\r
 145                  34, /* 33: TRAP #1                                            */\r
 146                  34, /* 34: TRAP #2                                            */\r
 147                  34, /* 35: TRAP #3                                            */\r
 148                  34, /* 36: TRAP #4                                            */\r
 149                  34, /* 37: TRAP #5                                            */\r
 150                  34, /* 38: TRAP #6                                            */\r
 151                  34, /* 39: TRAP #7                                            */\r
 152                  34, /* 40: TRAP #8                                            */\r
 153                  34, /* 41: TRAP #9                                            */\r
 154                  34, /* 42: TRAP #10                                           */\r
 155                  34, /* 43: TRAP #11                                           */\r
 156                  34, /* 44: TRAP #12                                           */\r
 157                  34, /* 45: TRAP #13                                           */\r
 158                  34, /* 46: TRAP #14                                           */\r
 159                  34, /* 47: TRAP #15                                           */\r
 160                   4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */\r
 161                   4, /* 49: FP Inexact Result                     (unemulated) */\r
 162                   4, /* 50: FP Divide by Zero                     (unemulated) */\r
 163                   4, /* 51: FP Underflow                          (unemulated) */\r
 164                   4, /* 52: FP Operand Error                      (unemulated) */\r
 165                   4, /* 53: FP Overflow                           (unemulated) */\r
 166                   4, /* 54: FP Signaling NAN                      (unemulated) */\r
 167                   4, /* 55: FP Unimplemented Data Type            (unemulated) */\r
 168                   4, /* 56: MMU Configuration Error               (unemulated) */\r
 169                   4, /* 57: MMU Illegal Operation Error           (unemulated) */\r
 170                   4, /* 58: MMU Access Level Violation Error      (unemulated) */\r
 171                   4, /* 59: RESERVED                                           */\r
 172                   4, /* 60: RESERVED                                           */\r
 173                   4, /* 61: RESERVED                                           */\r
 174                   4, /* 62: RESERVED                                           */\r
 175                   4, /* 63: RESERVED                                           */\r
 176                      /* 64-255: User Defined                                   */\r
 177                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 178                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 179                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 180                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 181                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 182                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4\r
 183         },\r
 184         { /* 010 */\r
 185                   4, /*  0: Reset - Initial Stack Pointer                      */\r
 186                   4, /*  1: Reset - Initial Program Counter                    */\r
 187                 126, /*  2: Bus Error                             (unemulated) */\r
 188                 126, /*  3: Address Error                         (unemulated) */\r
 189                  38, /*  4: Illegal Instruction                                */\r
 190                  44, /*  5: Divide by Zero                                     */\r
 191                  44, /*  6: CHK                                                */\r
 192                  34, /*  7: TRAPV                                              */\r
 193                  38, /*  8: Privilege Violation                                */\r
 194                  38, /*  9: Trace                                              */\r
 195                   4, /* 10: 1010                                               */\r
 196                   4, /* 11: 1111                                               */\r
 197                   4, /* 12: RESERVED                                           */\r
 198                   4, /* 13: Coprocessor Protocol Violation        (unemulated) */\r
 199                   4, /* 14: Format Error                                       */\r
 200                  44, /* 15: Uninitialized Interrupt                            */\r
 201                   4, /* 16: RESERVED                                           */\r
 202                   4, /* 17: RESERVED                                           */\r
 203                   4, /* 18: RESERVED                                           */\r
 204                   4, /* 19: RESERVED                                           */\r
 205                   4, /* 20: RESERVED                                           */\r
 206                   4, /* 21: RESERVED                                           */\r
 207                   4, /* 22: RESERVED                                           */\r
 208                   4, /* 23: RESERVED                                           */\r
 209                  46, /* 24: Spurious Interrupt                                 */\r
 210                  46, /* 25: Level 1 Interrupt Autovector                       */\r
 211                  46, /* 26: Level 2 Interrupt Autovector                       */\r
 212                  46, /* 27: Level 3 Interrupt Autovector                       */\r
 213                  46, /* 28: Level 4 Interrupt Autovector                       */\r
 214                  46, /* 29: Level 5 Interrupt Autovector                       */\r
 215                  46, /* 30: Level 6 Interrupt Autovector                       */\r
 216                  46, /* 31: Level 7 Interrupt Autovector                       */\r
 217                  38, /* 32: TRAP #0                                            */\r
 218                  38, /* 33: TRAP #1                                            */\r
 219                  38, /* 34: TRAP #2                                            */\r
 220                  38, /* 35: TRAP #3                                            */\r
 221                  38, /* 36: TRAP #4                                            */\r
 222                  38, /* 37: TRAP #5                                            */\r
 223                  38, /* 38: TRAP #6                                            */\r
 224                  38, /* 39: TRAP #7                                            */\r
 225                  38, /* 40: TRAP #8                                            */\r
 226                  38, /* 41: TRAP #9                                            */\r
 227                  38, /* 42: TRAP #10                                           */\r
 228                  38, /* 43: TRAP #11                                           */\r
 229                  38, /* 44: TRAP #12                                           */\r
 230                  38, /* 45: TRAP #13                                           */\r
 231                  38, /* 46: TRAP #14                                           */\r
 232                  38, /* 47: TRAP #15                                           */\r
 233                   4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */\r
 234                   4, /* 49: FP Inexact Result                     (unemulated) */\r
 235                   4, /* 50: FP Divide by Zero                     (unemulated) */\r
 236                   4, /* 51: FP Underflow                          (unemulated) */\r
 237                   4, /* 52: FP Operand Error                      (unemulated) */\r
 238                   4, /* 53: FP Overflow                           (unemulated) */\r
 239                   4, /* 54: FP Signaling NAN                      (unemulated) */\r
 240                   4, /* 55: FP Unimplemented Data Type            (unemulated) */\r
 241                   4, /* 56: MMU Configuration Error               (unemulated) */\r
 242                   4, /* 57: MMU Illegal Operation Error           (unemulated) */\r
 243                   4, /* 58: MMU Access Level Violation Error      (unemulated) */\r
 244                   4, /* 59: RESERVED                                           */\r
 245                   4, /* 60: RESERVED                                           */\r
 246                   4, /* 61: RESERVED                                           */\r
 247                   4, /* 62: RESERVED                                           */\r
 248                   4, /* 63: RESERVED                                           */\r
 249                      /* 64-255: User Defined                                   */\r
 250                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 251                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 252                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 253                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 254                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 255                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4\r
 256         },\r
 257         { /* 020 */\r
 258                   4, /*  0: Reset - Initial Stack Pointer                      */\r
 259                   4, /*  1: Reset - Initial Program Counter                    */\r
 260                  50, /*  2: Bus Error                             (unemulated) */\r
 261                  50, /*  3: Address Error                         (unemulated) */\r
 262                  20, /*  4: Illegal Instruction                                */\r
 263                  38, /*  5: Divide by Zero                                     */\r
 264                  40, /*  6: CHK                                                */\r
 265                  20, /*  7: TRAPV                                              */\r
 266                  34, /*  8: Privilege Violation                                */\r
 267                  25, /*  9: Trace                                              */\r
 268                  20, /* 10: 1010                                               */\r
 269                  20, /* 11: 1111                                               */\r
 270                   4, /* 12: RESERVED                                           */\r
 271                   4, /* 13: Coprocessor Protocol Violation        (unemulated) */\r
 272                   4, /* 14: Format Error                                       */\r
 273                  30, /* 15: Uninitialized Interrupt                            */\r
 274                   4, /* 16: RESERVED                                           */\r
 275                   4, /* 17: RESERVED                                           */\r
 276                   4, /* 18: RESERVED                                           */\r
 277                   4, /* 19: RESERVED                                           */\r
 278                   4, /* 20: RESERVED                                           */\r
 279                   4, /* 21: RESERVED                                           */\r
 280                   4, /* 22: RESERVED                                           */\r
 281                   4, /* 23: RESERVED                                           */\r
 282                  30, /* 24: Spurious Interrupt                                 */\r
 283                  30, /* 25: Level 1 Interrupt Autovector                       */\r
 284                  30, /* 26: Level 2 Interrupt Autovector                       */\r
 285                  30, /* 27: Level 3 Interrupt Autovector                       */\r
 286                  30, /* 28: Level 4 Interrupt Autovector                       */\r
 287                  30, /* 29: Level 5 Interrupt Autovector                       */\r
 288                  30, /* 30: Level 6 Interrupt Autovector                       */\r
 289                  30, /* 31: Level 7 Interrupt Autovector                       */\r
 290                  20, /* 32: TRAP #0                                            */\r
 291                  20, /* 33: TRAP #1                                            */\r
 292                  20, /* 34: TRAP #2                                            */\r
 293                  20, /* 35: TRAP #3                                            */\r
 294                  20, /* 36: TRAP #4                                            */\r
 295                  20, /* 37: TRAP #5                                            */\r
 296                  20, /* 38: TRAP #6                                            */\r
 297                  20, /* 39: TRAP #7                                            */\r
 298                  20, /* 40: TRAP #8                                            */\r
 299                  20, /* 41: TRAP #9                                            */\r
 300                  20, /* 42: TRAP #10                                           */\r
 301                  20, /* 43: TRAP #11                                           */\r
 302                  20, /* 44: TRAP #12                                           */\r
 303                  20, /* 45: TRAP #13                                           */\r
 304                  20, /* 46: TRAP #14                                           */\r
 305                  20, /* 47: TRAP #15                                           */\r
 306                   4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */\r
 307                   4, /* 49: FP Inexact Result                     (unemulated) */\r
 308                   4, /* 50: FP Divide by Zero                     (unemulated) */\r
 309                   4, /* 51: FP Underflow                          (unemulated) */\r
 310                   4, /* 52: FP Operand Error                      (unemulated) */\r
 311                   4, /* 53: FP Overflow                           (unemulated) */\r
 312                   4, /* 54: FP Signaling NAN                      (unemulated) */\r
 313                   4, /* 55: FP Unimplemented Data Type            (unemulated) */\r
 314                   4, /* 56: MMU Configuration Error               (unemulated) */\r
 315                   4, /* 57: MMU Illegal Operation Error           (unemulated) */\r
 316                   4, /* 58: MMU Access Level Violation Error      (unemulated) */\r
 317                   4, /* 59: RESERVED                                           */\r
 318                   4, /* 60: RESERVED                                           */\r
 319                   4, /* 61: RESERVED                                           */\r
 320                   4, /* 62: RESERVED                                           */\r
 321                   4, /* 63: RESERVED                                           */\r
 322                      /* 64-255: User Defined                                   */\r
 323                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 324                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 325                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 326                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 327                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,\r
 328                   4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4\r
 329         }\r
 330 };\r
 331 \r
 332 uint8 m68ki_ea_idx_cycle_table[64] =\r
 333 {\r
 334          0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,\r
 335          0, /* ..01.000 no memory indirect, base NULL             */\r
 336          5, /* ..01..01 memory indirect,    base NULL, outer NULL */\r
 337          7, /* ..01..10 memory indirect,    base NULL, outer 16   */\r
 338          7, /* ..01..11 memory indirect,    base NULL, outer 32   */\r
 339          0,  5,  7,  7,  0,  5,  7,  7,  0,  5,  7,  7,\r
 340          2, /* ..10.000 no memory indirect, base 16               */\r
 341          7, /* ..10..01 memory indirect,    base 16,   outer NULL */\r
 342          9, /* ..10..10 memory indirect,    base 16,   outer 16   */\r
 343          9, /* ..10..11 memory indirect,    base 16,   outer 32   */\r
 344          0,  7,  9,  9,  0,  7,  9,  9,  0,  7,  9,  9,\r
 345          6, /* ..11.000 no memory indirect, base 32               */\r
 346         11, /* ..11..01 memory indirect,    base 32,   outer NULL */\r
 347         13, /* ..11..10 memory indirect,    base 32,   outer 16   */\r
 348         13, /* ..11..11 memory indirect,    base 32,   outer 32   */\r
 349          0, 11, 13, 13,  0, 11, 13, 13,  0, 11, 13, 13\r
 350 };\r
 351 \r
 352 \r
 353 \r
 354 /* ======================================================================== */\r
 355 /* =============================== CALLBACKS ============================== */\r
 356 /* ======================================================================== */\r
 357 \r
 358 /* Default callbacks used if the callback hasn't been set yet, or if the\r
 359  * callback is set to NULL\r
 360  */\r
 361 \r
 362 /* Interrupt acknowledge */\r
 363 static int default_int_ack_callback_data;\r
 364 static int default_int_ack_callback(int int_level)\r
 365 {\r
 366         default_int_ack_callback_data = int_level;\r
 367         CPU_INT_LEVEL = 0;\r
 368         return M68K_INT_ACK_AUTOVECTOR;\r
 369 }\r
 370 \r
 371 /* Breakpoint acknowledge */\r
 372 static unsigned int default_bkpt_ack_callback_data;\r
 373 static void default_bkpt_ack_callback(unsigned int data)\r
 374 {\r
 375         default_bkpt_ack_callback_data = data;\r
 376 }\r
 377 \r
 378 /* Called when a reset instruction is executed */\r
 379 static void default_reset_instr_callback(void)\r
 380 {\r
 381 }\r
 382 \r
 383 /* Called when the program counter changed by a large value */\r
 384 static unsigned int default_pc_changed_callback_data;\r
 385 static void default_pc_changed_callback(unsigned int new_pc)\r
 386 {\r
 387         default_pc_changed_callback_data = new_pc;\r
 388 }\r
 389 \r
 390 /* Called every time there's bus activity (read/write to/from memory */\r
 391 static unsigned int default_set_fc_callback_data;\r
 392 static void default_set_fc_callback(unsigned int new_fc)\r
 393 {\r
 394         default_set_fc_callback_data = new_fc;\r
 395 }\r
 396 \r
 397 /* Called every instruction cycle prior to execution */\r
 398 static void default_instr_hook_callback(void)\r
 399 {\r
 400 }\r
 401 \r
 402 \r
 403 \r
 404 /* ======================================================================== */\r
 405 /* ================================= API ================================== */\r
 406 /* ======================================================================== */\r
 407 \r
 408 /* Access the internals of the CPU */\r
 409 unsigned int m68k_get_reg(void* context, m68k_register_t regnum)\r
 410 {\r
 411         m68ki_cpu_core* cpu = context != NULL ?(m68ki_cpu_core*)context : &m68ki_cpu;\r
 412 \r
 413         switch(regnum)\r
 414         {\r
 415                 case M68K_REG_D0:       return cpu->dar[0];\r
 416                 case M68K_REG_D1:       return cpu->dar[1];\r
 417                 case M68K_REG_D2:       return cpu->dar[2];\r
 418                 case M68K_REG_D3:       return cpu->dar[3];\r
 419                 case M68K_REG_D4:       return cpu->dar[4];\r
 420                 case M68K_REG_D5:       return cpu->dar[5];\r
 421                 case M68K_REG_D6:       return cpu->dar[6];\r
 422                 case M68K_REG_D7:       return cpu->dar[7];\r
 423                 case M68K_REG_A0:       return cpu->dar[8];\r
 424                 case M68K_REG_A1:       return cpu->dar[9];\r
 425                 case M68K_REG_A2:       return cpu->dar[10];\r
 426                 case M68K_REG_A3:       return cpu->dar[11];\r
 427                 case M68K_REG_A4:       return cpu->dar[12];\r
 428                 case M68K_REG_A5:       return cpu->dar[13];\r
 429                 case M68K_REG_A6:       return cpu->dar[14];\r
 430                 case M68K_REG_A7:       return cpu->dar[15];\r
 431                 case M68K_REG_PC:       return MASK_OUT_ABOVE_32(cpu->pc);\r
 432                 case M68K_REG_SR:       return  cpu->t1_flag                                            |\r
 433                                                                         cpu->t0_flag                                            |\r
 434                                                                         (cpu->s_flag << 11)                                     |\r
 435                                                                         (cpu->m_flag << 11)                                     |\r
 436                                                                         cpu->int_mask                                           |\r
 437                                                                         ((cpu->x_flag & XFLAG_SET) >> 4)        |\r
 438                                                                         ((cpu->n_flag & NFLAG_SET) >> 4)        |\r
 439                                                                         ((!cpu->not_z_flag) << 2)                       |\r
 440                                                                         ((cpu->v_flag & VFLAG_SET) >> 6)        |\r
 441                                                                         ((cpu->c_flag & CFLAG_SET) >> 8);\r
 442                 case M68K_REG_SP:       return cpu->dar[15];\r
 443                 case M68K_REG_USP:      return cpu->s_flag ? cpu->sp[0] : cpu->dar[15];\r
 444                 case M68K_REG_ISP:      return cpu->s_flag && !cpu->m_flag ? cpu->dar[15] : cpu->sp[4];\r
 445                 case M68K_REG_MSP:      return cpu->s_flag && cpu->m_flag ? cpu->dar[15] : cpu->sp[6];\r
 446                 case M68K_REG_SFC:      return cpu->sfc;\r
 447                 case M68K_REG_DFC:      return cpu->dfc;\r
 448                 case M68K_REG_VBR:      return cpu->vbr;\r
 449                 case M68K_REG_CACR:     return cpu->cacr;\r
 450                 case M68K_REG_CAAR:     return cpu->caar;\r
 451                 case M68K_REG_PREF_ADDR:        return cpu->pref_addr;\r
 452                 case M68K_REG_PREF_DATA:        return cpu->pref_data;\r
 453                 case M68K_REG_PPC:      return MASK_OUT_ABOVE_32(cpu->ppc);\r
 454                 case M68K_REG_IR:       return cpu->ir;\r
 455                 case M68K_REG_CPU_TYPE:\r
 456                         switch(cpu->cpu_type)\r
 457                         {\r
 458                                 case CPU_TYPE_000:              return (unsigned int)M68K_CPU_TYPE_68000;\r
 459                                 case CPU_TYPE_010:              return (unsigned int)M68K_CPU_TYPE_68010;\r
 460                                 case CPU_TYPE_EC020:    return (unsigned int)M68K_CPU_TYPE_68EC020;\r
 461                                 case CPU_TYPE_020:              return (unsigned int)M68K_CPU_TYPE_68020;\r
 462                         }\r
 463                         return M68K_CPU_TYPE_INVALID;\r
 464                 default:                        return 0;\r
 465         }\r
 466         return 0;\r
 467 }\r
 468 \r
 469 void m68k_set_reg(m68k_register_t regnum, unsigned int value)\r
 470 {\r
 471         switch(regnum)\r
 472         {\r
 473                 case M68K_REG_D0:       REG_D[0] = MASK_OUT_ABOVE_32(value); return;\r
 474                 case M68K_REG_D1:       REG_D[1] = MASK_OUT_ABOVE_32(value); return;\r
 475                 case M68K_REG_D2:       REG_D[2] = MASK_OUT_ABOVE_32(value); return;\r
 476                 case M68K_REG_D3:       REG_D[3] = MASK_OUT_ABOVE_32(value); return;\r
 477                 case M68K_REG_D4:       REG_D[4] = MASK_OUT_ABOVE_32(value); return;\r
 478                 case M68K_REG_D5:       REG_D[5] = MASK_OUT_ABOVE_32(value); return;\r
 479                 case M68K_REG_D6:       REG_D[6] = MASK_OUT_ABOVE_32(value); return;\r
 480                 case M68K_REG_D7:       REG_D[7] = MASK_OUT_ABOVE_32(value); return;\r
 481                 case M68K_REG_A0:       REG_A[0] = MASK_OUT_ABOVE_32(value); return;\r
 482                 case M68K_REG_A1:       REG_A[1] = MASK_OUT_ABOVE_32(value); return;\r
 483                 case M68K_REG_A2:       REG_A[2] = MASK_OUT_ABOVE_32(value); return;\r
 484                 case M68K_REG_A3:       REG_A[3] = MASK_OUT_ABOVE_32(value); return;\r
 485                 case M68K_REG_A4:       REG_A[4] = MASK_OUT_ABOVE_32(value); return;\r
 486                 case M68K_REG_A5:       REG_A[5] = MASK_OUT_ABOVE_32(value); return;\r
 487                 case M68K_REG_A6:       REG_A[6] = MASK_OUT_ABOVE_32(value); return;\r
 488                 case M68K_REG_A7:       REG_A[7] = MASK_OUT_ABOVE_32(value); return;\r
 489                 case M68K_REG_PC:       m68ki_jump(MASK_OUT_ABOVE_32(value)); return;\r
 490                 case M68K_REG_SR:       m68ki_set_sr(value); return;\r
 491                 case M68K_REG_SP:       REG_SP = MASK_OUT_ABOVE_32(value); return;\r
 492                 case M68K_REG_USP:      if(FLAG_S)\r
 493                                                                 REG_USP = MASK_OUT_ABOVE_32(value);\r
 494                                                         else\r
 495                                                                 REG_SP = MASK_OUT_ABOVE_32(value);\r
 496                                                         return;\r
 497                 case M68K_REG_ISP:      if(FLAG_S && !FLAG_M)\r
 498                                                                 REG_SP = MASK_OUT_ABOVE_32(value);\r
 499                                                         else\r
 500                                                                 REG_ISP = MASK_OUT_ABOVE_32(value);\r
 501                                                         return;\r
 502                 case M68K_REG_MSP:      if(FLAG_S && FLAG_M)\r
 503                                                                 REG_SP = MASK_OUT_ABOVE_32(value);\r
 504                                                         else\r
 505                                                                 REG_MSP = MASK_OUT_ABOVE_32(value);\r
 506                                                         return;\r
 507                 case M68K_REG_VBR:      REG_VBR = MASK_OUT_ABOVE_32(value); return;\r
 508                 case M68K_REG_SFC:      REG_SFC = value & 7; return;\r
 509                 case M68K_REG_DFC:      REG_DFC = value & 7; return;\r
 510                 case M68K_REG_CACR:     REG_CACR = MASK_OUT_ABOVE_32(value); return;\r
 511                 case M68K_REG_CAAR:     REG_CAAR = MASK_OUT_ABOVE_32(value); return;\r
 512                 case M68K_REG_PPC:      REG_PPC = MASK_OUT_ABOVE_32(value); return;\r
 513                 case M68K_REG_IR:       REG_IR = MASK_OUT_ABOVE_16(value); return;\r
 514                 case M68K_REG_CPU_TYPE: m68k_set_cpu_type(value); return;\r
 515                 default:                        return;\r
 516         }\r
 517 }\r
 518 \r
 519 /* Set the callbacks */\r
 520 void m68k_set_int_ack_callback(int  (*callback)(int int_level))\r
 521 {\r
 522         CALLBACK_INT_ACK = callback ? callback : default_int_ack_callback;\r
 523 }\r
 524 \r
 525 void m68k_set_bkpt_ack_callback(void  (*callback)(unsigned int data))\r
 526 {\r
 527         CALLBACK_BKPT_ACK = callback ? callback : default_bkpt_ack_callback;\r
 528 }\r
 529 \r
 530 void m68k_set_reset_instr_callback(void  (*callback)(void))\r
 531 {\r
 532         CALLBACK_RESET_INSTR = callback ? callback : default_reset_instr_callback;\r
 533 }\r
 534 \r
 535 void m68k_set_pc_changed_callback(void  (*callback)(unsigned int new_pc))\r
 536 {\r
 537         CALLBACK_PC_CHANGED = callback ? callback : default_pc_changed_callback;\r
 538 }\r
 539 \r
 540 void m68k_set_fc_callback(void  (*callback)(unsigned int new_fc))\r
 541 {\r
 542         CALLBACK_SET_FC = callback ? callback : default_set_fc_callback;\r
 543 }\r
 544 \r
 545 void m68k_set_instr_hook_callback(void  (*callback)(void))\r
 546 {\r
 547         CALLBACK_INSTR_HOOK = callback ? callback : default_instr_hook_callback;\r
 548 }\r
 549 \r
 550 #include <stdio.h>\r
 551 /* Set the CPU type. */\r
 552 void m68k_set_cpu_type(unsigned int cpu_type)\r
 553 {\r
 554         switch(cpu_type)\r
 555         {\r
 556                 case M68K_CPU_TYPE_68000:\r
 557                         CPU_TYPE         = CPU_TYPE_000;\r
 558                         CPU_ADDRESS_MASK = 0x00ffffff;\r
 559                         CPU_SR_MASK      = 0xa71f; /* T1 -- S  -- -- I2 I1 I0 -- -- -- X  N  Z  V  C  */\r
 560                         CYC_INSTRUCTION  = m68ki_cycles[0];\r
 561                         CYC_EXCEPTION    = m68ki_exception_cycle_table[0];\r
 562                         CYC_BCC_NOTAKE_B = -2;\r
 563                         CYC_BCC_NOTAKE_W = 2;\r
 564                         CYC_DBCC_F_NOEXP = -2;\r
 565                         CYC_DBCC_F_EXP   = 2;\r
 566                         CYC_SCC_R_FALSE  = 2;\r
 567                         CYC_MOVEM_W      = 2;\r
 568                         CYC_MOVEM_L      = 3;\r
 569                         CYC_SHIFT        = 1;\r
 570                         CYC_RESET        = 132;\r
 571                         return;\r
 572                 case M68K_CPU_TYPE_68010:\r
 573                         CPU_TYPE         = CPU_TYPE_010;\r
 574                         CPU_ADDRESS_MASK = 0x00ffffff;\r
 575                         CPU_SR_MASK      = 0xa71f; /* T1 -- S  -- -- I2 I1 I0 -- -- -- X  N  Z  V  C  */\r
 576                         CYC_INSTRUCTION  = m68ki_cycles[1];\r
 577                         CYC_EXCEPTION    = m68ki_exception_cycle_table[1];\r
 578                         CYC_BCC_NOTAKE_B = -4;\r
 579                         CYC_BCC_NOTAKE_W = 0;\r
 580                         CYC_DBCC_F_NOEXP = 0;\r
 581                         CYC_DBCC_F_EXP   = 6;\r
 582                         CYC_SCC_R_FALSE  = 0;\r
 583                         CYC_MOVEM_W      = 2;\r
 584                         CYC_MOVEM_L      = 3;\r
 585                         CYC_SHIFT        = 1;\r
 586                         CYC_RESET        = 130;\r
 587                         return;\r
 588                 case M68K_CPU_TYPE_68EC020:\r
 589                         CPU_TYPE         = CPU_TYPE_EC020;\r
 590                         CPU_ADDRESS_MASK = 0x00ffffff;\r
 591                         CPU_SR_MASK      = 0xf71f; /* T1 T0 S  M  -- I2 I1 I0 -- -- -- X  N  Z  V  C  */\r
 592                         CYC_INSTRUCTION  = m68ki_cycles[2];\r
 593                         CYC_EXCEPTION    = m68ki_exception_cycle_table[2];\r
 594                         CYC_BCC_NOTAKE_B = -2;\r
 595                         CYC_BCC_NOTAKE_W = 0;\r
 596                         CYC_DBCC_F_NOEXP = 0;\r
 597                         CYC_DBCC_F_EXP   = 4;\r
 598                         CYC_SCC_R_FALSE  = 0;\r
 599                         CYC_MOVEM_W      = 2;\r
 600                         CYC_MOVEM_L      = 2; \r
 601                         CYC_SHIFT        = 0;\r
 602                         CYC_RESET        = 518;\r
 603                         return;\r
 604                 case M68K_CPU_TYPE_68020:\r
 605                         CPU_TYPE         = CPU_TYPE_020;\r
 606                         CPU_ADDRESS_MASK = 0xffffffff;\r
 607                         CPU_SR_MASK      = 0xf71f; /* T1 T0 S  M  -- I2 I1 I0 -- -- -- X  N  Z  V  C  */\r
 608                         CYC_INSTRUCTION  = m68ki_cycles[2];\r
 609                         CYC_EXCEPTION    = m68ki_exception_cycle_table[2];\r
 610                         CYC_BCC_NOTAKE_B = -2;\r
 611                         CYC_BCC_NOTAKE_W = 0;\r
 612                         CYC_DBCC_F_NOEXP = 0;\r
 613                         CYC_DBCC_F_EXP   = 4;\r
 614                         CYC_SCC_R_FALSE  = 0;\r
 615                         CYC_MOVEM_W      = 2;\r
 616                         CYC_MOVEM_L      = 2;\r
 617                         CYC_SHIFT        = 0;\r
 618                         CYC_RESET        = 518;\r
 619                         return;\r
 620         }\r
 621 }\r
 622 \r
 623 /* Execute some instructions until we use up num_cycles clock cycles */\r
 624 /* ASG: removed per-instruction interrupt checks */\r
 625 int m68k_execute(int num_cycles)\r
 626 {\r
 627         /* Make sure we're not stopped */\r
 628         if(!CPU_STOPPED)\r
 629         {\r
 630                 /* Set our pool of clock cycles available */\r
 631                 SET_CYCLES(num_cycles);\r
 632                 m68ki_initial_cycles = num_cycles;\r
 633 \r
 634                 /* ASG: update cycles */\r
 635                 USE_CYCLES(CPU_INT_CYCLES);\r
 636                 CPU_INT_CYCLES = 0;\r
 637 \r
 638                 /* Return point if we had an address error */\r
 639                 m68ki_set_address_error_trap(); /* auto-disable (see m68kcpu.h) */\r
 640 \r
 641                 /* Main loop.  Keep going until we run out of clock cycles */\r
 642                 do\r
 643                 {\r
 644                         /* Set tracing accodring to T1. (T0 is done inside instruction) */\r
 645                         m68ki_trace_t1(); /* auto-disable (see m68kcpu.h) */\r
 646 \r
 647                         /* Set the address space for reads */\r
 648                         m68ki_use_data_space(); /* auto-disable (see m68kcpu.h) */\r
 649 \r
 650                         /* Call external hook to peek at CPU */\r
 651                         m68ki_instr_hook(); /* auto-disable (see m68kcpu.h) */\r
 652 \r
 653                         /* Record previous program counter */\r
 654                         REG_PPC = REG_PC;\r
 655 \r
 656                         /* Read an instruction and call its handler */\r
 657                         REG_IR = m68ki_read_imm_16();\r
 658                         m68ki_instruction_jump_table[REG_IR]();\r
 659                         USE_CYCLES(CYC_INSTRUCTION[REG_IR]);\r
 660 \r
 661                         /* Trace m68k_exception, if necessary */\r
 662                         m68ki_exception_if_trace(); /* auto-disable (see m68kcpu.h) */\r
 663                 } while(GET_CYCLES() > 0);\r
 664 \r
 665                 /* set previous PC to current PC for the next entry into the loop */\r
 666                 REG_PPC = REG_PC;\r
 667 \r
 668                 /* ASG: update cycles */\r
 669                 USE_CYCLES(CPU_INT_CYCLES);\r
 670                 CPU_INT_CYCLES = 0;\r
 671 \r
 672                 /* return how many clocks we used */\r
 673                 return m68ki_initial_cycles - GET_CYCLES();\r
 674         }\r
 675 \r
 676         /* We get here if the CPU is stopped or halted */\r
 677         SET_CYCLES(0);\r
 678         CPU_INT_CYCLES = 0;\r
 679 \r
 680         return num_cycles;\r
 681 }\r
 682 \r
 683 \r
 684 int m68k_cycles_run(void)\r
 685 {\r
 686         return m68ki_initial_cycles - GET_CYCLES();\r
 687 }\r
 688 \r
 689 int m68k_cycles_remaining(void)\r
 690 {\r
 691         return GET_CYCLES();\r
 692 }\r
 693 \r
 694 /* Change the timeslice */\r
 695 void m68k_modify_timeslice(int cycles)\r
 696 {\r
 697         m68ki_initial_cycles += cycles;\r
 698         ADD_CYCLES(cycles);\r
 699 }\r
 700 \r
 701 \r
 702 void m68k_end_timeslice(void)\r
 703 {\r
 704         m68ki_initial_cycles = GET_CYCLES();\r
 705         SET_CYCLES(0);\r
 706 }\r
 707 \r
 708 \r
 709 /* ASG: rewrote so that the int_level is a mask of the IPL0/IPL1/IPL2 bits */\r
 710 /* KS: Modified so that IPL* bits match with mask positions in the SR\r
 711  *     and cleaned out remenants of the interrupt controller.\r
 712  */\r
 713 void m68k_set_irq(unsigned int int_level)\r
 714 {\r
 715         uint old_level = CPU_INT_LEVEL;\r
 716         CPU_INT_LEVEL = int_level << 8;\r
 717 \r
 718         /* A transition from < 7 to 7 always interrupts (NMI) */\r
 719         /* Note: Level 7 can also level trigger like a normal IRQ */\r
 720         if(old_level != 0x0700 && CPU_INT_LEVEL == 0x0700)\r
 721                 m68ki_exception_interrupt(7); /* Edge triggered level 7 (NMI) */\r
 722         else\r
 723                 m68ki_check_interrupts(); /* Level triggered (IRQ) */\r
 724 }\r
 725 \r
 726 \r
 727 /* Pulse the RESET line on the CPU */\r
 728 void m68k_pulse_reset(void)\r
 729 {\r
 730         static uint emulation_initialized = 0;\r
 731 \r
 732         /* The first call to this function initializes the opcode handler jump table */\r
 733         if(!emulation_initialized)\r
 734         {\r
 735                 m68ki_build_opcode_table();\r
 736                 m68k_set_int_ack_callback(NULL);\r
 737                 m68k_set_bkpt_ack_callback(NULL);\r
 738                 m68k_set_reset_instr_callback(NULL);\r
 739                 m68k_set_pc_changed_callback(NULL);\r
 740                 m68k_set_fc_callback(NULL);\r
 741                 m68k_set_instr_hook_callback(NULL);\r
 742 \r
 743                 emulation_initialized = 1;\r
 744         }\r
 745 \r
 746 \r
 747         if(CPU_TYPE == 0)       /* KW 990319 */\r
 748                 m68k_set_cpu_type(M68K_CPU_TYPE_68000);\r
 749 \r
 750         /* Clear all stop levels and eat up all remaining cycles */\r
 751         CPU_STOPPED = 0;\r
 752         SET_CYCLES(0);\r
 753 \r
 754         /* Turn off tracing */\r
 755         FLAG_T1 = FLAG_T0 = 0;\r
 756         m68ki_clear_trace();\r
 757         /* Interrupt mask to level 7 */\r
 758         FLAG_INT_MASK = 0x0700;\r
 759         /* Reset VBR */\r
 760         REG_VBR = 0;\r
 761         /* Go to supervisor mode */\r
 762         m68ki_set_sm_flag(SFLAG_SET | MFLAG_CLEAR);\r
 763 \r
 764         /* Invalidate the prefetch queue */\r
 765 #if M68K_EMULATE_PREFETCH\r
 766         /* Set to arbitrary number since our first fetch is from 0 */\r
 767         CPU_PREF_ADDR = 0x1000;\r
 768 #endif /* M68K_EMULATE_PREFETCH */\r
 769 \r
 770         /* Read the initial stack pointer and program counter */\r
 771         m68ki_jump(0);\r
 772         REG_SP = m68ki_read_imm_32();\r
 773         REG_PC = m68ki_read_imm_32();\r
 774         m68ki_jump(REG_PC);\r
 775 }\r
 776 \r
 777 /* Pulse the HALT line on the CPU */\r
 778 void m68k_pulse_halt(void)\r
 779 {\r
 780         CPU_STOPPED |= STOP_LEVEL_HALT;\r
 781 }\r
 782 \r
 783 \r
 784 /* Get and set the current CPU context */\r
 785 /* This is to allow for multiple CPUs */\r
 786 unsigned int m68k_context_size()\r
 787 {\r
 788         return sizeof(m68ki_cpu_core);\r
 789 }\r
 790 \r
 791 unsigned int m68k_get_context(void* dst)\r
 792 {\r
 793         if(dst) *(m68ki_cpu_core*)dst = m68ki_cpu;\r
 794         return sizeof(m68ki_cpu_core);\r
 795 }\r
 796 \r
 797 void m68k_set_context(void* src)\r
 798 {\r
 799         if(src) m68ki_cpu = *(m68ki_cpu_core*)src;\r
 800 }\r
 801 \r
 802 void m68k_save_context( void (*save_value)(char*, unsigned int))\r
 803 {\r
 804         if(!save_value)\r
 805                 return;\r
 806 \r
 807         save_value("CPU_TYPE"  , m68k_get_reg(NULL, M68K_REG_CPU_TYPE));\r
 808         save_value("D0"        , REG_D[0]);\r
 809         save_value("D1"        , REG_D[1]);\r
 810         save_value("D2"        , REG_D[2]);\r
 811         save_value("D3"        , REG_D[3]);\r
 812         save_value("D4"        , REG_D[4]);\r
 813         save_value("D5"        , REG_D[5]);\r
 814         save_value("D6"        , REG_D[6]);\r
 815         save_value("D7"        , REG_D[7]);\r
 816         save_value("A0"        , REG_A[0]);\r
 817         save_value("A1"        , REG_A[1]);\r
 818         save_value("A2"        , REG_A[2]);\r
 819         save_value("A3"        , REG_A[3]);\r
 820         save_value("A4"        , REG_A[4]);\r
 821         save_value("A5"        , REG_A[5]);\r
 822         save_value("A6"        , REG_A[6]);\r
 823         save_value("A7"        , REG_A[7]);\r
 824         save_value("PPC"       , REG_PPC);\r
 825         save_value("PC"        , REG_PC);\r
 826         save_value("USP"       , REG_USP);\r
 827         save_value("ISP"       , REG_ISP);\r
 828         save_value("MSP"       , REG_MSP);\r
 829         save_value("VBR"       , REG_VBR);\r
 830         save_value("SFC"       , REG_SFC);\r
 831         save_value("DFC"       , REG_DFC);\r
 832         save_value("CACR"      , REG_CACR);\r
 833         save_value("CAAR"      , REG_CAAR);\r
 834         save_value("SR"        , m68ki_get_sr());\r
 835         save_value("INT_LEVEL" , CPU_INT_LEVEL);\r
 836         save_value("INT_CYCLES", CPU_INT_CYCLES);\r
 837         save_value("STOPPED"   , (CPU_STOPPED & STOP_LEVEL_STOP) != 0);\r
 838         save_value("HALTED"    , (CPU_STOPPED & STOP_LEVEL_HALT) != 0);\r
 839         save_value("PREF_ADDR" , CPU_PREF_ADDR);\r
 840         save_value("PREF_DATA" , CPU_PREF_DATA);\r
 841 }\r
 842 \r
 843 void m68k_load_context(unsigned int (*load_value)(char*))\r
 844 {\r
 845         unsigned int temp;\r
 846 \r
 847         m68k_set_cpu_type(load_value("CPU_TYPE"));\r
 848         REG_PPC = load_value("PPC");\r
 849         REG_PC = load_value("PC");\r
 850         m68ki_jump(REG_PC);\r
 851         CPU_INT_LEVEL = 0;\r
 852         m68ki_set_sr_noint(load_value("SR"));\r
 853         REG_D[0]       = load_value("D0");\r
 854         REG_D[1]       = load_value("D1");\r
 855         REG_D[2]       = load_value("D2");\r
 856         REG_D[3]       = load_value("D3");\r
 857         REG_D[4]       = load_value("D4");\r
 858         REG_D[5]       = load_value("D5");\r
 859         REG_D[6]       = load_value("D6");\r
 860         REG_D[7]       = load_value("D7");\r
 861         REG_A[0]       = load_value("A0");\r
 862         REG_A[1]       = load_value("A1");\r
 863         REG_A[2]       = load_value("A2");\r
 864         REG_A[3]       = load_value("A3");\r
 865         REG_A[4]       = load_value("A4");\r
 866         REG_A[5]       = load_value("A5");\r
 867         REG_A[6]       = load_value("A6");\r
 868         REG_A[7]       = load_value("A7");\r
 869         REG_USP        = load_value("USP");\r
 870         REG_ISP        = load_value("ISP");\r
 871         REG_MSP        = load_value("MSP");\r
 872         REG_VBR        = load_value("VBR");\r
 873         REG_SFC        = load_value("SFC");\r
 874         REG_DFC        = load_value("DFC");\r
 875         REG_CACR       = load_value("CACR");\r
 876         REG_CAAR       = load_value("CAAR");\r
 877         CPU_INT_LEVEL  = load_value("INT_LEVEL");\r
 878         CPU_INT_CYCLES = load_value("INT_CYCLES");\r
 879 \r
 880         CPU_STOPPED = 0;\r
 881         temp           = load_value("STOPPED");\r
 882         if(temp) CPU_STOPPED |= STOP_LEVEL_STOP;\r
 883         temp           = load_value("HALTED");\r
 884         if(temp) CPU_STOPPED |= STOP_LEVEL_HALT;\r
 885 \r
 886         CPU_PREF_ADDR  = load_value("PREF_ADDR");\r
 887         CPU_PREF_DATA  = load_value("PREF_DATA");\r
 888 }\r
 889 \r
 890 \r
 891 \r
 892 /* ======================================================================== */\r
 893 /* ============================== END OF FILE ============================= */\r
 894 /* ======================================================================== */\r