1 /* ======================================================================== */
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2 /* ========================= LICENSING & COPYRIGHT ======================== */
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3 /* ======================================================================== */
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8 * A portable Motorola M680x0 processor emulation engine.
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9 * Copyright 1998-2001 Karl Stenerud. All rights reserved.
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11 * This code may be freely used for non-commercial purposes as long as this
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12 * copyright notice remains unaltered in the source code and any binary files
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13 * containing this code in compiled form.
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15 * All other lisencing terms must be negotiated with the author
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18 * The latest version of this code can be obtained at:
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19 * http://kstenerud.cjb.net
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24 /* Input file for m68kmake
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25 * -----------------------
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27 * All sections begin with 80 X's in a row followed by an end-of-line
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29 * After this, m68kmake will expect to find one of the following section
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31 * M68KMAKE_PROTOTYPE_HEADER - header for opcode handler prototypes
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32 * M68KMAKE_PROTOTYPE_FOOTER - footer for opcode handler prototypes
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33 * M68KMAKE_TABLE_HEADER - header for opcode handler jumptable
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34 * M68KMAKE_TABLE_FOOTER - footer for opcode handler jumptable
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35 * M68KMAKE_TABLE_BODY - the table itself
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36 * M68KMAKE_OPCODE_HANDLER_HEADER - header for opcode handler implementation
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37 * M68KMAKE_OPCODE_HANDLER_FOOTER - footer for opcode handler implementation
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38 * M68KMAKE_OPCODE_HANDLER_BODY - body section for opcode handler implementation
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40 * NOTE: M68KMAKE_OPCODE_HANDLER_BODY must be last in the file and
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41 * M68KMAKE_TABLE_BODY must be second last in the file.
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43 * The M68KMAKE_OPHANDLER_BODY section contains the opcode handler
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44 * primitives themselves. Each opcode handler begins with:
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45 * M68KMAKE_OP(A, B, C, D)
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47 * where A is the opcode handler name, B is the size of the operation,
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48 * C denotes any special processing mode, and D denotes a specific
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50 * For C and D where nothing is specified, use "."
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53 * M68KMAKE_OP(abcd, 8, rr, .) abcd, size 8, register to register, default EA
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54 * M68KMAKE_OP(abcd, 8, mm, ax7) abcd, size 8, memory to memory, register X is A7
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55 * M68KMAKE_OP(tst, 16, ., pcix) tst, size 16, PCIX addressing
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57 * All opcode handler primitives end with a closing curly brace "}" at column 1
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59 * NOTE: Do not place a M68KMAKE_OP() directive inside the opcode handler,
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60 * and do not put a closing curly brace at column 1 unless it is
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61 * marking the end of the handler!
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63 * Inside the handler, m68kmake will recognize M68KMAKE_GET_OPER_xx_xx,
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64 * M68KMAKE_GET_EA_xx_xx, and M68KMAKE_CC directives, and create multiple
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65 * opcode handlers to handle variations in the opcode handler.
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66 * Note: M68KMAKE_CC will only be interpreted in condition code opcodes.
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67 * As well, M68KMAKE_GET_EA_xx_xx and M68KMAKE_GET_OPER_xx_xx will only
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68 * be interpreted on instructions where the corresponding table entry
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69 * specifies multiple effective addressing modes.
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71 * clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
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73 * This table entry says that the clr.l opcde has 7 variations (A+-DXWL).
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74 * It is run in user or supervisor mode for all CPUs, and uses 12 cycles for
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75 * 68000, 6 cycles for 68010, and 4 cycles for 68020.
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78 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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79 M68KMAKE_PROTOTYPE_HEADER
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81 #ifndef M68KOPS__HEADER
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82 #define M68KOPS__HEADER
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84 /* ======================================================================== */
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85 /* ============================ OPCODE HANDLERS =========================== */
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86 /* ======================================================================== */
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90 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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91 M68KMAKE_PROTOTYPE_FOOTER
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94 /* Build the opcode handler table */
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95 void m68ki_build_opcode_table(void);
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97 extern void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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98 extern unsigned char m68ki_cycles[][0x10000];
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101 /* ======================================================================== */
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102 /* ============================== END OF FILE ============================= */
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103 /* ======================================================================== */
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105 #endif /* M68KOPS__HEADER */
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109 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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110 M68KMAKE_TABLE_HEADER
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112 /* ======================================================================== */
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113 /* ========================= OPCODE TABLE BUILDER ========================= */
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114 /* ======================================================================== */
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116 #include "m68kops.h"
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118 #define NUM_CPU_TYPES 3
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120 void (*m68ki_instruction_jump_table[0x10000])(void); /* opcode handler jump table */
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121 unsigned char m68ki_cycles[NUM_CPU_TYPES][0x10000]; /* Cycles used by CPU type */
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123 /* This is used to generate the opcode handler jump table */
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126 void (*opcode_handler)(void); /* handler function */
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127 unsigned int mask; /* mask on opcode */
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128 unsigned int match; /* what to match after masking */
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129 unsigned char cycles[NUM_CPU_TYPES]; /* cycles each cpu type takes */
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130 } opcode_handler_struct;
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133 /* Opcode handler table */
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134 static opcode_handler_struct m68k_opcode_handler_table[] =
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136 /* function mask match 000 010 020 */
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140 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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141 M68KMAKE_TABLE_FOOTER
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143 {0, 0, 0, {0, 0, 0}}
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147 /* Build the opcode handler jump table */
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148 void m68ki_build_opcode_table(void)
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150 opcode_handler_struct *ostruct;
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156 for(i = 0; i < 0x10000; i++)
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158 /* default to illegal */
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159 m68ki_instruction_jump_table[i] = m68k_op_illegal;
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160 for(k=0;k<NUM_CPU_TYPES;k++)
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161 m68ki_cycles[k][i] = 0;
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164 ostruct = m68k_opcode_handler_table;
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165 while(ostruct->mask != 0xff00)
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167 for(i = 0;i < 0x10000;i++)
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169 if((i & ostruct->mask) == ostruct->match)
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171 m68ki_instruction_jump_table[i] = ostruct->opcode_handler;
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172 for(k=0;k<NUM_CPU_TYPES;k++)
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173 m68ki_cycles[k][i] = ostruct->cycles[k];
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178 while(ostruct->mask == 0xff00)
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180 for(i = 0;i <= 0xff;i++)
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182 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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183 for(k=0;k<NUM_CPU_TYPES;k++)
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184 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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188 while(ostruct->mask == 0xf1f8)
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190 for(i = 0;i < 8;i++)
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192 for(j = 0;j < 8;j++)
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194 instr = ostruct->match | (i << 9) | j;
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195 m68ki_instruction_jump_table[instr] = ostruct->opcode_handler;
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196 for(k=0;k<NUM_CPU_TYPES;k++)
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197 m68ki_cycles[k][instr] = ostruct->cycles[k];
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198 if((instr & 0xf000) == 0xe000 && (!(instr & 0x20)))
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199 m68ki_cycles[0][instr] = m68ki_cycles[1][instr] = ostruct->cycles[k] + ((((j-1)&7)+1)<<1);
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204 while(ostruct->mask == 0xfff0)
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206 for(i = 0;i <= 0x0f;i++)
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208 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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209 for(k=0;k<NUM_CPU_TYPES;k++)
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210 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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214 while(ostruct->mask == 0xf1ff)
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216 for(i = 0;i <= 0x07;i++)
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218 m68ki_instruction_jump_table[ostruct->match | (i << 9)] = ostruct->opcode_handler;
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219 for(k=0;k<NUM_CPU_TYPES;k++)
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220 m68ki_cycles[k][ostruct->match | (i << 9)] = ostruct->cycles[k];
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224 while(ostruct->mask == 0xfff8)
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226 for(i = 0;i <= 0x07;i++)
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228 m68ki_instruction_jump_table[ostruct->match | i] = ostruct->opcode_handler;
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229 for(k=0;k<NUM_CPU_TYPES;k++)
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230 m68ki_cycles[k][ostruct->match | i] = ostruct->cycles[k];
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234 while(ostruct->mask == 0xffff)
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236 m68ki_instruction_jump_table[ostruct->match] = ostruct->opcode_handler;
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237 for(k=0;k<NUM_CPU_TYPES;k++)
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238 m68ki_cycles[k][ostruct->match] = ostruct->cycles[k];
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244 /* ======================================================================== */
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245 /* ============================== END OF FILE ============================= */
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246 /* ======================================================================== */
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250 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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251 M68KMAKE_OPCODE_HANDLER_HEADER
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253 #include "m68kcpu.h"
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255 /* ======================================================================== */
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256 /* ========================= INSTRUCTION HANDLERS ========================= */
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257 /* ======================================================================== */
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261 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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262 M68KMAKE_OPCODE_HANDLER_FOOTER
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264 /* ======================================================================== */
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265 /* ============================== END OF FILE ============================= */
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266 /* ======================================================================== */
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270 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
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271 M68KMAKE_TABLE_BODY
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273 The following table is arranged as follows:
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275 name: Opcode mnemonic
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277 size: Operation size
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279 spec proc: Special processing mode:
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282 r: register operand
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283 rr: register to register
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284 mm: memory to memory
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285 er: effective address to register
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286 re: register to effective address
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287 dd: data register to data register
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288 da: data register to address register
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289 aa: address register to address register
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290 cr: control register to register
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291 rc: register to control register
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292 toc: to condition code register
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293 tos: to status register
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294 tou: to user stack pointer
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295 frc: from condition code register
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296 frs: from status register
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297 fru: from user stack pointer
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298 * for move.x, the special processing mode is a specific
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299 destination effective addressing mode.
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301 spec ea: Specific effective addressing mode:
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305 a: address register
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306 ai: address register indirect
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307 pi: address register indirect with postincrement
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308 pd: address register indirect with predecrement
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309 di: address register indirect with displacement
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310 ix: address register indirect with index
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311 aw: absolute word address
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312 al: absolute long address
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313 pcdi: program counter relative with displacement
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314 pcix: program counter relative with index
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315 a7: register specified in instruction is A7
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316 ax7: register field X of instruction is A7
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317 ay7: register field Y of instruction is A7
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318 axy7: register fields X and Y of instruction are A7
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320 bit pattern: Pattern to recognize this opcode. "." means don't care.
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322 allowed ea: List of allowed addressing modes:
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324 A: address register indirect
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325 +: ARI (address register indirect) with postincrement
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326 -: ARI with predecrement
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327 D: ARI with displacement
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329 W: absolute word address
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330 L: absolute long address
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331 d: program counter indirect with displacement
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332 x: program counter indirect with index
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334 mode: CPU operating mode for each cpu type. U = user or supervisor,
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335 S = supervisor only, "." = opcode not present.
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337 cpu cycles: Base number of cycles required to execute this opcode on the
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338 specified CPU type.
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339 Use "." if CPU does not have this opcode.
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343 spec spec allowed ea mode cpu cycles
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344 name size proc ea bit pattern A+-DXWLdxI 0 1 2 000 010 020 comments
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345 ====== ==== ==== ==== ================ ========== = = = === === === =============
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346 M68KMAKE_TABLE_START
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347 1010 0 . . 1010............ .......... U U U 4 4 4
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348 1111 0 . . 1111............ .......... U U U 4 4 4
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349 abcd 8 rr . 1100...100000... .......... U U U 6 6 4
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350 abcd 8 mm ax7 1100111100001... .......... U U U 18 18 16
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351 abcd 8 mm ay7 1100...100001111 .......... U U U 18 18 16
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352 abcd 8 mm axy7 1100111100001111 .......... U U U 18 18 16
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353 abcd 8 mm . 1100...100001... .......... U U U 18 18 16
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354 add 8 er d 1101...000000... .......... U U U 4 4 2
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355 add 8 er . 1101...000...... A+-DXWLdxI U U U 4 4 2
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356 add 16 er d 1101...001000... .......... U U U 4 4 2
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357 add 16 er a 1101...001001... .......... U U U 4 4 2
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358 add 16 er . 1101...001...... A+-DXWLdxI U U U 4 4 2
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359 add 32 er d 1101...010000... .......... U U U 6 6 2
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360 add 32 er a 1101...010001... .......... U U U 6 6 2
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361 add 32 er . 1101...010...... A+-DXWLdxI U U U 6 6 2
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362 add 8 re . 1101...100...... A+-DXWL... U U U 8 8 4
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363 add 16 re . 1101...101...... A+-DXWL... U U U 8 8 4
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364 add 32 re . 1101...110...... A+-DXWL... U U U 12 12 4
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365 adda 16 . d 1101...011000... .......... U U U 8 8 2
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366 adda 16 . a 1101...011001... .......... U U U 8 8 2
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367 adda 16 . . 1101...011...... A+-DXWLdxI U U U 8 8 2
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368 adda 32 . d 1101...111000... .......... U U U 6 6 2
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369 adda 32 . a 1101...111001... .......... U U U 6 6 2
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370 adda 32 . . 1101...111...... A+-DXWLdxI U U U 6 6 2
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371 addi 8 . d 0000011000000... .......... U U U 8 8 2
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372 addi 8 . . 0000011000...... A+-DXWL... U U U 12 12 4
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373 addi 16 . d 0000011001000... .......... U U U 8 8 2
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374 addi 16 . . 0000011001...... A+-DXWL... U U U 12 12 4
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375 addi 32 . d 0000011010000... .......... U U U 16 14 2
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376 addi 32 . . 0000011010...... A+-DXWL... U U U 20 20 4
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377 addq 8 . d 0101...000000... .......... U U U 4 4 2
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378 addq 8 . . 0101...000...... A+-DXWL... U U U 8 8 4
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379 addq 16 . d 0101...001000... .......... U U U 4 4 2
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380 addq 16 . a 0101...001001... .......... U U U 4 4 2
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381 addq 16 . . 0101...001...... A+-DXWL... U U U 8 8 4
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382 addq 32 . d 0101...010000... .......... U U U 8 8 2
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383 addq 32 . a 0101...010001... .......... U U U 8 8 2
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384 addq 32 . . 0101...010...... A+-DXWL... U U U 12 12 4
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385 addx 8 rr . 1101...100000... .......... U U U 4 4 2
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386 addx 16 rr . 1101...101000... .......... U U U 4 4 2
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387 addx 32 rr . 1101...110000... .......... U U U 8 6 2
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388 addx 8 mm ax7 1101111100001... .......... U U U 18 18 12
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389 addx 8 mm ay7 1101...100001111 .......... U U U 18 18 12
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390 addx 8 mm axy7 1101111100001111 .......... U U U 18 18 12
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391 addx 8 mm . 1101...100001... .......... U U U 18 18 12
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392 addx 16 mm . 1101...101001... .......... U U U 18 18 12
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393 addx 32 mm . 1101...110001... .......... U U U 30 30 12
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394 and 8 er d 1100...000000... .......... U U U 4 4 2
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395 and 8 er . 1100...000...... A+-DXWLdxI U U U 4 4 2
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396 and 16 er d 1100...001000... .......... U U U 4 4 2
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397 and 16 er . 1100...001...... A+-DXWLdxI U U U 4 4 2
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398 and 32 er d 1100...010000... .......... U U U 6 6 2
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399 and 32 er . 1100...010...... A+-DXWLdxI U U U 6 6 2
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400 and 8 re . 1100...100...... A+-DXWL... U U U 8 8 4
\r
401 and 16 re . 1100...101...... A+-DXWL... U U U 8 8 4
\r
402 and 32 re . 1100...110...... A+-DXWL... U U U 12 12 4
\r
403 andi 16 toc . 0000001000111100 .......... U U U 20 16 12
\r
404 andi 16 tos . 0000001001111100 .......... S S S 20 16 12
\r
405 andi 8 . d 0000001000000... .......... U U U 8 8 2
\r
406 andi 8 . . 0000001000...... A+-DXWL... U U U 12 12 4
\r
407 andi 16 . d 0000001001000... .......... U U U 8 8 2
\r
408 andi 16 . . 0000001001...... A+-DXWL... U U U 12 12 4
\r
409 andi 32 . d 0000001010000... .......... U U U 14 14 2
\r
410 andi 32 . . 0000001010...... A+-DXWL... U U U 20 20 4
\r
411 asr 8 s . 1110...000000... .......... U U U 6 6 6
\r
412 asr 16 s . 1110...001000... .......... U U U 6 6 6
\r
413 asr 32 s . 1110...010000... .......... U U U 8 8 6
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414 asr 8 r . 1110...000100... .......... U U U 6 6 6
\r
415 asr 16 r . 1110...001100... .......... U U U 6 6 6
\r
416 asr 32 r . 1110...010100... .......... U U U 8 8 6
\r
417 asr 16 . . 1110000011...... A+-DXWL... U U U 8 8 5
\r
418 asl 8 s . 1110...100000... .......... U U U 6 6 8
\r
419 asl 16 s . 1110...101000... .......... U U U 6 6 8
\r
420 asl 32 s . 1110...110000... .......... U U U 8 8 8
\r
421 asl 8 r . 1110...100100... .......... U U U 6 6 8
\r
422 asl 16 r . 1110...101100... .......... U U U 6 6 8
\r
423 asl 32 r . 1110...110100... .......... U U U 8 8 8
\r
424 asl 16 . . 1110000111...... A+-DXWL... U U U 8 8 6
\r
425 bcc 8 . . 0110............ .......... U U U 8 8 6
\r
426 bcc 16 . . 0110....00000000 .......... U U U 10 10 6
\r
427 bcc 32 . . 0110....11111111 .......... . . U . . 6
\r
428 bchg 8 r . 0000...101...... A+-DXWL... U U U 8 8 4
\r
429 bchg 32 r d 0000...101000... .......... U U U 8 8 4
\r
430 bchg 8 s . 0000100001...... A+-DXWL... U U U 12 12 4
\r
431 bchg 32 s d 0000100001000... .......... U U U 12 12 4
\r
432 bclr 8 r . 0000...110...... A+-DXWL... U U U 8 10 4
\r
433 bclr 32 r d 0000...110000... .......... U U U 10 10 4
\r
434 bclr 8 s . 0000100010...... A+-DXWL... U U U 12 12 4
\r
435 bclr 32 s d 0000100010000... .......... U U U 14 14 4
\r
436 bfchg 32 . d 1110101011000... .......... . . U . . 12 timing not quite correct
\r
437 bfchg 32 . . 1110101011...... A..DXWL... . . U . . 20
\r
438 bfclr 32 . d 1110110011000... .......... . . U . . 12
\r
439 bfclr 32 . . 1110110011...... A..DXWL... . . U . . 20
\r
440 bfexts 32 . d 1110101111000... .......... . . U . . 8
\r
441 bfexts 32 . . 1110101111...... A..DXWLdx. . . U . . 15
\r
442 bfextu 32 . d 1110100111000... .......... . . U . . 8
\r
443 bfextu 32 . . 1110100111...... A..DXWLdx. . . U . . 15
\r
444 bfffo 32 . d 1110110111000... .......... . . U . . 18
\r
445 bfffo 32 . . 1110110111...... A..DXWLdx. . . U . . 28
\r
446 bfins 32 . d 1110111111000... .......... . . U . . 10
\r
447 bfins 32 . . 1110111111...... A..DXWL... . . U . . 17
\r
448 bfset 32 . d 1110111011000... .......... . . U . . 12
\r
449 bfset 32 . . 1110111011...... A..DXWL... . . U . . 20
\r
450 bftst 32 . d 1110100011000... .......... . . U . . 6
\r
451 bftst 32 . . 1110100011...... A..DXWLdx. . . U . . 13
\r
452 bkpt 0 . . 0100100001001... .......... . U U . 10 10
\r
453 bra 8 . . 01100000........ .......... U U U 10 10 10
\r
454 bra 16 . . 0110000000000000 .......... U U U 10 10 10
\r
455 bra 32 . . 0110000011111111 .......... U U U . . 10
\r
456 bset 32 r d 0000...111000... .......... U U U 8 8 4
\r
457 bset 8 r . 0000...111...... A+-DXWL... U U U 8 8 4
\r
458 bset 8 s . 0000100011...... A+-DXWL... U U U 12 12 4
\r
459 bset 32 s d 0000100011000... .......... U U U 12 12 4
\r
460 bsr 8 . . 01100001........ .......... U U U 18 18 7
\r
461 bsr 16 . . 0110000100000000 .......... U U U 18 18 7
\r
462 bsr 32 . . 0110000111111111 .......... . . U . . 7
\r
463 btst 8 r . 0000...100...... A+-DXWLdxI U U U 4 4 4
\r
464 btst 32 r d 0000...100000... .......... U U U 6 6 4
\r
465 btst 8 s . 0000100000...... A+-DXWLdx. U U U 8 8 4
\r
466 btst 32 s d 0000100000000... .......... U U U 10 10 4
\r
467 callm 32 . . 0000011011...... A..DXWLdx. . . U . . 60 not properly emulated
\r
468 cas 8 . . 0000101011...... A+-DXWL... . . U . . 12
\r
469 cas 16 . . 0000110011...... A+-DXWL... . . U . . 12
\r
470 cas 32 . . 0000111011...... A+-DXWL... . . U . . 12
\r
471 cas2 16 . . 0000110011111100 .......... . . U . . 12
\r
472 cas2 32 . . 0000111011111100 .......... . . U . . 12
\r
473 chk 16 . d 0100...110000... .......... U U U 10 8 8
\r
474 chk 16 . . 0100...110...... A+-DXWLdxI U U U 10 8 8
\r
475 chk 32 . d 0100...100000... .......... . . U . . 8
\r
476 chk 32 . . 0100...100...... A+-DXWLdxI . . U . . 8
\r
477 chk2cmp2 8 . . 0000000011...... A..DXWLdx. . . U . . 18
\r
478 chk2cmp2 16 . . 0000001011...... A..DXWLdx. . . U . . 18
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479 chk2cmp2 32 . . 0000010011...... A..DXWLdx. . . U . . 18
\r
480 clr 8 . d 0100001000000... .......... U U U 4 4 2
\r
481 clr 8 . . 0100001000...... A+-DXWL... U U U 8 4 4
\r
482 clr 16 . d 0100001001000... .......... U U U 4 4 2
\r
483 clr 16 . . 0100001001...... A+-DXWL... U U U 8 4 4
\r
484 clr 32 . d 0100001010000... .......... U U U 6 6 2
\r
485 clr 32 . . 0100001010...... A+-DXWL... U U U 12 6 4
\r
486 cmp 8 . d 1011...000000... .......... U U U 4 4 2
\r
487 cmp 8 . . 1011...000...... A+-DXWLdxI U U U 4 4 2
\r
488 cmp 16 . d 1011...001000... .......... U U U 4 4 2
\r
489 cmp 16 . a 1011...001001... .......... U U U 4 4 2
\r
490 cmp 16 . . 1011...001...... A+-DXWLdxI U U U 4 4 2
\r
491 cmp 32 . d 1011...010000... .......... U U U 6 6 2
\r
492 cmp 32 . a 1011...010001... .......... U U U 6 6 2
\r
493 cmp 32 . . 1011...010...... A+-DXWLdxI U U U 6 6 2
\r
494 cmpa 16 . d 1011...011000... .......... U U U 6 6 4
\r
495 cmpa 16 . a 1011...011001... .......... U U U 6 6 4
\r
496 cmpa 16 . . 1011...011...... A+-DXWLdxI U U U 6 6 4
\r
497 cmpa 32 . d 1011...111000... .......... U U U 6 6 4
\r
498 cmpa 32 . a 1011...111001... .......... U U U 6 6 4
\r
499 cmpa 32 . . 1011...111...... A+-DXWLdxI U U U 6 6 4
\r
500 cmpi 8 . d 0000110000000... .......... U U U 8 8 2
\r
501 cmpi 8 . . 0000110000...... A+-DXWL... U U U 8 8 2
\r
502 cmpi 8 . pcdi 0000110000111010 .......... . . U . . 7
\r
503 cmpi 8 . pcix 0000110000111011 .......... . . U . . 9
\r
504 cmpi 16 . d 0000110001000... .......... U U U 8 8 2
\r
505 cmpi 16 . . 0000110001...... A+-DXWL... U U U 8 8 2
\r
506 cmpi 16 . pcdi 0000110001111010 .......... . . U . . 7
\r
507 cmpi 16 . pcix 0000110001111011 .......... . . U . . 9
\r
508 cmpi 32 . d 0000110010000... .......... U U U 14 12 2
\r
509 cmpi 32 . . 0000110010...... A+-DXWL... U U U 12 12 2
\r
510 cmpi 32 . pcdi 0000110010111010 .......... . . U . . 7
\r
511 cmpi 32 . pcix 0000110010111011 .......... . . U . . 9
\r
512 cmpm 8 . ax7 1011111100001... .......... U U U 12 12 9
\r
513 cmpm 8 . ay7 1011...100001111 .......... U U U 12 12 9
\r
514 cmpm 8 . axy7 1011111100001111 .......... U U U 12 12 9
\r
515 cmpm 8 . . 1011...100001... .......... U U U 12 12 9
\r
516 cmpm 16 . . 1011...101001... .......... U U U 12 12 9
\r
517 cmpm 32 . . 1011...110001... .......... U U U 20 20 9
\r
518 cpbcc 32 . . 1111...01....... .......... . . U . . 4 unemulated
\r
519 cpdbcc 32 . . 1111...001001... .......... . . U . . 4 unemulated
\r
520 cpgen 32 . . 1111...000...... .......... . . U . . 4 unemulated
\r
521 cpscc 32 . . 1111...001...... .......... . . U . . 4 unemulated
\r
522 cptrapcc 32 . . 1111...001111... .......... . . U . . 4 unemulated
\r
523 dbt 16 . . 0101000011001... .......... U U U 12 12 6
\r
524 dbf 16 . . 0101000111001... .......... U U U 14 14 6
\r
525 dbcc 16 . . 0101....11001... .......... U U U 12 12 6
\r
526 divs 16 . d 1000...111000... .......... U U U 158 122 56
\r
527 divs 16 . . 1000...111...... A+-DXWLdxI U U U 158 122 56
\r
528 divu 16 . d 1000...011000... .......... U U U 140 108 44
\r
529 divu 16 . . 1000...011...... A+-DXWLdxI U U U 140 108 44
\r
530 divl 32 . d 0100110001000... .......... . . U . . 84
\r
531 divl 32 . . 0100110001...... A+-DXWLdxI . . U . . 84
\r
532 eor 8 . d 1011...100000... .......... U U U 4 4 2
\r
533 eor 8 . . 1011...100...... A+-DXWL... U U U 8 8 4
\r
534 eor 16 . d 1011...101000... .......... U U U 4 4 2
\r
535 eor 16 . . 1011...101...... A+-DXWL... U U U 8 8 4
\r
536 eor 32 . d 1011...110000... .......... U U U 8 6 2
\r
537 eor 32 . . 1011...110...... A+-DXWL... U U U 12 12 4
\r
538 eori 16 toc . 0000101000111100 .......... U U U 20 16 12
\r
539 eori 16 tos . 0000101001111100 .......... S S S 20 16 12
\r
540 eori 8 . d 0000101000000... .......... U U U 8 8 2
\r
541 eori 8 . . 0000101000...... A+-DXWL... U U U 12 12 4
\r
542 eori 16 . d 0000101001000... .......... U U U 8 8 2
\r
543 eori 16 . . 0000101001...... A+-DXWL... U U U 12 12 4
\r
544 eori 32 . d 0000101010000... .......... U U U 16 14 2
\r
545 eori 32 . . 0000101010...... A+-DXWL... U U U 20 20 4
\r
546 exg 32 dd . 1100...101000... .......... U U U 6 6 2
\r
547 exg 32 aa . 1100...101001... .......... U U U 6 6 2
\r
548 exg 32 da . 1100...110001... .......... U U U 6 6 2
\r
549 ext 16 . . 0100100010000... .......... U U U 4 4 4
\r
550 ext 32 . . 0100100011000... .......... U U U 4 4 4
\r
551 extb 32 . . 0100100111000... .......... . . U . . 4
\r
552 illegal 0 . . 0100101011111100 .......... U U U 4 4 4
\r
553 jmp 32 . . 0100111011...... A..DXWLdx. U U U 4 4 0
\r
554 jsr 32 . . 0100111010...... A..DXWLdx. U U U 12 12 0
\r
555 lea 32 . . 0100...111...... A..DXWLdx. U U U 0 0 2
\r
556 link 16 . a7 0100111001010111 .......... U U U 16 16 5
\r
557 link 16 . . 0100111001010... .......... U U U 16 16 5
\r
558 link 32 . a7 0100100000001111 .......... . . U . . 6
\r
559 link 32 . . 0100100000001... .......... . . U . . 6
\r
560 lsr 8 s . 1110...000001... .......... U U U 6 6 4
\r
561 lsr 16 s . 1110...001001... .......... U U U 6 6 4
\r
562 lsr 32 s . 1110...010001... .......... U U U 8 8 4
\r
563 lsr 8 r . 1110...000101... .......... U U U 6 6 6
\r
564 lsr 16 r . 1110...001101... .......... U U U 6 6 6
\r
565 lsr 32 r . 1110...010101... .......... U U U 8 8 6
\r
566 lsr 16 . . 1110001011...... A+-DXWL... U U U 8 8 5
\r
567 lsl 8 s . 1110...100001... .......... U U U 6 6 4
\r
568 lsl 16 s . 1110...101001... .......... U U U 6 6 4
\r
569 lsl 32 s . 1110...110001... .......... U U U 8 8 4
\r
570 lsl 8 r . 1110...100101... .......... U U U 6 6 6
\r
571 lsl 16 r . 1110...101101... .......... U U U 6 6 6
\r
572 lsl 32 r . 1110...110101... .......... U U U 8 8 6
\r
573 lsl 16 . . 1110001111...... A+-DXWL... U U U 8 8 5
\r
574 move 8 d d 0001...000000... .......... U U U 4 4 2
\r
575 move 8 d . 0001...000...... A+-DXWLdxI U U U 4 4 2
\r
576 move 8 ai d 0001...010000... .......... U U U 8 8 4
\r
577 move 8 ai . 0001...010...... A+-DXWLdxI U U U 8 8 4
\r
578 move 8 pi d 0001...011000... .......... U U U 8 8 4
\r
579 move 8 pi . 0001...011...... A+-DXWLdxI U U U 8 8 4
\r
580 move 8 pi7 d 0001111011000... .......... U U U 8 8 4
\r
581 move 8 pi7 . 0001111011...... A+-DXWLdxI U U U 8 8 4
\r
582 move 8 pd d 0001...100000... .......... U U U 8 8 5
\r
583 move 8 pd . 0001...100...... A+-DXWLdxI U U U 8 8 5
\r
584 move 8 pd7 d 0001111100000... .......... U U U 8 8 5
\r
585 move 8 pd7 . 0001111100...... A+-DXWLdxI U U U 8 8 5
\r
586 move 8 di d 0001...101000... .......... U U U 12 12 5
\r
587 move 8 di . 0001...101...... A+-DXWLdxI U U U 12 12 5
\r
588 move 8 ix d 0001...110000... .......... U U U 14 14 7
\r
589 move 8 ix . 0001...110...... A+-DXWLdxI U U U 14 14 7
\r
590 move 8 aw d 0001000111000... .......... U U U 12 12 4
\r
591 move 8 aw . 0001000111...... A+-DXWLdxI U U U 12 12 4
\r
592 move 8 al d 0001001111000... .......... U U U 16 16 6
\r
593 move 8 al . 0001001111...... A+-DXWLdxI U U U 16 16 6
\r
594 move 16 d d 0011...000000... .......... U U U 4 4 2
\r
595 move 16 d a 0011...000001... .......... U U U 4 4 2
\r
596 move 16 d . 0011...000...... A+-DXWLdxI U U U 4 4 2
\r
597 move 16 ai d 0011...010000... .......... U U U 8 8 4
\r
598 move 16 ai a 0011...010001... .......... U U U 8 8 4
\r
599 move 16 ai . 0011...010...... A+-DXWLdxI U U U 8 8 4
\r
600 move 16 pi d 0011...011000... .......... U U U 8 8 4
\r
601 move 16 pi a 0011...011001... .......... U U U 8 8 4
\r
602 move 16 pi . 0011...011...... A+-DXWLdxI U U U 8 8 4
\r
603 move 16 pd d 0011...100000... .......... U U U 8 8 5
\r
604 move 16 pd a 0011...100001... .......... U U U 8 8 5
\r
605 move 16 pd . 0011...100...... A+-DXWLdxI U U U 8 8 5
\r
606 move 16 di d 0011...101000... .......... U U U 12 12 5
\r
607 move 16 di a 0011...101001... .......... U U U 12 12 5
\r
608 move 16 di . 0011...101...... A+-DXWLdxI U U U 12 12 5
\r
609 move 16 ix d 0011...110000... .......... U U U 14 14 7
\r
610 move 16 ix a 0011...110001... .......... U U U 14 14 7
\r
611 move 16 ix . 0011...110...... A+-DXWLdxI U U U 14 14 7
\r
612 move 16 aw d 0011000111000... .......... U U U 12 12 4
\r
613 move 16 aw a 0011000111001... .......... U U U 12 12 4
\r
614 move 16 aw . 0011000111...... A+-DXWLdxI U U U 12 12 4
\r
615 move 16 al d 0011001111000... .......... U U U 16 16 6
\r
616 move 16 al a 0011001111001... .......... U U U 16 16 6
\r
617 move 16 al . 0011001111...... A+-DXWLdxI U U U 16 16 6
\r
618 move 32 d d 0010...000000... .......... U U U 4 4 2
\r
619 move 32 d a 0010...000001... .......... U U U 4 4 2
\r
620 move 32 d . 0010...000...... A+-DXWLdxI U U U 4 4 2
\r
621 move 32 ai d 0010...010000... .......... U U U 12 12 4
\r
622 move 32 ai a 0010...010001... .......... U U U 12 12 4
\r
623 move 32 ai . 0010...010...... A+-DXWLdxI U U U 12 12 4
\r
624 move 32 pi d 0010...011000... .......... U U U 12 12 4
\r
625 move 32 pi a 0010...011001... .......... U U U 12 12 4
\r
626 move 32 pi . 0010...011...... A+-DXWLdxI U U U 12 12 4
\r
627 move 32 pd d 0010...100000... .......... U U U 12 14 5
\r
628 move 32 pd a 0010...100001... .......... U U U 12 14 5
\r
629 move 32 pd . 0010...100...... A+-DXWLdxI U U U 12 14 5
\r
630 move 32 di d 0010...101000... .......... U U U 16 16 5
\r
631 move 32 di a 0010...101001... .......... U U U 16 16 5
\r
632 move 32 di . 0010...101...... A+-DXWLdxI U U U 16 16 5
\r
633 move 32 ix d 0010...110000... .......... U U U 18 18 7
\r
634 move 32 ix a 0010...110001... .......... U U U 18 18 7
\r
635 move 32 ix . 0010...110...... A+-DXWLdxI U U U 18 18 7
\r
636 move 32 aw d 0010000111000... .......... U U U 16 16 4
\r
637 move 32 aw a 0010000111001... .......... U U U 16 16 4
\r
638 move 32 aw . 0010000111...... A+-DXWLdxI U U U 16 16 4
\r
639 move 32 al d 0010001111000... .......... U U U 20 20 6
\r
640 move 32 al a 0010001111001... .......... U U U 20 20 6
\r
641 move 32 al . 0010001111...... A+-DXWLdxI U U U 20 20 6
\r
642 movea 16 . d 0011...001000... .......... U U U 4 4 2
\r
643 movea 16 . a 0011...001001... .......... U U U 4 4 2
\r
644 movea 16 . . 0011...001...... A+-DXWLdxI U U U 4 4 2
\r
645 movea 32 . d 0010...001000... .......... U U U 4 4 2
\r
646 movea 32 . a 0010...001001... .......... U U U 4 4 2
\r
647 movea 32 . . 0010...001...... A+-DXWLdxI U U U 4 4 2
\r
648 move 16 frc d 0100001011000... .......... . U U . 4 4
\r
649 move 16 frc . 0100001011...... A+-DXWL... . U U . 8 4
\r
650 move 16 toc d 0100010011000... .......... U U U 12 12 4
\r
651 move 16 toc . 0100010011...... A+-DXWLdxI U U U 12 12 4
\r
652 move 16 frs d 0100000011000... .......... U S S 6 4 8 U only for 000
\r
653 move 16 frs . 0100000011...... A+-DXWL... U S S 8 8 8 U only for 000
\r
654 move 16 tos d 0100011011000... .......... S S S 12 12 8
\r
655 move 16 tos . 0100011011...... A+-DXWLdxI S S S 12 12 8
\r
656 move 32 fru . 0100111001101... .......... S S S 4 6 2
\r
657 move 32 tou . 0100111001100... .......... S S S 4 6 2
\r
658 movec 32 cr . 0100111001111010 .......... . S S . 12 6
\r
659 movec 32 rc . 0100111001111011 .......... . S S . 10 12
\r
660 movem 16 re pd 0100100010100... .......... U U U 8 8 4
\r
661 movem 16 re . 0100100010...... A..DXWL... U U U 8 8 4
\r
662 movem 32 re pd 0100100011100... .......... U U U 8 8 4
\r
663 movem 32 re . 0100100011...... A..DXWL... U U U 8 8 4
\r
664 movem 16 er pi 0100110010011... .......... U U U 12 12 8
\r
665 movem 16 er . 0100110010...... A..DXWLdx. U U U 12 12 8
\r
666 movem 32 er pi 0100110011011... .......... U U U 12 12 8
\r
667 movem 32 er . 0100110011...... A..DXWLdx. U U U 12 12 8
\r
668 movep 16 er . 0000...100001... .......... U U U 16 16 12
\r
669 movep 32 er . 0000...101001... .......... U U U 24 24 18
\r
670 movep 16 re . 0000...110001... .......... U U U 16 16 11
\r
671 movep 32 re . 0000...111001... .......... U U U 24 24 17
\r
672 moveq 32 . . 0111...0........ .......... U U U 4 4 2
\r
673 moves 8 . . 0000111000...... A+-DXWL... . S S . 14 5
\r
674 moves 16 . . 0000111001...... A+-DXWL... . S S . 14 5
\r
675 moves 32 . . 0000111010...... A+-DXWL... . S S . 16 5
\r
676 muls 16 . d 1100...111000... .......... U U U 54 32 27
\r
677 muls 16 . . 1100...111...... A+-DXWLdxI U U U 54 32 27
\r
678 mulu 16 . d 1100...011000... .......... U U U 54 30 27
\r
679 mulu 16 . . 1100...011...... A+-DXWLdxI U U U 54 30 27
\r
680 mull 32 . d 0100110000000... .......... . . U . . 43
\r
681 mull 32 . . 0100110000...... A+-DXWLdxI . . U . . 43
\r
682 nbcd 8 . d 0100100000000... .......... U U U 6 6 6
\r
683 nbcd 8 . . 0100100000...... A+-DXWL... U U U 8 8 6
\r
684 neg 8 . d 0100010000000... .......... U U U 4 4 2
\r
685 neg 8 . . 0100010000...... A+-DXWL... U U U 8 8 4
\r
686 neg 16 . d 0100010001000... .......... U U U 4 4 2
\r
687 neg 16 . . 0100010001...... A+-DXWL... U U U 8 8 4
\r
688 neg 32 . d 0100010010000... .......... U U U 6 6 2
\r
689 neg 32 . . 0100010010...... A+-DXWL... U U U 12 12 4
\r
690 negx 8 . d 0100000000000... .......... U U U 4 4 2
\r
691 negx 8 . . 0100000000...... A+-DXWL... U U U 8 8 4
\r
692 negx 16 . d 0100000001000... .......... U U U 4 4 2
\r
693 negx 16 . . 0100000001...... A+-DXWL... U U U 8 8 4
\r
694 negx 32 . d 0100000010000... .......... U U U 6 6 2
\r
695 negx 32 . . 0100000010...... A+-DXWL... U U U 12 12 4
\r
696 nop 0 . . 0100111001110001 .......... U U U 4 4 2
\r
697 not 8 . d 0100011000000... .......... U U U 4 4 2
\r
698 not 8 . . 0100011000...... A+-DXWL... U U U 8 8 4
\r
699 not 16 . d 0100011001000... .......... U U U 4 4 2
\r
700 not 16 . . 0100011001...... A+-DXWL... U U U 8 8 4
\r
701 not 32 . d 0100011010000... .......... U U U 6 6 2
\r
702 not 32 . . 0100011010...... A+-DXWL... U U U 12 12 4
\r
703 or 8 er d 1000...000000... .......... U U U 4 4 2
\r
704 or 8 er . 1000...000...... A+-DXWLdxI U U U 4 4 2
\r
705 or 16 er d 1000...001000... .......... U U U 4 4 2
\r
706 or 16 er . 1000...001...... A+-DXWLdxI U U U 4 4 2
\r
707 or 32 er d 1000...010000... .......... U U U 6 6 2
\r
708 or 32 er . 1000...010...... A+-DXWLdxI U U U 6 6 2
\r
709 or 8 re . 1000...100...... A+-DXWL... U U U 8 8 4
\r
710 or 16 re . 1000...101...... A+-DXWL... U U U 8 8 4
\r
711 or 32 re . 1000...110...... A+-DXWL... U U U 12 12 4
\r
712 ori 16 toc . 0000000000111100 .......... U U U 20 16 12
\r
713 ori 16 tos . 0000000001111100 .......... S S S 20 16 12
\r
714 ori 8 . d 0000000000000... .......... U U U 8 8 2
\r
715 ori 8 . . 0000000000...... A+-DXWL... U U U 12 12 4
\r
716 ori 16 . d 0000000001000... .......... U U U 8 8 2
\r
717 ori 16 . . 0000000001...... A+-DXWL... U U U 12 12 4
\r
718 ori 32 . d 0000000010000... .......... U U U 16 14 2
\r
719 ori 32 . . 0000000010...... A+-DXWL... U U U 20 20 4
\r
720 pack 16 rr . 1000...101000... .......... . . U . . 6
\r
721 pack 16 mm ax7 1000111101001... .......... . . U . . 13
\r
722 pack 16 mm ay7 1000...101001111 .......... . . U . . 13
\r
723 pack 16 mm axy7 1000111101001111 .......... . . U . . 13
\r
724 pack 16 mm . 1000...101001... .......... . . U . . 13
\r
725 pea 32 . . 0100100001...... A..DXWLdx. U U U 6 6 5
\r
726 reset 0 . . 0100111001110000 .......... S S S 0 0 0
\r
727 ror 8 s . 1110...000011... .......... U U U 6 6 8
\r
728 ror 16 s . 1110...001011... .......... U U U 6 6 8
\r
729 ror 32 s . 1110...010011... .......... U U U 8 8 8
\r
730 ror 8 r . 1110...000111... .......... U U U 6 6 8
\r
731 ror 16 r . 1110...001111... .......... U U U 6 6 8
\r
732 ror 32 r . 1110...010111... .......... U U U 8 8 8
\r
733 ror 16 . . 1110011011...... A+-DXWL... U U U 8 8 7
\r
734 rol 8 s . 1110...100011... .......... U U U 6 6 8
\r
735 rol 16 s . 1110...101011... .......... U U U 6 6 8
\r
736 rol 32 s . 1110...110011... .......... U U U 8 8 8
\r
737 rol 8 r . 1110...100111... .......... U U U 6 6 8
\r
738 rol 16 r . 1110...101111... .......... U U U 6 6 8
\r
739 rol 32 r . 1110...110111... .......... U U U 8 8 8
\r
740 rol 16 . . 1110011111...... A+-DXWL... U U U 8 8 7
\r
741 roxr 8 s . 1110...000010... .......... U U U 6 6 12
\r
742 roxr 16 s . 1110...001010... .......... U U U 6 6 12
\r
743 roxr 32 s . 1110...010010... .......... U U U 8 8 12
\r
744 roxr 8 r . 1110...000110... .......... U U U 6 6 12
\r
745 roxr 16 r . 1110...001110... .......... U U U 6 6 12
\r
746 roxr 32 r . 1110...010110... .......... U U U 8 8 12
\r
747 roxr 16 . . 1110010011...... A+-DXWL... U U U 8 8 5
\r
748 roxl 8 s . 1110...100010... .......... U U U 6 6 12
\r
749 roxl 16 s . 1110...101010... .......... U U U 6 6 12
\r
750 roxl 32 s . 1110...110010... .......... U U U 8 8 12
\r
751 roxl 8 r . 1110...100110... .......... U U U 6 6 12
\r
752 roxl 16 r . 1110...101110... .......... U U U 6 6 12
\r
753 roxl 32 r . 1110...110110... .......... U U U 8 8 12
\r
754 roxl 16 . . 1110010111...... A+-DXWL... U U U 8 8 5
\r
755 rtd 32 . . 0100111001110100 .......... . U U . 16 10
\r
756 rte 32 . . 0100111001110011 .......... S S S 20 24 20 bus fault not emulated
\r
757 rtm 32 . . 000001101100.... .......... . . U . . 19 not properly emulated
\r
758 rtr 32 . . 0100111001110111 .......... U U U 20 20 14
\r
759 rts 32 . . 0100111001110101 .......... U U U 16 16 10
\r
760 sbcd 8 rr . 1000...100000... .......... U U U 6 6 4
\r
761 sbcd 8 mm ax7 1000111100001... .......... U U U 18 18 16
\r
762 sbcd 8 mm ay7 1000...100001111 .......... U U U 18 18 16
\r
763 sbcd 8 mm axy7 1000111100001111 .......... U U U 18 18 16
\r
764 sbcd 8 mm . 1000...100001... .......... U U U 18 18 16
\r
765 st 8 . d 0101000011000... .......... U U U 6 4 4
\r
766 st 8 . . 0101000011...... A+-DXWL... U U U 8 8 6
\r
767 sf 8 . d 0101000111000... .......... U U U 4 4 4
\r
768 sf 8 . . 0101000111...... A+-DXWL... U U U 8 8 6
\r
769 scc 8 . d 0101....11000... .......... U U U 4 4 4
\r
770 scc 8 . . 0101....11...... A+-DXWL... U U U 8 8 6
\r
771 stop 0 . . 0100111001110010 .......... S S S 4 4 8
\r
772 sub 8 er d 1001...000000... .......... U U U 4 4 2
\r
773 sub 8 er . 1001...000...... A+-DXWLdxI U U U 4 4 2
\r
774 sub 16 er d 1001...001000... .......... U U U 4 4 2
\r
775 sub 16 er a 1001...001001... .......... U U U 4 4 2
\r
776 sub 16 er . 1001...001...... A+-DXWLdxI U U U 4 4 2
\r
777 sub 32 er d 1001...010000... .......... U U U 6 6 2
\r
778 sub 32 er a 1001...010001... .......... U U U 6 6 2
\r
779 sub 32 er . 1001...010...... A+-DXWLdxI U U U 6 6 2
\r
780 sub 8 re . 1001...100...... A+-DXWL... U U U 8 8 4
\r
781 sub 16 re . 1001...101...... A+-DXWL... U U U 8 8 4
\r
782 sub 32 re . 1001...110...... A+-DXWL... U U U 12 12 4
\r
783 suba 16 . d 1001...011000... .......... U U U 8 8 2
\r
784 suba 16 . a 1001...011001... .......... U U U 8 8 2
\r
785 suba 16 . . 1001...011...... A+-DXWLdxI U U U 8 8 2
\r
786 suba 32 . d 1001...111000... .......... U U U 6 6 2
\r
787 suba 32 . a 1001...111001... .......... U U U 6 6 2
\r
788 suba 32 . . 1001...111...... A+-DXWLdxI U U U 6 6 2
\r
789 subi 8 . d 0000010000000... .......... U U U 8 8 2
\r
790 subi 8 . . 0000010000...... A+-DXWL... U U U 12 12 4
\r
791 subi 16 . d 0000010001000... .......... U U U 8 8 2
\r
792 subi 16 . . 0000010001...... A+-DXWL... U U U 12 12 4
\r
793 subi 32 . d 0000010010000... .......... U U U 16 14 2
\r
794 subi 32 . . 0000010010...... A+-DXWL... U U U 20 20 4
\r
795 subq 8 . d 0101...100000... .......... U U U 4 4 2
\r
796 subq 8 . . 0101...100...... A+-DXWL... U U U 8 8 4
\r
797 subq 16 . d 0101...101000... .......... U U U 4 4 2
\r
798 subq 16 . a 0101...101001... .......... U U U 8 4 2
\r
799 subq 16 . . 0101...101...... A+-DXWL... U U U 8 8 4
\r
800 subq 32 . d 0101...110000... .......... U U U 8 8 2
\r
801 subq 32 . a 0101...110001... .......... U U U 8 8 2
\r
802 subq 32 . . 0101...110...... A+-DXWL... U U U 12 12 4
\r
803 subx 8 rr . 1001...100000... .......... U U U 4 4 2
\r
804 subx 16 rr . 1001...101000... .......... U U U 4 4 2
\r
805 subx 32 rr . 1001...110000... .......... U U U 8 6 2
\r
806 subx 8 mm ax7 1001111100001... .......... U U U 18 18 12
\r
807 subx 8 mm ay7 1001...100001111 .......... U U U 18 18 12
\r
808 subx 8 mm axy7 1001111100001111 .......... U U U 18 18 12
\r
809 subx 8 mm . 1001...100001... .......... U U U 18 18 12
\r
810 subx 16 mm . 1001...101001... .......... U U U 18 18 12
\r
811 subx 32 mm . 1001...110001... .......... U U U 30 30 12
\r
812 swap 32 . . 0100100001000... .......... U U U 4 4 4
\r
813 tas 8 . d 0100101011000... .......... U U U 4 4 4
\r
814 tas 8 . . 0100101011...... A+-DXWL... U U U 14 14 12
\r
815 trap 0 . . 010011100100.... .......... U U U 4 4 4
\r
816 trapt 0 . . 0101000011111100 .......... . . U . . 4
\r
817 trapt 16 . . 0101000011111010 .......... . . U . . 6
\r
818 trapt 32 . . 0101000011111011 .......... . . U . . 8
\r
819 trapf 0 . . 0101000111111100 .......... . . U . . 4
\r
820 trapf 16 . . 0101000111111010 .......... . . U . . 6
\r
821 trapf 32 . . 0101000111111011 .......... . . U . . 8
\r
822 trapcc 0 . . 0101....11111100 .......... . . U . . 4
\r
823 trapcc 16 . . 0101....11111010 .......... . . U . . 6
\r
824 trapcc 32 . . 0101....11111011 .......... . . U . . 8
\r
825 trapv 0 . . 0100111001110110 .......... U U U 4 4 4
\r
826 tst 8 . d 0100101000000... .......... U U U 4 4 2
\r
827 tst 8 . . 0100101000...... A+-DXWL... U U U 4 4 2
\r
828 tst 8 . pcdi 0100101000111010 .......... . . U . . 7
\r
829 tst 8 . pcix 0100101000111011 .......... . . U . . 9
\r
830 tst 8 . i 0100101000111100 .......... . . U . . 6
\r
831 tst 16 . d 0100101001000... .......... U U U 4 4 2
\r
832 tst 16 . a 0100101001001... .......... . . U . . 2
\r
833 tst 16 . . 0100101001...... A+-DXWL... U U U 4 4 2
\r
834 tst 16 . pcdi 0100101001111010 .......... . . U . . 7
\r
835 tst 16 . pcix 0100101001111011 .......... . . U . . 9
\r
836 tst 16 . i 0100101001111100 .......... . . U . . 6
\r
837 tst 32 . d 0100101010000... .......... U U U 4 4 2
\r
838 tst 32 . a 0100101010001... .......... . . U . . 2
\r
839 tst 32 . . 0100101010...... A+-DXWL... U U U 4 4 2
\r
840 tst 32 . pcdi 0100101010111010 .......... . . U . . 7
\r
841 tst 32 . pcix 0100101010111011 .......... . . U . . 9
\r
842 tst 32 . i 0100101010111100 .......... . . U . . 6
\r
843 unlk 32 . a7 0100111001011111 .......... U U U 12 12 6
\r
844 unlk 32 . . 0100111001011... .......... U U U 12 12 6
\r
845 unpk 16 rr . 1000...110000... .......... . . U . . 8
\r
846 unpk 16 mm ax7 1000111110001... .......... . . U . . 13
\r
847 unpk 16 mm ay7 1000...110001111 .......... . . U . . 13
\r
848 unpk 16 mm axy7 1000111110001111 .......... . . U . . 13
\r
849 unpk 16 mm . 1000...110001... .......... . . U . . 13
\r
853 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
854 M68KMAKE_OPCODE_HANDLER_BODY
\r
856 M68KMAKE_OP(1010, 0, ., .)
\r
858 m68ki_exception_1010();
\r
862 M68KMAKE_OP(1111, 0, ., .)
\r
864 m68ki_exception_1111();
\r
868 M68KMAKE_OP(abcd, 8, rr, .)
\r
873 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
877 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
878 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
882 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
884 res = MASK_OUT_ABOVE_8(res);
\r
887 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
891 M68KMAKE_OP(abcd, 8, mm, ax7)
\r
893 uint src = OPER_AY_PD_8();
\r
894 uint ea = EA_A7_PD_8();
\r
895 uint dst = m68ki_read_8(ea);
\r
896 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
900 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
901 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
905 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
907 res = MASK_OUT_ABOVE_8(res);
\r
910 m68ki_write_8(ea, res);
\r
914 M68KMAKE_OP(abcd, 8, mm, ay7)
\r
916 uint src = OPER_A7_PD_8();
\r
917 uint ea = EA_AX_PD_8();
\r
918 uint dst = m68ki_read_8(ea);
\r
919 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
923 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
924 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
928 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
930 res = MASK_OUT_ABOVE_8(res);
\r
933 m68ki_write_8(ea, res);
\r
937 M68KMAKE_OP(abcd, 8, mm, axy7)
\r
939 uint src = OPER_A7_PD_8();
\r
940 uint ea = EA_A7_PD_8();
\r
941 uint dst = m68ki_read_8(ea);
\r
942 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
946 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
947 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
951 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
953 res = MASK_OUT_ABOVE_8(res);
\r
956 m68ki_write_8(ea, res);
\r
960 M68KMAKE_OP(abcd, 8, mm, .)
\r
962 uint src = OPER_AY_PD_8();
\r
963 uint ea = EA_AX_PD_8();
\r
964 uint dst = m68ki_read_8(ea);
\r
965 uint res = LOW_NIBBLE(src) + LOW_NIBBLE(dst) + XFLAG_AS_1();
\r
969 res += HIGH_NIBBLE(src) + HIGH_NIBBLE(dst);
\r
970 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
974 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
976 res = MASK_OUT_ABOVE_8(res);
\r
979 m68ki_write_8(ea, res);
\r
983 M68KMAKE_OP(add, 8, er, d)
\r
986 uint src = MASK_OUT_ABOVE_8(DY);
\r
987 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
988 uint res = src + dst;
\r
990 FLAG_N = NFLAG_8(res);
\r
991 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
992 FLAG_X = FLAG_C = CFLAG_8(res);
\r
993 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
995 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
999 M68KMAKE_OP(add, 8, er, .)
\r
1001 uint* r_dst = &DX;
\r
1002 uint src = M68KMAKE_GET_OPER_AY_8;
\r
1003 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1004 uint res = src + dst;
\r
1006 FLAG_N = NFLAG_8(res);
\r
1007 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1008 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1009 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1011 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1015 M68KMAKE_OP(add, 16, er, d)
\r
1017 uint* r_dst = &DX;
\r
1018 uint src = MASK_OUT_ABOVE_16(DY);
\r
1019 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1020 uint res = src + dst;
\r
1022 FLAG_N = NFLAG_16(res);
\r
1023 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1024 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1025 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1027 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1031 M68KMAKE_OP(add, 16, er, a)
\r
1033 uint* r_dst = &DX;
\r
1034 uint src = MASK_OUT_ABOVE_16(AY);
\r
1035 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1036 uint res = src + dst;
\r
1038 FLAG_N = NFLAG_16(res);
\r
1039 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1040 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1041 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1043 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1047 M68KMAKE_OP(add, 16, er, .)
\r
1049 uint* r_dst = &DX;
\r
1050 uint src = M68KMAKE_GET_OPER_AY_16;
\r
1051 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1052 uint res = src + dst;
\r
1054 FLAG_N = NFLAG_16(res);
\r
1055 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1056 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1057 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1059 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1063 M68KMAKE_OP(add, 32, er, d)
\r
1065 uint* r_dst = &DX;
\r
1067 uint dst = *r_dst;
\r
1068 uint res = src + dst;
\r
1070 FLAG_N = NFLAG_32(res);
\r
1071 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1072 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1073 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1079 M68KMAKE_OP(add, 32, er, a)
\r
1081 uint* r_dst = &DX;
\r
1083 uint dst = *r_dst;
\r
1084 uint res = src + dst;
\r
1086 FLAG_N = NFLAG_32(res);
\r
1087 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1088 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1089 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1095 M68KMAKE_OP(add, 32, er, .)
\r
1097 uint* r_dst = &DX;
\r
1098 uint src = M68KMAKE_GET_OPER_AY_32;
\r
1099 uint dst = *r_dst;
\r
1100 uint res = src + dst;
\r
1102 FLAG_N = NFLAG_32(res);
\r
1103 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1104 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1105 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1111 M68KMAKE_OP(add, 8, re, .)
\r
1113 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1114 uint src = MASK_OUT_ABOVE_8(DX);
\r
1115 uint dst = m68ki_read_8(ea);
\r
1116 uint res = src + dst;
\r
1118 FLAG_N = NFLAG_8(res);
\r
1119 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1120 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1121 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1123 m68ki_write_8(ea, FLAG_Z);
\r
1127 M68KMAKE_OP(add, 16, re, .)
\r
1129 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1130 uint src = MASK_OUT_ABOVE_16(DX);
\r
1131 uint dst = m68ki_read_16(ea);
\r
1132 uint res = src + dst;
\r
1134 FLAG_N = NFLAG_16(res);
\r
1135 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1136 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1137 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1139 m68ki_write_16(ea, FLAG_Z);
\r
1143 M68KMAKE_OP(add, 32, re, .)
\r
1145 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1147 uint dst = m68ki_read_32(ea);
\r
1148 uint res = src + dst;
\r
1150 FLAG_N = NFLAG_32(res);
\r
1151 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1152 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1153 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1155 m68ki_write_32(ea, FLAG_Z);
\r
1159 M68KMAKE_OP(adda, 16, ., d)
\r
1161 uint* r_dst = &AX;
\r
1163 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(DY));
\r
1167 M68KMAKE_OP(adda, 16, ., a)
\r
1169 uint* r_dst = &AX;
\r
1171 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(AY));
\r
1175 M68KMAKE_OP(adda, 16, ., .)
\r
1177 uint* r_dst = &AX;
\r
1179 *r_dst = MASK_OUT_ABOVE_32(*r_dst + MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));
\r
1183 M68KMAKE_OP(adda, 32, ., d)
\r
1185 uint* r_dst = &AX;
\r
1187 *r_dst = MASK_OUT_ABOVE_32(*r_dst + DY);
\r
1191 M68KMAKE_OP(adda, 32, ., a)
\r
1193 uint* r_dst = &AX;
\r
1195 *r_dst = MASK_OUT_ABOVE_32(*r_dst + AY);
\r
1199 M68KMAKE_OP(adda, 32, ., .)
\r
1201 uint* r_dst = &AX;
\r
1203 *r_dst = MASK_OUT_ABOVE_32(*r_dst + M68KMAKE_GET_OPER_AY_32);
\r
1207 M68KMAKE_OP(addi, 8, ., d)
\r
1209 uint* r_dst = &DY;
\r
1210 uint src = OPER_I_8();
\r
1211 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1212 uint res = src + dst;
\r
1214 FLAG_N = NFLAG_8(res);
\r
1215 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1216 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1217 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1219 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1223 M68KMAKE_OP(addi, 8, ., .)
\r
1225 uint src = OPER_I_8();
\r
1226 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1227 uint dst = m68ki_read_8(ea);
\r
1228 uint res = src + dst;
\r
1230 FLAG_N = NFLAG_8(res);
\r
1231 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1232 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1233 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1235 m68ki_write_8(ea, FLAG_Z);
\r
1239 M68KMAKE_OP(addi, 16, ., d)
\r
1241 uint* r_dst = &DY;
\r
1242 uint src = OPER_I_16();
\r
1243 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1244 uint res = src + dst;
\r
1246 FLAG_N = NFLAG_16(res);
\r
1247 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1248 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1249 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1251 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1255 M68KMAKE_OP(addi, 16, ., .)
\r
1257 uint src = OPER_I_16();
\r
1258 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1259 uint dst = m68ki_read_16(ea);
\r
1260 uint res = src + dst;
\r
1262 FLAG_N = NFLAG_16(res);
\r
1263 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1264 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1265 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1267 m68ki_write_16(ea, FLAG_Z);
\r
1271 M68KMAKE_OP(addi, 32, ., d)
\r
1273 uint* r_dst = &DY;
\r
1274 uint src = OPER_I_32();
\r
1275 uint dst = *r_dst;
\r
1276 uint res = src + dst;
\r
1278 FLAG_N = NFLAG_32(res);
\r
1279 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1280 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1281 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1287 M68KMAKE_OP(addi, 32, ., .)
\r
1289 uint src = OPER_I_32();
\r
1290 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1291 uint dst = m68ki_read_32(ea);
\r
1292 uint res = src + dst;
\r
1294 FLAG_N = NFLAG_32(res);
\r
1295 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1296 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1297 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1299 m68ki_write_32(ea, FLAG_Z);
\r
1303 M68KMAKE_OP(addq, 8, ., d)
\r
1305 uint* r_dst = &DY;
\r
1306 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1307 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1308 uint res = src + dst;
\r
1310 FLAG_N = NFLAG_8(res);
\r
1311 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1312 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1313 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1315 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
1319 M68KMAKE_OP(addq, 8, ., .)
\r
1321 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1322 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1323 uint dst = m68ki_read_8(ea);
\r
1324 uint res = src + dst;
\r
1326 FLAG_N = NFLAG_8(res);
\r
1327 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1328 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1329 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1331 m68ki_write_8(ea, FLAG_Z);
\r
1335 M68KMAKE_OP(addq, 16, ., d)
\r
1337 uint* r_dst = &DY;
\r
1338 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1339 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1340 uint res = src + dst;
\r
1342 FLAG_N = NFLAG_16(res);
\r
1343 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1344 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1345 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1347 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
1351 M68KMAKE_OP(addq, 16, ., a)
\r
1353 uint* r_dst = &AY;
\r
1355 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1359 M68KMAKE_OP(addq, 16, ., .)
\r
1361 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1362 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1363 uint dst = m68ki_read_16(ea);
\r
1364 uint res = src + dst;
\r
1366 FLAG_N = NFLAG_16(res);
\r
1367 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1368 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1369 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1371 m68ki_write_16(ea, FLAG_Z);
\r
1375 M68KMAKE_OP(addq, 32, ., d)
\r
1377 uint* r_dst = &DY;
\r
1378 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1379 uint dst = *r_dst;
\r
1380 uint res = src + dst;
\r
1382 FLAG_N = NFLAG_32(res);
\r
1383 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1384 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1385 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1391 M68KMAKE_OP(addq, 32, ., a)
\r
1393 uint* r_dst = &AY;
\r
1395 *r_dst = MASK_OUT_ABOVE_32(*r_dst + (((REG_IR >> 9) - 1) & 7) + 1);
\r
1399 M68KMAKE_OP(addq, 32, ., .)
\r
1401 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1402 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1403 uint dst = m68ki_read_32(ea);
\r
1404 uint res = src + dst;
\r
1407 FLAG_N = NFLAG_32(res);
\r
1408 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1409 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1410 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
1412 m68ki_write_32(ea, FLAG_Z);
\r
1416 M68KMAKE_OP(addx, 8, rr, .)
\r
1418 uint* r_dst = &DX;
\r
1419 uint src = MASK_OUT_ABOVE_8(DY);
\r
1420 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
1421 uint res = src + dst + XFLAG_AS_1();
\r
1423 FLAG_N = NFLAG_8(res);
\r
1424 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1425 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1427 res = MASK_OUT_ABOVE_8(res);
\r
1430 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1434 M68KMAKE_OP(addx, 16, rr, .)
\r
1436 uint* r_dst = &DX;
\r
1437 uint src = MASK_OUT_ABOVE_16(DY);
\r
1438 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
1439 uint res = src + dst + XFLAG_AS_1();
\r
1441 FLAG_N = NFLAG_16(res);
\r
1442 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1443 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1445 res = MASK_OUT_ABOVE_16(res);
\r
1448 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1452 M68KMAKE_OP(addx, 32, rr, .)
\r
1454 uint* r_dst = &DX;
\r
1456 uint dst = *r_dst;
\r
1457 uint res = src + dst + XFLAG_AS_1();
\r
1459 FLAG_N = NFLAG_32(res);
\r
1460 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1461 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1463 res = MASK_OUT_ABOVE_32(res);
\r
1470 M68KMAKE_OP(addx, 8, mm, ax7)
\r
1472 uint src = OPER_AY_PD_8();
\r
1473 uint ea = EA_A7_PD_8();
\r
1474 uint dst = m68ki_read_8(ea);
\r
1475 uint res = src + dst + XFLAG_AS_1();
\r
1477 FLAG_N = NFLAG_8(res);
\r
1478 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1479 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1481 res = MASK_OUT_ABOVE_8(res);
\r
1484 m68ki_write_8(ea, res);
\r
1488 M68KMAKE_OP(addx, 8, mm, ay7)
\r
1490 uint src = OPER_A7_PD_8();
\r
1491 uint ea = EA_AX_PD_8();
\r
1492 uint dst = m68ki_read_8(ea);
\r
1493 uint res = src + dst + XFLAG_AS_1();
\r
1495 FLAG_N = NFLAG_8(res);
\r
1496 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1497 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1499 res = MASK_OUT_ABOVE_8(res);
\r
1502 m68ki_write_8(ea, res);
\r
1506 M68KMAKE_OP(addx, 8, mm, axy7)
\r
1508 uint src = OPER_A7_PD_8();
\r
1509 uint ea = EA_A7_PD_8();
\r
1510 uint dst = m68ki_read_8(ea);
\r
1511 uint res = src + dst + XFLAG_AS_1();
\r
1513 FLAG_N = NFLAG_8(res);
\r
1514 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1515 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1517 res = MASK_OUT_ABOVE_8(res);
\r
1520 m68ki_write_8(ea, res);
\r
1524 M68KMAKE_OP(addx, 8, mm, .)
\r
1526 uint src = OPER_AY_PD_8();
\r
1527 uint ea = EA_AX_PD_8();
\r
1528 uint dst = m68ki_read_8(ea);
\r
1529 uint res = src + dst + XFLAG_AS_1();
\r
1531 FLAG_N = NFLAG_8(res);
\r
1532 FLAG_V = VFLAG_ADD_8(src, dst, res);
\r
1533 FLAG_X = FLAG_C = CFLAG_8(res);
\r
1535 res = MASK_OUT_ABOVE_8(res);
\r
1538 m68ki_write_8(ea, res);
\r
1542 M68KMAKE_OP(addx, 16, mm, .)
\r
1544 uint src = OPER_AY_PD_16();
\r
1545 uint ea = EA_AX_PD_16();
\r
1546 uint dst = m68ki_read_16(ea);
\r
1547 uint res = src + dst + XFLAG_AS_1();
\r
1549 FLAG_N = NFLAG_16(res);
\r
1550 FLAG_V = VFLAG_ADD_16(src, dst, res);
\r
1551 FLAG_X = FLAG_C = CFLAG_16(res);
\r
1553 res = MASK_OUT_ABOVE_16(res);
\r
1556 m68ki_write_16(ea, res);
\r
1560 M68KMAKE_OP(addx, 32, mm, .)
\r
1562 uint src = OPER_AY_PD_32();
\r
1563 uint ea = EA_AX_PD_32();
\r
1564 uint dst = m68ki_read_32(ea);
\r
1565 uint res = src + dst + XFLAG_AS_1();
\r
1567 FLAG_N = NFLAG_32(res);
\r
1568 FLAG_V = VFLAG_ADD_32(src, dst, res);
\r
1569 FLAG_X = FLAG_C = CFLAG_ADD_32(src, dst, res);
\r
1571 res = MASK_OUT_ABOVE_32(res);
\r
1574 m68ki_write_32(ea, res);
\r
1578 M68KMAKE_OP(and, 8, er, d)
\r
1580 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (DY | 0xffffff00));
\r
1582 FLAG_N = NFLAG_8(FLAG_Z);
\r
1583 FLAG_C = CFLAG_CLEAR;
\r
1584 FLAG_V = VFLAG_CLEAR;
\r
1588 M68KMAKE_OP(and, 8, er, .)
\r
1590 FLAG_Z = MASK_OUT_ABOVE_8(DX &= (M68KMAKE_GET_OPER_AY_8 | 0xffffff00));
\r
1592 FLAG_N = NFLAG_8(FLAG_Z);
\r
1593 FLAG_C = CFLAG_CLEAR;
\r
1594 FLAG_V = VFLAG_CLEAR;
\r
1598 M68KMAKE_OP(and, 16, er, d)
\r
1600 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (DY | 0xffff0000));
\r
1602 FLAG_N = NFLAG_16(FLAG_Z);
\r
1603 FLAG_C = CFLAG_CLEAR;
\r
1604 FLAG_V = VFLAG_CLEAR;
\r
1608 M68KMAKE_OP(and, 16, er, .)
\r
1610 FLAG_Z = MASK_OUT_ABOVE_16(DX &= (M68KMAKE_GET_OPER_AY_16 | 0xffff0000));
\r
1612 FLAG_N = NFLAG_16(FLAG_Z);
\r
1613 FLAG_C = CFLAG_CLEAR;
\r
1614 FLAG_V = VFLAG_CLEAR;
\r
1618 M68KMAKE_OP(and, 32, er, d)
\r
1620 FLAG_Z = DX &= DY;
\r
1622 FLAG_N = NFLAG_32(FLAG_Z);
\r
1623 FLAG_C = CFLAG_CLEAR;
\r
1624 FLAG_V = VFLAG_CLEAR;
\r
1628 M68KMAKE_OP(and, 32, er, .)
\r
1630 FLAG_Z = DX &= M68KMAKE_GET_OPER_AY_32;
\r
1632 FLAG_N = NFLAG_32(FLAG_Z);
\r
1633 FLAG_C = CFLAG_CLEAR;
\r
1634 FLAG_V = VFLAG_CLEAR;
\r
1638 M68KMAKE_OP(and, 8, re, .)
\r
1640 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1641 uint res = DX & m68ki_read_8(ea);
\r
1643 FLAG_N = NFLAG_8(res);
\r
1644 FLAG_C = CFLAG_CLEAR;
\r
1645 FLAG_V = VFLAG_CLEAR;
\r
1646 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
1648 m68ki_write_8(ea, FLAG_Z);
\r
1652 M68KMAKE_OP(and, 16, re, .)
\r
1654 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1655 uint res = DX & m68ki_read_16(ea);
\r
1657 FLAG_N = NFLAG_16(res);
\r
1658 FLAG_C = CFLAG_CLEAR;
\r
1659 FLAG_V = VFLAG_CLEAR;
\r
1660 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
1662 m68ki_write_16(ea, FLAG_Z);
\r
1666 M68KMAKE_OP(and, 32, re, .)
\r
1668 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1669 uint res = DX & m68ki_read_32(ea);
\r
1671 FLAG_N = NFLAG_32(res);
\r
1673 FLAG_C = CFLAG_CLEAR;
\r
1674 FLAG_V = VFLAG_CLEAR;
\r
1676 m68ki_write_32(ea, res);
\r
1680 M68KMAKE_OP(andi, 8, ., d)
\r
1682 FLAG_Z = MASK_OUT_ABOVE_8(DY &= (OPER_I_8() | 0xffffff00));
\r
1684 FLAG_N = NFLAG_8(FLAG_Z);
\r
1685 FLAG_C = CFLAG_CLEAR;
\r
1686 FLAG_V = VFLAG_CLEAR;
\r
1690 M68KMAKE_OP(andi, 8, ., .)
\r
1692 uint src = OPER_I_8();
\r
1693 uint ea = M68KMAKE_GET_EA_AY_8;
\r
1694 uint res = src & m68ki_read_8(ea);
\r
1696 FLAG_N = NFLAG_8(res);
\r
1698 FLAG_C = CFLAG_CLEAR;
\r
1699 FLAG_V = VFLAG_CLEAR;
\r
1701 m68ki_write_8(ea, res);
\r
1705 M68KMAKE_OP(andi, 16, ., d)
\r
1707 FLAG_Z = MASK_OUT_ABOVE_16(DY &= (OPER_I_16() | 0xffff0000));
\r
1709 FLAG_N = NFLAG_16(FLAG_Z);
\r
1710 FLAG_C = CFLAG_CLEAR;
\r
1711 FLAG_V = VFLAG_CLEAR;
\r
1715 M68KMAKE_OP(andi, 16, ., .)
\r
1717 uint src = OPER_I_16();
\r
1718 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1719 uint res = src & m68ki_read_16(ea);
\r
1721 FLAG_N = NFLAG_16(res);
\r
1723 FLAG_C = CFLAG_CLEAR;
\r
1724 FLAG_V = VFLAG_CLEAR;
\r
1726 m68ki_write_16(ea, res);
\r
1730 M68KMAKE_OP(andi, 32, ., d)
\r
1732 FLAG_Z = DY &= (OPER_I_32());
\r
1734 FLAG_N = NFLAG_32(FLAG_Z);
\r
1735 FLAG_C = CFLAG_CLEAR;
\r
1736 FLAG_V = VFLAG_CLEAR;
\r
1740 M68KMAKE_OP(andi, 32, ., .)
\r
1742 uint src = OPER_I_32();
\r
1743 uint ea = M68KMAKE_GET_EA_AY_32;
\r
1744 uint res = src & m68ki_read_32(ea);
\r
1746 FLAG_N = NFLAG_32(res);
\r
1748 FLAG_C = CFLAG_CLEAR;
\r
1749 FLAG_V = VFLAG_CLEAR;
\r
1751 m68ki_write_32(ea, res);
\r
1755 M68KMAKE_OP(andi, 16, toc, .)
\r
1757 m68ki_set_ccr(m68ki_get_ccr() & OPER_I_16());
\r
1761 M68KMAKE_OP(andi, 16, tos, .)
\r
1765 uint src = OPER_I_16();
\r
1766 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
1767 m68ki_set_sr(m68ki_get_sr() & src);
\r
1770 m68ki_exception_privilege_violation();
\r
1774 M68KMAKE_OP(asr, 8, s, .)
\r
1776 uint* r_dst = &DY;
\r
1777 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1778 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1779 uint res = src >> shift;
\r
1781 if(GET_MSB_8(src))
\r
1782 res |= m68ki_shift_8_table[shift];
\r
1784 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1786 FLAG_N = NFLAG_8(res);
\r
1788 FLAG_V = VFLAG_CLEAR;
\r
1789 FLAG_X = FLAG_C = src << (9-shift);
\r
1793 M68KMAKE_OP(asr, 16, s, .)
\r
1795 uint* r_dst = &DY;
\r
1796 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1797 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1798 uint res = src >> shift;
\r
1800 if(GET_MSB_16(src))
\r
1801 res |= m68ki_shift_16_table[shift];
\r
1803 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1805 FLAG_N = NFLAG_16(res);
\r
1807 FLAG_V = VFLAG_CLEAR;
\r
1808 FLAG_X = FLAG_C = src << (9-shift);
\r
1812 M68KMAKE_OP(asr, 32, s, .)
\r
1814 uint* r_dst = &DY;
\r
1815 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
1816 uint src = *r_dst;
\r
1817 uint res = src >> shift;
\r
1819 if(GET_MSB_32(src))
\r
1820 res |= m68ki_shift_32_table[shift];
\r
1824 FLAG_N = NFLAG_32(res);
\r
1826 FLAG_V = VFLAG_CLEAR;
\r
1827 FLAG_X = FLAG_C = src << (9-shift);
\r
1831 M68KMAKE_OP(asr, 8, r, .)
\r
1833 uint* r_dst = &DY;
\r
1834 uint shift = DX & 0x3f;
\r
1835 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
1836 uint res = src >> shift;
\r
1840 USE_CYCLES(shift<<CYC_SHIFT);
\r
1844 if(GET_MSB_8(src))
\r
1845 res |= m68ki_shift_8_table[shift];
\r
1847 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
1849 FLAG_X = FLAG_C = src << (9-shift);
\r
1850 FLAG_N = NFLAG_8(res);
\r
1852 FLAG_V = VFLAG_CLEAR;
\r
1856 if(GET_MSB_8(src))
\r
1859 FLAG_C = CFLAG_SET;
\r
1860 FLAG_X = XFLAG_SET;
\r
1861 FLAG_N = NFLAG_SET;
\r
1862 FLAG_Z = ZFLAG_CLEAR;
\r
1863 FLAG_V = VFLAG_CLEAR;
\r
1867 *r_dst &= 0xffffff00;
\r
1868 FLAG_C = CFLAG_CLEAR;
\r
1869 FLAG_X = XFLAG_CLEAR;
\r
1870 FLAG_N = NFLAG_CLEAR;
\r
1871 FLAG_Z = ZFLAG_SET;
\r
1872 FLAG_V = VFLAG_CLEAR;
\r
1876 FLAG_C = CFLAG_CLEAR;
\r
1877 FLAG_N = NFLAG_8(src);
\r
1879 FLAG_V = VFLAG_CLEAR;
\r
1883 M68KMAKE_OP(asr, 16, r, .)
\r
1885 uint* r_dst = &DY;
\r
1886 uint shift = DX & 0x3f;
\r
1887 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
1888 uint res = src >> shift;
\r
1892 USE_CYCLES(shift<<CYC_SHIFT);
\r
1896 if(GET_MSB_16(src))
\r
1897 res |= m68ki_shift_16_table[shift];
\r
1899 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
1901 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
1902 FLAG_N = NFLAG_16(res);
\r
1904 FLAG_V = VFLAG_CLEAR;
\r
1908 if(GET_MSB_16(src))
\r
1911 FLAG_C = CFLAG_SET;
\r
1912 FLAG_X = XFLAG_SET;
\r
1913 FLAG_N = NFLAG_SET;
\r
1914 FLAG_Z = ZFLAG_CLEAR;
\r
1915 FLAG_V = VFLAG_CLEAR;
\r
1919 *r_dst &= 0xffff0000;
\r
1920 FLAG_C = CFLAG_CLEAR;
\r
1921 FLAG_X = XFLAG_CLEAR;
\r
1922 FLAG_N = NFLAG_CLEAR;
\r
1923 FLAG_Z = ZFLAG_SET;
\r
1924 FLAG_V = VFLAG_CLEAR;
\r
1928 FLAG_C = CFLAG_CLEAR;
\r
1929 FLAG_N = NFLAG_16(src);
\r
1931 FLAG_V = VFLAG_CLEAR;
\r
1935 M68KMAKE_OP(asr, 32, r, .)
\r
1937 uint* r_dst = &DY;
\r
1938 uint shift = DX & 0x3f;
\r
1939 uint src = *r_dst;
\r
1940 uint res = src >> shift;
\r
1944 USE_CYCLES(shift<<CYC_SHIFT);
\r
1948 if(GET_MSB_32(src))
\r
1949 res |= m68ki_shift_32_table[shift];
\r
1953 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
1954 FLAG_N = NFLAG_32(res);
\r
1956 FLAG_V = VFLAG_CLEAR;
\r
1960 if(GET_MSB_32(src))
\r
1962 *r_dst = 0xffffffff;
\r
1963 FLAG_C = CFLAG_SET;
\r
1964 FLAG_X = XFLAG_SET;
\r
1965 FLAG_N = NFLAG_SET;
\r
1966 FLAG_Z = ZFLAG_CLEAR;
\r
1967 FLAG_V = VFLAG_CLEAR;
\r
1972 FLAG_C = CFLAG_CLEAR;
\r
1973 FLAG_X = XFLAG_CLEAR;
\r
1974 FLAG_N = NFLAG_CLEAR;
\r
1975 FLAG_Z = ZFLAG_SET;
\r
1976 FLAG_V = VFLAG_CLEAR;
\r
1980 FLAG_C = CFLAG_CLEAR;
\r
1981 FLAG_N = NFLAG_32(src);
\r
1983 FLAG_V = VFLAG_CLEAR;
\r
1987 M68KMAKE_OP(asr, 16, ., .)
\r
1989 uint ea = M68KMAKE_GET_EA_AY_16;
\r
1990 uint src = m68ki_read_16(ea);
\r
1991 uint res = src >> 1;
\r
1993 if(GET_MSB_16(src))
\r
1996 m68ki_write_16(ea, res);
\r
1998 FLAG_N = NFLAG_16(res);
\r
2000 FLAG_V = VFLAG_CLEAR;
\r
2001 FLAG_C = FLAG_X = src << 8;
\r
2005 M68KMAKE_OP(asl, 8, s, .)
\r
2007 uint* r_dst = &DY;
\r
2008 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2009 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2010 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2012 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2014 FLAG_X = FLAG_C = src << shift;
\r
2015 FLAG_N = NFLAG_8(res);
\r
2017 src &= m68ki_shift_8_table[shift + 1];
\r
2018 FLAG_V = (!(src == 0 || (src == m68ki_shift_8_table[shift + 1] && shift < 8)))<<7;
\r
2022 M68KMAKE_OP(asl, 16, s, .)
\r
2024 uint* r_dst = &DY;
\r
2025 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2026 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2027 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2029 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2031 FLAG_N = NFLAG_16(res);
\r
2033 FLAG_X = FLAG_C = src >> (8-shift);
\r
2034 src &= m68ki_shift_16_table[shift + 1];
\r
2035 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2039 M68KMAKE_OP(asl, 32, s, .)
\r
2041 uint* r_dst = &DY;
\r
2042 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
2043 uint src = *r_dst;
\r
2044 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2048 FLAG_N = NFLAG_32(res);
\r
2050 FLAG_X = FLAG_C = src >> (24-shift);
\r
2051 src &= m68ki_shift_32_table[shift + 1];
\r
2052 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2056 M68KMAKE_OP(asl, 8, r, .)
\r
2058 uint* r_dst = &DY;
\r
2059 uint shift = DX & 0x3f;
\r
2060 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
2061 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
2065 USE_CYCLES(shift<<CYC_SHIFT);
\r
2069 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
2070 FLAG_X = FLAG_C = src << shift;
\r
2071 FLAG_N = NFLAG_8(res);
\r
2073 src &= m68ki_shift_8_table[shift + 1];
\r
2074 FLAG_V = (!(src == 0 || src == m68ki_shift_8_table[shift + 1]))<<7;
\r
2078 *r_dst &= 0xffffff00;
\r
2079 FLAG_X = FLAG_C = ((shift == 8 ? src & 1 : 0))<<8;
\r
2080 FLAG_N = NFLAG_CLEAR;
\r
2081 FLAG_Z = ZFLAG_SET;
\r
2082 FLAG_V = (!(src == 0))<<7;
\r
2086 FLAG_C = CFLAG_CLEAR;
\r
2087 FLAG_N = NFLAG_8(src);
\r
2089 FLAG_V = VFLAG_CLEAR;
\r
2093 M68KMAKE_OP(asl, 16, r, .)
\r
2095 uint* r_dst = &DY;
\r
2096 uint shift = DX & 0x3f;
\r
2097 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
2098 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
2102 USE_CYCLES(shift<<CYC_SHIFT);
\r
2106 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
2107 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
2108 FLAG_N = NFLAG_16(res);
\r
2110 src &= m68ki_shift_16_table[shift + 1];
\r
2111 FLAG_V = (!(src == 0 || src == m68ki_shift_16_table[shift + 1]))<<7;
\r
2115 *r_dst &= 0xffff0000;
\r
2116 FLAG_X = FLAG_C = ((shift == 16 ? src & 1 : 0))<<8;
\r
2117 FLAG_N = NFLAG_CLEAR;
\r
2118 FLAG_Z = ZFLAG_SET;
\r
2119 FLAG_V = (!(src == 0))<<7;
\r
2123 FLAG_C = CFLAG_CLEAR;
\r
2124 FLAG_N = NFLAG_16(src);
\r
2126 FLAG_V = VFLAG_CLEAR;
\r
2130 M68KMAKE_OP(asl, 32, r, .)
\r
2132 uint* r_dst = &DY;
\r
2133 uint shift = DX & 0x3f;
\r
2134 uint src = *r_dst;
\r
2135 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
2139 USE_CYCLES(shift<<CYC_SHIFT);
\r
2144 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
2145 FLAG_N = NFLAG_32(res);
\r
2147 src &= m68ki_shift_32_table[shift + 1];
\r
2148 FLAG_V = (!(src == 0 || src == m68ki_shift_32_table[shift + 1]))<<7;
\r
2153 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
2154 FLAG_N = NFLAG_CLEAR;
\r
2155 FLAG_Z = ZFLAG_SET;
\r
2156 FLAG_V = (!(src == 0))<<7;
\r
2160 FLAG_C = CFLAG_CLEAR;
\r
2161 FLAG_N = NFLAG_32(src);
\r
2163 FLAG_V = VFLAG_CLEAR;
\r
2167 M68KMAKE_OP(asl, 16, ., .)
\r
2169 uint ea = M68KMAKE_GET_EA_AY_16;
\r
2170 uint src = m68ki_read_16(ea);
\r
2171 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
2173 m68ki_write_16(ea, res);
\r
2175 FLAG_N = NFLAG_16(res);
\r
2177 FLAG_X = FLAG_C = src >> 7;
\r
2179 FLAG_V = (!(src == 0 || src == 0xc000))<<7;
\r
2183 M68KMAKE_OP(bcc, 8, ., .)
\r
2187 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2188 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
2191 USE_CYCLES(CYC_BCC_NOTAKE_B);
\r
2195 M68KMAKE_OP(bcc, 16, ., .)
\r
2199 uint offset = OPER_I_16();
\r
2201 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2202 m68ki_branch_16(offset);
\r
2206 USE_CYCLES(CYC_BCC_NOTAKE_W);
\r
2210 M68KMAKE_OP(bcc, 32, ., .)
\r
2212 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2216 uint offset = OPER_I_32();
\r
2218 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
2219 m68ki_branch_32(offset);
\r
2225 m68ki_exception_illegal();
\r
2229 M68KMAKE_OP(bchg, 32, r, d)
\r
2231 uint* r_dst = &DY;
\r
2232 uint mask = 1 << (DX & 0x1f);
\r
2234 FLAG_Z = *r_dst & mask;
\r
2239 M68KMAKE_OP(bchg, 8, r, .)
\r
2241 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2242 uint src = m68ki_read_8(ea);
\r
2243 uint mask = 1 << (DX & 7);
\r
2245 FLAG_Z = src & mask;
\r
2246 m68ki_write_8(ea, src ^ mask);
\r
2250 M68KMAKE_OP(bchg, 32, s, d)
\r
2252 uint* r_dst = &DY;
\r
2253 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2255 FLAG_Z = *r_dst & mask;
\r
2260 M68KMAKE_OP(bchg, 8, s, .)
\r
2262 uint mask = 1 << (OPER_I_8() & 7);
\r
2263 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2264 uint src = m68ki_read_8(ea);
\r
2266 FLAG_Z = src & mask;
\r
2267 m68ki_write_8(ea, src ^ mask);
\r
2271 M68KMAKE_OP(bclr, 32, r, d)
\r
2273 uint* r_dst = &DY;
\r
2274 uint mask = 1 << (DX & 0x1f);
\r
2276 FLAG_Z = *r_dst & mask;
\r
2281 M68KMAKE_OP(bclr, 8, r, .)
\r
2283 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2284 uint src = m68ki_read_8(ea);
\r
2285 uint mask = 1 << (DX & 7);
\r
2287 FLAG_Z = src & mask;
\r
2288 m68ki_write_8(ea, src & ~mask);
\r
2292 M68KMAKE_OP(bclr, 32, s, d)
\r
2294 uint* r_dst = &DY;
\r
2295 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
2297 FLAG_Z = *r_dst & mask;
\r
2302 M68KMAKE_OP(bclr, 8, s, .)
\r
2304 uint mask = 1 << (OPER_I_8() & 7);
\r
2305 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2306 uint src = m68ki_read_8(ea);
\r
2308 FLAG_Z = src & mask;
\r
2309 m68ki_write_8(ea, src & ~mask);
\r
2313 M68KMAKE_OP(bfchg, 32, ., d)
\r
2315 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2317 uint word2 = OPER_I_16();
\r
2318 uint offset = (word2>>6)&31;
\r
2319 uint width = word2;
\r
2325 offset = REG_D[offset&7];
\r
2327 width = REG_D[width&7];
\r
2330 width = ((width-1) & 31) + 1;
\r
2332 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2333 mask = ROR_32(mask, offset);
\r
2335 FLAG_N = NFLAG_32(*data<<offset);
\r
2336 FLAG_Z = *data & mask;
\r
2337 FLAG_V = VFLAG_CLEAR;
\r
2338 FLAG_C = CFLAG_CLEAR;
\r
2344 m68ki_exception_illegal();
\r
2348 M68KMAKE_OP(bfchg, 32, ., .)
\r
2350 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2352 uint word2 = OPER_I_16();
\r
2353 sint offset = (word2>>6)&31;
\r
2354 uint width = word2;
\r
2358 uint data_byte = 0;
\r
2359 uint mask_byte = 0;
\r
2360 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2364 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2366 width = REG_D[width&7];
\r
2368 /* Offset is signed so we have to use ugly math =( */
\r
2376 width = ((width-1) & 31) + 1;
\r
2378 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2379 mask_long = mask_base >> offset;
\r
2381 data_long = m68ki_read_32(ea);
\r
2382 FLAG_N = NFLAG_32(data_long << offset);
\r
2383 FLAG_Z = data_long & mask_long;
\r
2384 FLAG_V = VFLAG_CLEAR;
\r
2385 FLAG_C = CFLAG_CLEAR;
\r
2387 m68ki_write_32(ea, data_long ^ mask_long);
\r
2389 if((width + offset) > 32)
\r
2391 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2392 data_byte = m68ki_read_8(ea+4);
\r
2393 FLAG_Z |= (data_byte & mask_byte);
\r
2394 m68ki_write_8(ea+4, data_byte ^ mask_byte);
\r
2398 m68ki_exception_illegal();
\r
2402 M68KMAKE_OP(bfclr, 32, ., d)
\r
2404 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2406 uint word2 = OPER_I_16();
\r
2407 uint offset = (word2>>6)&31;
\r
2408 uint width = word2;
\r
2414 offset = REG_D[offset&7];
\r
2416 width = REG_D[width&7];
\r
2420 width = ((width-1) & 31) + 1;
\r
2423 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2424 mask = ROR_32(mask, offset);
\r
2426 FLAG_N = NFLAG_32(*data<<offset);
\r
2427 FLAG_Z = *data & mask;
\r
2428 FLAG_V = VFLAG_CLEAR;
\r
2429 FLAG_C = CFLAG_CLEAR;
\r
2435 m68ki_exception_illegal();
\r
2439 M68KMAKE_OP(bfclr, 32, ., .)
\r
2441 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2443 uint word2 = OPER_I_16();
\r
2444 sint offset = (word2>>6)&31;
\r
2445 uint width = word2;
\r
2449 uint data_byte = 0;
\r
2450 uint mask_byte = 0;
\r
2451 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2455 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2457 width = REG_D[width&7];
\r
2459 /* Offset is signed so we have to use ugly math =( */
\r
2467 width = ((width-1) & 31) + 1;
\r
2469 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2470 mask_long = mask_base >> offset;
\r
2472 data_long = m68ki_read_32(ea);
\r
2473 FLAG_N = NFLAG_32(data_long << offset);
\r
2474 FLAG_Z = data_long & mask_long;
\r
2475 FLAG_V = VFLAG_CLEAR;
\r
2476 FLAG_C = CFLAG_CLEAR;
\r
2478 m68ki_write_32(ea, data_long & ~mask_long);
\r
2480 if((width + offset) > 32)
\r
2482 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2483 data_byte = m68ki_read_8(ea+4);
\r
2484 FLAG_Z |= (data_byte & mask_byte);
\r
2485 m68ki_write_8(ea+4, data_byte & ~mask_byte);
\r
2489 m68ki_exception_illegal();
\r
2493 M68KMAKE_OP(bfexts, 32, ., d)
\r
2495 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2497 uint word2 = OPER_I_16();
\r
2498 uint offset = (word2>>6)&31;
\r
2499 uint width = word2;
\r
2504 offset = REG_D[offset&7];
\r
2506 width = REG_D[width&7];
\r
2509 width = ((width-1) & 31) + 1;
\r
2511 data = ROL_32(data, offset);
\r
2512 FLAG_N = NFLAG_32(data);
\r
2513 data = MAKE_INT_32(data) >> (32 - width);
\r
2516 FLAG_V = VFLAG_CLEAR;
\r
2517 FLAG_C = CFLAG_CLEAR;
\r
2519 REG_D[(word2>>12)&7] = data;
\r
2523 m68ki_exception_illegal();
\r
2527 M68KMAKE_OP(bfexts, 32, ., .)
\r
2529 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2531 uint word2 = OPER_I_16();
\r
2532 sint offset = (word2>>6)&31;
\r
2533 uint width = word2;
\r
2535 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2539 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2541 width = REG_D[width&7];
\r
2543 /* Offset is signed so we have to use ugly math =( */
\r
2551 width = ((width-1) & 31) + 1;
\r
2553 data = m68ki_read_32(ea);
\r
2555 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2557 if((offset+width) > 32)
\r
2558 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2560 FLAG_N = NFLAG_32(data);
\r
2561 data = MAKE_INT_32(data) >> (32 - width);
\r
2564 FLAG_V = VFLAG_CLEAR;
\r
2565 FLAG_C = CFLAG_CLEAR;
\r
2567 REG_D[(word2 >> 12) & 7] = data;
\r
2571 m68ki_exception_illegal();
\r
2575 M68KMAKE_OP(bfextu, 32, ., d)
\r
2577 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2579 uint word2 = OPER_I_16();
\r
2580 uint offset = (word2>>6)&31;
\r
2581 uint width = word2;
\r
2586 offset = REG_D[offset&7];
\r
2588 width = REG_D[width&7];
\r
2591 width = ((width-1) & 31) + 1;
\r
2593 data = ROL_32(data, offset);
\r
2594 FLAG_N = NFLAG_32(data);
\r
2595 data >>= 32 - width;
\r
2598 FLAG_V = VFLAG_CLEAR;
\r
2599 FLAG_C = CFLAG_CLEAR;
\r
2601 REG_D[(word2>>12)&7] = data;
\r
2605 m68ki_exception_illegal();
\r
2609 M68KMAKE_OP(bfextu, 32, ., .)
\r
2611 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2613 uint word2 = OPER_I_16();
\r
2614 sint offset = (word2>>6)&31;
\r
2615 uint width = word2;
\r
2617 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2621 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2623 width = REG_D[width&7];
\r
2625 /* Offset is signed so we have to use ugly math =( */
\r
2633 width = ((width-1) & 31) + 1;
\r
2635 data = m68ki_read_32(ea);
\r
2636 data = MASK_OUT_ABOVE_32(data<<offset);
\r
2638 if((offset+width) > 32)
\r
2639 data |= (m68ki_read_8(ea+4) << offset) >> 8;
\r
2641 FLAG_N = NFLAG_32(data);
\r
2642 data >>= (32 - width);
\r
2645 FLAG_V = VFLAG_CLEAR;
\r
2646 FLAG_C = CFLAG_CLEAR;
\r
2648 REG_D[(word2 >> 12) & 7] = data;
\r
2652 m68ki_exception_illegal();
\r
2656 M68KMAKE_OP(bfffo, 32, ., d)
\r
2658 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2660 uint word2 = OPER_I_16();
\r
2661 uint offset = (word2>>6)&31;
\r
2662 uint width = word2;
\r
2668 offset = REG_D[offset&7];
\r
2670 width = REG_D[width&7];
\r
2673 width = ((width-1) & 31) + 1;
\r
2675 data = ROL_32(data, offset);
\r
2676 FLAG_N = NFLAG_32(data);
\r
2677 data >>= 32 - width;
\r
2680 FLAG_V = VFLAG_CLEAR;
\r
2681 FLAG_C = CFLAG_CLEAR;
\r
2683 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2686 REG_D[(word2>>12)&7] = offset;
\r
2690 m68ki_exception_illegal();
\r
2694 M68KMAKE_OP(bfffo, 32, ., .)
\r
2696 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2698 uint word2 = OPER_I_16();
\r
2699 sint offset = (word2>>6)&31;
\r
2700 sint local_offset;
\r
2701 uint width = word2;
\r
2704 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2708 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2710 width = REG_D[width&7];
\r
2712 /* Offset is signed so we have to use ugly math =( */
\r
2714 local_offset = offset % 8;
\r
2715 if(local_offset < 0)
\r
2717 local_offset += 8;
\r
2720 width = ((width-1) & 31) + 1;
\r
2722 data = m68ki_read_32(ea);
\r
2723 data = MASK_OUT_ABOVE_32(data<<local_offset);
\r
2725 if((local_offset+width) > 32)
\r
2726 data |= (m68ki_read_8(ea+4) << local_offset) >> 8;
\r
2728 FLAG_N = NFLAG_32(data);
\r
2729 data >>= (32 - width);
\r
2732 FLAG_V = VFLAG_CLEAR;
\r
2733 FLAG_C = CFLAG_CLEAR;
\r
2735 for(bit = 1<<(width-1);bit && !(data & bit);bit>>= 1)
\r
2738 REG_D[(word2>>12)&7] = offset;
\r
2742 m68ki_exception_illegal();
\r
2746 M68KMAKE_OP(bfins, 32, ., d)
\r
2748 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2750 uint word2 = OPER_I_16();
\r
2751 uint offset = (word2>>6)&31;
\r
2752 uint width = word2;
\r
2755 uint64 insert = REG_D[(word2>>12)&7];
\r
2759 offset = REG_D[offset&7];
\r
2761 width = REG_D[width&7];
\r
2765 width = ((width-1) & 31) + 1;
\r
2768 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2769 mask = ROR_32(mask, offset);
\r
2771 insert = MASK_OUT_ABOVE_32(insert << (32 - width));
\r
2772 FLAG_N = NFLAG_32(insert);
\r
2774 insert = ROR_32(insert, offset);
\r
2776 FLAG_V = VFLAG_CLEAR;
\r
2777 FLAG_C = CFLAG_CLEAR;
\r
2784 m68ki_exception_illegal();
\r
2788 M68KMAKE_OP(bfins, 32, ., .)
\r
2790 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2792 uint word2 = OPER_I_16();
\r
2793 sint offset = (word2>>6)&31;
\r
2794 uint width = word2;
\r
2795 uint insert_base = REG_D[(word2>>12)&7];
\r
2801 uint data_byte = 0;
\r
2802 uint mask_byte = 0;
\r
2803 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2807 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2809 width = REG_D[width&7];
\r
2811 /* Offset is signed so we have to use ugly math =( */
\r
2819 width = ((width-1) & 31) + 1;
\r
2821 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2822 mask_long = mask_base >> offset;
\r
2824 insert_base = MASK_OUT_ABOVE_32(insert_base << (32 - width));
\r
2825 FLAG_N = NFLAG_32(insert_base);
\r
2826 FLAG_Z = insert_base;
\r
2827 insert_long = insert_base >> offset;
\r
2829 data_long = m68ki_read_32(ea);
\r
2830 FLAG_V = VFLAG_CLEAR;
\r
2831 FLAG_C = CFLAG_CLEAR;
\r
2833 m68ki_write_32(ea, (data_long & ~mask_long) | insert_long);
\r
2835 if((width + offset) > 32)
\r
2837 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2838 insert_byte = MASK_OUT_ABOVE_8(insert_base);
\r
2839 data_byte = m68ki_read_8(ea+4);
\r
2840 FLAG_Z |= (data_byte & mask_byte);
\r
2841 m68ki_write_8(ea+4, (data_byte & ~mask_byte) | insert_byte);
\r
2845 m68ki_exception_illegal();
\r
2849 M68KMAKE_OP(bfset, 32, ., d)
\r
2851 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2853 uint word2 = OPER_I_16();
\r
2854 uint offset = (word2>>6)&31;
\r
2855 uint width = word2;
\r
2861 offset = REG_D[offset&7];
\r
2863 width = REG_D[width&7];
\r
2867 width = ((width-1) & 31) + 1;
\r
2870 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2871 mask = ROR_32(mask, offset);
\r
2873 FLAG_N = NFLAG_32(*data<<offset);
\r
2874 FLAG_Z = *data & mask;
\r
2875 FLAG_V = VFLAG_CLEAR;
\r
2876 FLAG_C = CFLAG_CLEAR;
\r
2882 m68ki_exception_illegal();
\r
2886 M68KMAKE_OP(bfset, 32, ., .)
\r
2888 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2890 uint word2 = OPER_I_16();
\r
2891 sint offset = (word2>>6)&31;
\r
2892 uint width = word2;
\r
2896 uint data_byte = 0;
\r
2897 uint mask_byte = 0;
\r
2898 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2902 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2904 width = REG_D[width&7];
\r
2906 /* Offset is signed so we have to use ugly math =( */
\r
2914 width = ((width-1) & 31) + 1;
\r
2917 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2918 mask_long = mask_base >> offset;
\r
2920 data_long = m68ki_read_32(ea);
\r
2921 FLAG_N = NFLAG_32(data_long << offset);
\r
2922 FLAG_Z = data_long & mask_long;
\r
2923 FLAG_V = VFLAG_CLEAR;
\r
2924 FLAG_C = CFLAG_CLEAR;
\r
2926 m68ki_write_32(ea, data_long | mask_long);
\r
2928 if((width + offset) > 32)
\r
2930 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
2931 data_byte = m68ki_read_8(ea+4);
\r
2932 FLAG_Z |= (data_byte & mask_byte);
\r
2933 m68ki_write_8(ea+4, data_byte | mask_byte);
\r
2937 m68ki_exception_illegal();
\r
2941 M68KMAKE_OP(bftst, 32, ., d)
\r
2943 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2945 uint word2 = OPER_I_16();
\r
2946 uint offset = (word2>>6)&31;
\r
2947 uint width = word2;
\r
2953 offset = REG_D[offset&7];
\r
2955 width = REG_D[width&7];
\r
2959 width = ((width-1) & 31) + 1;
\r
2962 mask = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
2963 mask = ROR_32(mask, offset);
\r
2965 FLAG_N = NFLAG_32(*data<<offset);
\r
2966 FLAG_Z = *data & mask;
\r
2967 FLAG_V = VFLAG_CLEAR;
\r
2968 FLAG_C = CFLAG_CLEAR;
\r
2972 m68ki_exception_illegal();
\r
2976 M68KMAKE_OP(bftst, 32, ., .)
\r
2978 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
2980 uint word2 = OPER_I_16();
\r
2981 sint offset = (word2>>6)&31;
\r
2982 uint width = word2;
\r
2986 uint data_byte = 0;
\r
2987 uint mask_byte = 0;
\r
2988 uint ea = M68KMAKE_GET_EA_AY_8;
\r
2991 offset = MAKE_INT_32(REG_D[offset&7]);
\r
2993 width = REG_D[width&7];
\r
2995 /* Offset is signed so we have to use ugly math =( */
\r
3003 width = ((width-1) & 31) + 1;
\r
3006 mask_base = MASK_OUT_ABOVE_32(0xffffffff << (32 - width));
\r
3007 mask_long = mask_base >> offset;
\r
3009 data_long = m68ki_read_32(ea);
\r
3010 FLAG_N = ((data_long & (0x80000000 >> offset))<<offset)>>24;
\r
3011 FLAG_Z = data_long & mask_long;
\r
3012 FLAG_V = VFLAG_CLEAR;
\r
3013 FLAG_C = CFLAG_CLEAR;
\r
3015 if((width + offset) > 32)
\r
3017 mask_byte = MASK_OUT_ABOVE_8(mask_base);
\r
3018 data_byte = m68ki_read_8(ea+4);
\r
3019 FLAG_Z |= (data_byte & mask_byte);
\r
3023 m68ki_exception_illegal();
\r
3027 M68KMAKE_OP(bkpt, 0, ., .)
\r
3029 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
3031 m68ki_bkpt_ack(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE) ? REG_IR & 7 : 0); /* auto-disable (see m68kcpu.h) */
\r
3033 m68ki_exception_illegal();
\r
3037 M68KMAKE_OP(bra, 8, ., .)
\r
3039 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3040 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3041 if(REG_PC == REG_PPC)
\r
3046 M68KMAKE_OP(bra, 16, ., .)
\r
3048 uint offset = OPER_I_16();
\r
3050 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3051 m68ki_branch_16(offset);
\r
3052 if(REG_PC == REG_PPC)
\r
3057 M68KMAKE_OP(bra, 32, ., .)
\r
3059 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3061 uint offset = OPER_I_32();
\r
3063 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3064 m68ki_branch_32(offset);
\r
3065 if(REG_PC == REG_PPC)
\r
3069 m68ki_exception_illegal();
\r
3073 M68KMAKE_OP(bset, 32, r, d)
\r
3075 uint* r_dst = &DY;
\r
3076 uint mask = 1 << (DX & 0x1f);
\r
3078 FLAG_Z = *r_dst & mask;
\r
3083 M68KMAKE_OP(bset, 8, r, .)
\r
3085 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3086 uint src = m68ki_read_8(ea);
\r
3087 uint mask = 1 << (DX & 7);
\r
3089 FLAG_Z = src & mask;
\r
3090 m68ki_write_8(ea, src | mask);
\r
3094 M68KMAKE_OP(bset, 32, s, d)
\r
3096 uint* r_dst = &DY;
\r
3097 uint mask = 1 << (OPER_I_8() & 0x1f);
\r
3099 FLAG_Z = *r_dst & mask;
\r
3104 M68KMAKE_OP(bset, 8, s, .)
\r
3106 uint mask = 1 << (OPER_I_8() & 7);
\r
3107 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3108 uint src = m68ki_read_8(ea);
\r
3110 FLAG_Z = src & mask;
\r
3111 m68ki_write_8(ea, src | mask);
\r
3115 M68KMAKE_OP(bsr, 8, ., .)
\r
3117 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3118 m68ki_push_32(REG_PC);
\r
3119 m68ki_branch_8(MASK_OUT_ABOVE_8(REG_IR));
\r
3123 M68KMAKE_OP(bsr, 16, ., .)
\r
3125 uint offset = OPER_I_16();
\r
3126 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3127 m68ki_push_32(REG_PC);
\r
3129 m68ki_branch_16(offset);
\r
3133 M68KMAKE_OP(bsr, 32, ., .)
\r
3135 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3137 uint offset = OPER_I_32();
\r
3138 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3139 m68ki_push_32(REG_PC);
\r
3141 m68ki_branch_32(offset);
\r
3144 m68ki_exception_illegal();
\r
3148 M68KMAKE_OP(btst, 32, r, d)
\r
3150 FLAG_Z = DY & (1 << (DX & 0x1f));
\r
3154 M68KMAKE_OP(btst, 8, r, .)
\r
3156 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << (DX & 7));
\r
3160 M68KMAKE_OP(btst, 32, s, d)
\r
3162 FLAG_Z = DY & (1 << (OPER_I_8() & 0x1f));
\r
3166 M68KMAKE_OP(btst, 8, s, .)
\r
3168 uint bit = OPER_I_8() & 7;
\r
3170 FLAG_Z = M68KMAKE_GET_OPER_AY_8 & (1 << bit);
\r
3174 M68KMAKE_OP(callm, 32, ., .)
\r
3176 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
3178 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3180 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3182 (void)ea; /* just to avoid an 'unused variable' warning */
\r
3183 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
3184 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
3185 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
3188 m68ki_exception_illegal();
\r
3192 M68KMAKE_OP(cas, 8, ., .)
\r
3194 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3196 uint word2 = OPER_I_16();
\r
3197 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3198 uint dest = m68ki_read_8(ea);
\r
3199 uint* compare = ®_D[word2 & 7];
\r
3200 uint res = dest - MASK_OUT_ABOVE_8(*compare);
\r
3202 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3203 FLAG_N = NFLAG_8(res);
\r
3204 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3205 FLAG_V = VFLAG_SUB_8(*compare, dest, res);
\r
3206 FLAG_C = CFLAG_8(res);
\r
3209 *compare = MASK_OUT_BELOW_8(*compare) | dest;
\r
3213 m68ki_write_8(ea, MASK_OUT_ABOVE_8(REG_D[(word2 >> 6) & 7]));
\r
3217 m68ki_exception_illegal();
\r
3221 M68KMAKE_OP(cas, 16, ., .)
\r
3223 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3225 uint word2 = OPER_I_16();
\r
3226 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3227 uint dest = m68ki_read_16(ea);
\r
3228 uint* compare = ®_D[word2 & 7];
\r
3229 uint res = dest - MASK_OUT_ABOVE_16(*compare);
\r
3231 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3232 FLAG_N = NFLAG_16(res);
\r
3233 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3234 FLAG_V = VFLAG_SUB_16(*compare, dest, res);
\r
3235 FLAG_C = CFLAG_16(res);
\r
3238 *compare = MASK_OUT_BELOW_16(*compare) | dest;
\r
3242 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_D[(word2 >> 6) & 7]));
\r
3246 m68ki_exception_illegal();
\r
3250 M68KMAKE_OP(cas, 32, ., .)
\r
3252 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3254 uint word2 = OPER_I_16();
\r
3255 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3256 uint dest = m68ki_read_32(ea);
\r
3257 uint* compare = ®_D[word2 & 7];
\r
3258 uint res = dest - *compare;
\r
3260 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3261 FLAG_N = NFLAG_32(res);
\r
3262 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3263 FLAG_V = VFLAG_SUB_32(*compare, dest, res);
\r
3264 FLAG_C = CFLAG_SUB_32(*compare, dest, res);
\r
3271 m68ki_write_32(ea, REG_D[(word2 >> 6) & 7]);
\r
3275 m68ki_exception_illegal();
\r
3279 M68KMAKE_OP(cas2, 16, ., .)
\r
3281 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3283 uint word2 = OPER_I_32();
\r
3284 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3285 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3286 uint dest1 = m68ki_read_16(ea1);
\r
3287 uint res1 = dest1 - MASK_OUT_ABOVE_16(*compare1);
\r
3288 uint* compare2 = ®_D[word2 & 7];
\r
3289 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3290 uint dest2 = m68ki_read_16(ea2);
\r
3293 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3294 FLAG_N = NFLAG_16(res1);
\r
3295 FLAG_Z = MASK_OUT_ABOVE_16(res1);
\r
3296 FLAG_V = VFLAG_SUB_16(*compare1, dest1, res1);
\r
3297 FLAG_C = CFLAG_16(res1);
\r
3301 res2 = dest2 - MASK_OUT_ABOVE_16(*compare2);
\r
3303 FLAG_N = NFLAG_16(res2);
\r
3304 FLAG_Z = MASK_OUT_ABOVE_16(res2);
\r
3305 FLAG_V = VFLAG_SUB_16(*compare2, dest2, res2);
\r
3306 FLAG_C = CFLAG_16(res2);
\r
3311 m68ki_write_16(ea1, REG_D[(word2 >> 22) & 7]);
\r
3312 m68ki_write_16(ea2, REG_D[(word2 >> 6) & 7]);
\r
3316 *compare1 = BIT_1F(word2) ? MAKE_INT_16(dest1) : MASK_OUT_BELOW_16(*compare1) | dest1;
\r
3317 *compare2 = BIT_F(word2) ? MAKE_INT_16(dest2) : MASK_OUT_BELOW_16(*compare2) | dest2;
\r
3320 m68ki_exception_illegal();
\r
3324 M68KMAKE_OP(cas2, 32, ., .)
\r
3326 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3328 uint word2 = OPER_I_32();
\r
3329 uint* compare1 = ®_D[(word2 >> 16) & 7];
\r
3330 uint ea1 = REG_DA[(word2 >> 28) & 15];
\r
3331 uint dest1 = m68ki_read_32(ea1);
\r
3332 uint res1 = dest1 - *compare1;
\r
3333 uint* compare2 = ®_D[word2 & 7];
\r
3334 uint ea2 = REG_DA[(word2 >> 12) & 15];
\r
3335 uint dest2 = m68ki_read_32(ea2);
\r
3338 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
3339 FLAG_N = NFLAG_32(res1);
\r
3340 FLAG_Z = MASK_OUT_ABOVE_32(res1);
\r
3341 FLAG_V = VFLAG_SUB_32(*compare1, dest1, res1);
\r
3342 FLAG_C = CFLAG_SUB_32(*compare1, dest1, res1);
\r
3346 res2 = dest2 - *compare2;
\r
3348 FLAG_N = NFLAG_32(res2);
\r
3349 FLAG_Z = MASK_OUT_ABOVE_32(res2);
\r
3350 FLAG_V = VFLAG_SUB_32(*compare2, dest2, res2);
\r
3351 FLAG_C = CFLAG_SUB_32(*compare2, dest2, res2);
\r
3356 m68ki_write_32(ea1, REG_D[(word2 >> 22) & 7]);
\r
3357 m68ki_write_32(ea2, REG_D[(word2 >> 6) & 7]);
\r
3361 *compare1 = dest1;
\r
3362 *compare2 = dest2;
\r
3365 m68ki_exception_illegal();
\r
3369 M68KMAKE_OP(chk, 16, ., d)
\r
3371 sint src = MAKE_INT_16(DX);
\r
3372 sint bound = MAKE_INT_16(DY);
\r
3374 if(src >= 0 && src <= bound)
\r
3378 FLAG_N = (src < 0)<<7;
\r
3379 m68ki_exception_trap(EXCEPTION_CHK);
\r
3383 M68KMAKE_OP(chk, 16, ., .)
\r
3385 sint src = MAKE_INT_16(DX);
\r
3386 sint bound = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
3388 if(src >= 0 && src <= bound)
\r
3392 FLAG_N = (src < 0)<<7;
\r
3393 m68ki_exception_trap(EXCEPTION_CHK);
\r
3397 M68KMAKE_OP(chk, 32, ., d)
\r
3399 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3401 sint src = MAKE_INT_32(DX);
\r
3402 sint bound = MAKE_INT_32(DY);
\r
3404 if(src >= 0 && src <= bound)
\r
3408 FLAG_N = (src < 0)<<7;
\r
3409 m68ki_exception_trap(EXCEPTION_CHK);
\r
3412 m68ki_exception_illegal();
\r
3416 M68KMAKE_OP(chk, 32, ., .)
\r
3418 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3420 sint src = MAKE_INT_32(DX);
\r
3421 sint bound = MAKE_INT_32(M68KMAKE_GET_OPER_AY_32);
\r
3423 if(src >= 0 && src <= bound)
\r
3427 FLAG_N = (src < 0)<<7;
\r
3428 m68ki_exception_trap(EXCEPTION_CHK);
\r
3431 m68ki_exception_illegal();
\r
3435 M68KMAKE_OP(chk2cmp2, 8, ., .)
\r
3437 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3439 uint word2 = OPER_I_16();
\r
3440 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3441 uint ea = M68KMAKE_GET_EA_AY_8;
\r
3442 uint lower_bound = m68ki_read_8(ea);
\r
3443 uint upper_bound = m68ki_read_8(ea + 1);
\r
3446 compare = MAKE_INT_8(compare);
\r
3448 FLAG_C = compare - lower_bound;
\r
3449 FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
\r
3453 m68ki_exception_trap(EXCEPTION_CHK);
\r
3457 FLAG_C = upper_bound - compare;
\r
3458 FLAG_Z = MASK_OUT_ABOVE_8(FLAG_C);
\r
3459 if(COND_CS() && BIT_B(word2))
\r
3460 m68ki_exception_trap(EXCEPTION_CHK);
\r
3464 m68ki_exception_illegal();
\r
3468 M68KMAKE_OP(chk2cmp2, 16, ., .)
\r
3470 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3472 uint word2 = OPER_I_16();
\r
3473 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3474 uint ea = M68KMAKE_GET_EA_AY_16;
\r
3475 uint lower_bound = m68ki_read_16(ea);
\r
3476 uint upper_bound = m68ki_read_16(ea + 1);
\r
3479 compare = MAKE_INT_16(compare);
\r
3481 FLAG_C = compare - lower_bound;
\r
3482 FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
\r
3483 FLAG_C = CFLAG_16(FLAG_C);
\r
3487 m68ki_exception_trap(EXCEPTION_CHK);
\r
3491 FLAG_C = upper_bound - compare;
\r
3492 FLAG_Z = MASK_OUT_ABOVE_16(FLAG_C);
\r
3493 FLAG_C = CFLAG_16(FLAG_C);
\r
3494 if(COND_CS() && BIT_B(word2))
\r
3495 m68ki_exception_trap(EXCEPTION_CHK);
\r
3499 m68ki_exception_illegal();
\r
3503 M68KMAKE_OP(chk2cmp2, 32, ., .)
\r
3505 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3507 uint word2 = OPER_I_16();
\r
3508 uint compare = REG_DA[(word2 >> 12) & 15];
\r
3509 uint ea = M68KMAKE_GET_EA_AY_32;
\r
3510 uint lower_bound = m68ki_read_32(ea);
\r
3511 uint upper_bound = m68ki_read_32(ea + 1);
\r
3513 FLAG_C = compare - lower_bound;
\r
3514 FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
\r
3515 FLAG_C = CFLAG_SUB_32(lower_bound, compare, FLAG_C);
\r
3519 m68ki_exception_trap(EXCEPTION_CHK);
\r
3523 FLAG_C = upper_bound - compare;
\r
3524 FLAG_Z = MASK_OUT_ABOVE_32(FLAG_C);
\r
3525 FLAG_C = CFLAG_SUB_32(compare, upper_bound, FLAG_C);
\r
3526 if(COND_CS() && BIT_B(word2))
\r
3527 m68ki_exception_trap(EXCEPTION_CHK);
\r
3531 m68ki_exception_illegal();
\r
3535 M68KMAKE_OP(clr, 8, ., d)
\r
3539 FLAG_N = NFLAG_CLEAR;
\r
3540 FLAG_V = VFLAG_CLEAR;
\r
3541 FLAG_C = CFLAG_CLEAR;
\r
3542 FLAG_Z = ZFLAG_SET;
\r
3546 M68KMAKE_OP(clr, 8, ., .)
\r
3548 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
3550 FLAG_N = NFLAG_CLEAR;
\r
3551 FLAG_V = VFLAG_CLEAR;
\r
3552 FLAG_C = CFLAG_CLEAR;
\r
3553 FLAG_Z = ZFLAG_SET;
\r
3557 M68KMAKE_OP(clr, 16, ., d)
\r
3561 FLAG_N = NFLAG_CLEAR;
\r
3562 FLAG_V = VFLAG_CLEAR;
\r
3563 FLAG_C = CFLAG_CLEAR;
\r
3564 FLAG_Z = ZFLAG_SET;
\r
3568 M68KMAKE_OP(clr, 16, ., .)
\r
3570 m68ki_write_16(M68KMAKE_GET_EA_AY_16, 0);
\r
3572 FLAG_N = NFLAG_CLEAR;
\r
3573 FLAG_V = VFLAG_CLEAR;
\r
3574 FLAG_C = CFLAG_CLEAR;
\r
3575 FLAG_Z = ZFLAG_SET;
\r
3579 M68KMAKE_OP(clr, 32, ., d)
\r
3583 FLAG_N = NFLAG_CLEAR;
\r
3584 FLAG_V = VFLAG_CLEAR;
\r
3585 FLAG_C = CFLAG_CLEAR;
\r
3586 FLAG_Z = ZFLAG_SET;
\r
3590 M68KMAKE_OP(clr, 32, ., .)
\r
3592 m68ki_write_32(M68KMAKE_GET_EA_AY_32, 0);
\r
3594 FLAG_N = NFLAG_CLEAR;
\r
3595 FLAG_V = VFLAG_CLEAR;
\r
3596 FLAG_C = CFLAG_CLEAR;
\r
3597 FLAG_Z = ZFLAG_SET;
\r
3601 M68KMAKE_OP(cmp, 8, ., d)
\r
3603 uint src = MASK_OUT_ABOVE_8(DY);
\r
3604 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3605 uint res = dst - src;
\r
3607 FLAG_N = NFLAG_8(res);
\r
3608 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3609 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3610 FLAG_C = CFLAG_8(res);
\r
3614 M68KMAKE_OP(cmp, 8, ., .)
\r
3616 uint src = M68KMAKE_GET_OPER_AY_8;
\r
3617 uint dst = MASK_OUT_ABOVE_8(DX);
\r
3618 uint res = dst - src;
\r
3620 FLAG_N = NFLAG_8(res);
\r
3621 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3622 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3623 FLAG_C = CFLAG_8(res);
\r
3627 M68KMAKE_OP(cmp, 16, ., d)
\r
3629 uint src = MASK_OUT_ABOVE_16(DY);
\r
3630 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3631 uint res = dst - src;
\r
3633 FLAG_N = NFLAG_16(res);
\r
3634 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3635 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3636 FLAG_C = CFLAG_16(res);
\r
3640 M68KMAKE_OP(cmp, 16, ., a)
\r
3642 uint src = MASK_OUT_ABOVE_16(AY);
\r
3643 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3644 uint res = dst - src;
\r
3646 FLAG_N = NFLAG_16(res);
\r
3647 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3648 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3649 FLAG_C = CFLAG_16(res);
\r
3653 M68KMAKE_OP(cmp, 16, ., .)
\r
3655 uint src = M68KMAKE_GET_OPER_AY_16;
\r
3656 uint dst = MASK_OUT_ABOVE_16(DX);
\r
3657 uint res = dst - src;
\r
3659 FLAG_N = NFLAG_16(res);
\r
3660 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3661 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3662 FLAG_C = CFLAG_16(res);
\r
3666 M68KMAKE_OP(cmp, 32, ., d)
\r
3670 uint res = dst - src;
\r
3672 FLAG_N = NFLAG_32(res);
\r
3673 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3674 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3675 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3679 M68KMAKE_OP(cmp, 32, ., a)
\r
3683 uint res = dst - src;
\r
3685 FLAG_N = NFLAG_32(res);
\r
3686 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3687 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3688 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3692 M68KMAKE_OP(cmp, 32, ., .)
\r
3694 uint src = M68KMAKE_GET_OPER_AY_32;
\r
3696 uint res = dst - src;
\r
3698 FLAG_N = NFLAG_32(res);
\r
3699 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3700 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3701 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3705 M68KMAKE_OP(cmpa, 16, ., d)
\r
3707 uint src = MAKE_INT_16(DY);
\r
3709 uint res = dst - src;
\r
3711 FLAG_N = NFLAG_32(res);
\r
3712 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3713 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3714 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3718 M68KMAKE_OP(cmpa, 16, ., a)
\r
3720 uint src = MAKE_INT_16(AY);
\r
3722 uint res = dst - src;
\r
3724 FLAG_N = NFLAG_32(res);
\r
3725 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3726 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3727 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3731 M68KMAKE_OP(cmpa, 16, ., .)
\r
3733 uint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
3735 uint res = dst - src;
\r
3737 FLAG_N = NFLAG_32(res);
\r
3738 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3739 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3740 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3744 M68KMAKE_OP(cmpa, 32, ., d)
\r
3748 uint res = dst - src;
\r
3750 FLAG_N = NFLAG_32(res);
\r
3751 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3752 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3753 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3757 M68KMAKE_OP(cmpa, 32, ., a)
\r
3761 uint res = dst - src;
\r
3763 FLAG_N = NFLAG_32(res);
\r
3764 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3765 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3766 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3770 M68KMAKE_OP(cmpa, 32, ., .)
\r
3772 uint src = M68KMAKE_GET_OPER_AY_32;
\r
3774 uint res = dst - src;
\r
3776 FLAG_N = NFLAG_32(res);
\r
3777 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3778 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3779 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3783 M68KMAKE_OP(cmpi, 8, ., d)
\r
3785 uint src = OPER_I_8();
\r
3786 uint dst = MASK_OUT_ABOVE_8(DY);
\r
3787 uint res = dst - src;
\r
3789 FLAG_N = NFLAG_8(res);
\r
3790 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3791 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3792 FLAG_C = CFLAG_8(res);
\r
3796 M68KMAKE_OP(cmpi, 8, ., .)
\r
3798 uint src = OPER_I_8();
\r
3799 uint dst = M68KMAKE_GET_OPER_AY_8;
\r
3800 uint res = dst - src;
\r
3802 FLAG_N = NFLAG_8(res);
\r
3803 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3804 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3805 FLAG_C = CFLAG_8(res);
\r
3809 M68KMAKE_OP(cmpi, 8, ., pcdi)
\r
3811 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3813 uint src = OPER_I_8();
\r
3814 uint dst = OPER_PCDI_8();
\r
3815 uint res = dst - src;
\r
3817 FLAG_N = NFLAG_8(res);
\r
3818 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3819 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3820 FLAG_C = CFLAG_8(res);
\r
3823 m68ki_exception_illegal();
\r
3827 M68KMAKE_OP(cmpi, 8, ., pcix)
\r
3829 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3831 uint src = OPER_I_8();
\r
3832 uint dst = OPER_PCIX_8();
\r
3833 uint res = dst - src;
\r
3835 FLAG_N = NFLAG_8(res);
\r
3836 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3837 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3838 FLAG_C = CFLAG_8(res);
\r
3841 m68ki_exception_illegal();
\r
3845 M68KMAKE_OP(cmpi, 16, ., d)
\r
3847 uint src = OPER_I_16();
\r
3848 uint dst = MASK_OUT_ABOVE_16(DY);
\r
3849 uint res = dst - src;
\r
3851 FLAG_N = NFLAG_16(res);
\r
3852 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3853 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3854 FLAG_C = CFLAG_16(res);
\r
3858 M68KMAKE_OP(cmpi, 16, ., .)
\r
3860 uint src = OPER_I_16();
\r
3861 uint dst = M68KMAKE_GET_OPER_AY_16;
\r
3862 uint res = dst - src;
\r
3864 FLAG_N = NFLAG_16(res);
\r
3865 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3866 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3867 FLAG_C = CFLAG_16(res);
\r
3871 M68KMAKE_OP(cmpi, 16, ., pcdi)
\r
3873 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3875 uint src = OPER_I_16();
\r
3876 uint dst = OPER_PCDI_16();
\r
3877 uint res = dst - src;
\r
3879 FLAG_N = NFLAG_16(res);
\r
3880 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3881 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3882 FLAG_C = CFLAG_16(res);
\r
3885 m68ki_exception_illegal();
\r
3889 M68KMAKE_OP(cmpi, 16, ., pcix)
\r
3891 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3893 uint src = OPER_I_16();
\r
3894 uint dst = OPER_PCIX_16();
\r
3895 uint res = dst - src;
\r
3897 FLAG_N = NFLAG_16(res);
\r
3898 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
3899 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
3900 FLAG_C = CFLAG_16(res);
\r
3903 m68ki_exception_illegal();
\r
3907 M68KMAKE_OP(cmpi, 32, ., d)
\r
3909 uint src = OPER_I_32();
\r
3911 uint res = dst - src;
\r
3913 FLAG_N = NFLAG_32(res);
\r
3914 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3915 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3916 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3920 M68KMAKE_OP(cmpi, 32, ., .)
\r
3922 uint src = OPER_I_32();
\r
3923 uint dst = M68KMAKE_GET_OPER_AY_32;
\r
3924 uint res = dst - src;
\r
3926 FLAG_N = NFLAG_32(res);
\r
3927 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3928 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3929 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3933 M68KMAKE_OP(cmpi, 32, ., pcdi)
\r
3935 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3937 uint src = OPER_I_32();
\r
3938 uint dst = OPER_PCDI_32();
\r
3939 uint res = dst - src;
\r
3941 FLAG_N = NFLAG_32(res);
\r
3942 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3943 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3944 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3947 m68ki_exception_illegal();
\r
3951 M68KMAKE_OP(cmpi, 32, ., pcix)
\r
3953 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
3955 uint src = OPER_I_32();
\r
3956 uint dst = OPER_PCIX_32();
\r
3957 uint res = dst - src;
\r
3959 FLAG_N = NFLAG_32(res);
\r
3960 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
3961 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
3962 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
3965 m68ki_exception_illegal();
\r
3969 M68KMAKE_OP(cmpm, 8, ., ax7)
\r
3971 uint src = OPER_AY_PI_8();
\r
3972 uint dst = OPER_A7_PI_8();
\r
3973 uint res = dst - src;
\r
3975 FLAG_N = NFLAG_8(res);
\r
3976 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3977 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3978 FLAG_C = CFLAG_8(res);
\r
3982 M68KMAKE_OP(cmpm, 8, ., ay7)
\r
3984 uint src = OPER_A7_PI_8();
\r
3985 uint dst = OPER_AX_PI_8();
\r
3986 uint res = dst - src;
\r
3988 FLAG_N = NFLAG_8(res);
\r
3989 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
3990 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
3991 FLAG_C = CFLAG_8(res);
\r
3995 M68KMAKE_OP(cmpm, 8, ., axy7)
\r
3997 uint src = OPER_A7_PI_8();
\r
3998 uint dst = OPER_A7_PI_8();
\r
3999 uint res = dst - src;
\r
4001 FLAG_N = NFLAG_8(res);
\r
4002 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4003 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4004 FLAG_C = CFLAG_8(res);
\r
4008 M68KMAKE_OP(cmpm, 8, ., .)
\r
4010 uint src = OPER_AY_PI_8();
\r
4011 uint dst = OPER_AX_PI_8();
\r
4012 uint res = dst - src;
\r
4014 FLAG_N = NFLAG_8(res);
\r
4015 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
4016 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
4017 FLAG_C = CFLAG_8(res);
\r
4021 M68KMAKE_OP(cmpm, 16, ., .)
\r
4023 uint src = OPER_AY_PI_16();
\r
4024 uint dst = OPER_AX_PI_16();
\r
4025 uint res = dst - src;
\r
4027 FLAG_N = NFLAG_16(res);
\r
4028 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
4029 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
4030 FLAG_C = CFLAG_16(res);
\r
4034 M68KMAKE_OP(cmpm, 32, ., .)
\r
4036 uint src = OPER_AY_PI_32();
\r
4037 uint dst = OPER_AX_PI_32();
\r
4038 uint res = dst - src;
\r
4040 FLAG_N = NFLAG_32(res);
\r
4041 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
4042 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
4043 FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
4047 M68KMAKE_OP(cpbcc, 32, ., .)
\r
4049 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4051 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4052 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4053 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4056 m68ki_exception_1111();
\r
4060 M68KMAKE_OP(cpdbcc, 32, ., .)
\r
4062 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4064 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4065 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4066 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4069 m68ki_exception_1111();
\r
4073 M68KMAKE_OP(cpgen, 32, ., .)
\r
4075 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4077 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4078 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4079 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4082 m68ki_exception_1111();
\r
4086 M68KMAKE_OP(cpscc, 32, ., .)
\r
4088 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4090 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4091 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4092 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4095 m68ki_exception_1111();
\r
4099 M68KMAKE_OP(cptrapcc, 32, ., .)
\r
4101 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4103 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
4104 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
4105 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
4108 m68ki_exception_1111();
\r
4112 M68KMAKE_OP(dbt, 16, ., .)
\r
4118 M68KMAKE_OP(dbf, 16, ., .)
\r
4120 uint* r_dst = &DY;
\r
4121 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4123 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4126 uint offset = OPER_I_16();
\r
4128 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4129 m68ki_branch_16(offset);
\r
4136 M68KMAKE_OP(dbcc, 16, ., .)
\r
4138 if(M68KMAKE_NOT_CC)
\r
4140 uint* r_dst = &DY;
\r
4141 uint res = MASK_OUT_ABOVE_16(*r_dst - 1);
\r
4143 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
4146 uint offset = OPER_I_16();
\r
4148 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4149 m68ki_branch_16(offset);
\r
4150 USE_CYCLES(CYC_DBCC_F_NOEXP);
\r
4154 USE_CYCLES(CYC_DBCC_F_EXP);
\r
4161 M68KMAKE_OP(divs, 16, ., d)
\r
4163 uint* r_dst = &DX;
\r
4164 sint src = MAKE_INT_16(DY);
\r
4170 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4173 FLAG_N = NFLAG_CLEAR;
\r
4174 FLAG_V = VFLAG_CLEAR;
\r
4175 FLAG_C = CFLAG_CLEAR;
\r
4180 quotient = MAKE_INT_32(*r_dst) / src;
\r
4181 remainder = MAKE_INT_32(*r_dst) % src;
\r
4183 if(quotient == MAKE_INT_16(quotient))
\r
4185 FLAG_Z = quotient;
\r
4186 FLAG_N = NFLAG_16(quotient);
\r
4187 FLAG_V = VFLAG_CLEAR;
\r
4188 FLAG_C = CFLAG_CLEAR;
\r
4189 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4192 FLAG_V = VFLAG_SET;
\r
4195 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4199 M68KMAKE_OP(divs, 16, ., .)
\r
4201 uint* r_dst = &DX;
\r
4202 sint src = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
4208 if((uint32)*r_dst == 0x80000000 && src == -1)
\r
4211 FLAG_N = NFLAG_CLEAR;
\r
4212 FLAG_V = VFLAG_CLEAR;
\r
4213 FLAG_C = CFLAG_CLEAR;
\r
4218 quotient = MAKE_INT_32(*r_dst) / src;
\r
4219 remainder = MAKE_INT_32(*r_dst) % src;
\r
4221 if(quotient == MAKE_INT_16(quotient))
\r
4223 FLAG_Z = quotient;
\r
4224 FLAG_N = NFLAG_16(quotient);
\r
4225 FLAG_V = VFLAG_CLEAR;
\r
4226 FLAG_C = CFLAG_CLEAR;
\r
4227 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4230 FLAG_V = VFLAG_SET;
\r
4233 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4237 M68KMAKE_OP(divu, 16, ., d)
\r
4239 uint* r_dst = &DX;
\r
4240 uint src = MASK_OUT_ABOVE_16(DY);
\r
4244 uint quotient = *r_dst / src;
\r
4245 uint remainder = *r_dst % src;
\r
4247 if(quotient < 0x10000)
\r
4249 FLAG_Z = quotient;
\r
4250 FLAG_N = NFLAG_16(quotient);
\r
4251 FLAG_V = VFLAG_CLEAR;
\r
4252 FLAG_C = CFLAG_CLEAR;
\r
4253 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4256 FLAG_V = VFLAG_SET;
\r
4259 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4263 M68KMAKE_OP(divu, 16, ., .)
\r
4265 uint* r_dst = &DX;
\r
4266 uint src = M68KMAKE_GET_OPER_AY_16;
\r
4270 uint quotient = *r_dst / src;
\r
4271 uint remainder = *r_dst % src;
\r
4273 if(quotient < 0x10000)
\r
4275 FLAG_Z = quotient;
\r
4276 FLAG_N = NFLAG_16(quotient);
\r
4277 FLAG_V = VFLAG_CLEAR;
\r
4278 FLAG_C = CFLAG_CLEAR;
\r
4279 *r_dst = MASK_OUT_ABOVE_32(MASK_OUT_ABOVE_16(quotient) | (remainder << 16));
\r
4282 FLAG_V = VFLAG_SET;
\r
4285 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4289 M68KMAKE_OP(divl, 32, ., d)
\r
4291 #if M68K_USE_64_BIT
\r
4293 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4295 uint word2 = OPER_I_16();
\r
4296 uint64 divisor = DY;
\r
4297 uint64 dividend = 0;
\r
4298 uint64 quotient = 0;
\r
4299 uint64 remainder = 0;
\r
4303 if(BIT_A(word2)) /* 64 bit */
\r
4305 dividend = REG_D[word2 & 7];
\r
4307 dividend |= REG_D[(word2 >> 12) & 7];
\r
4309 if(BIT_B(word2)) /* signed */
\r
4311 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4312 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4313 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4315 FLAG_V = VFLAG_SET;
\r
4319 else /* unsigned */
\r
4321 quotient = dividend / divisor;
\r
4322 if(quotient > 0xffffffff)
\r
4324 FLAG_V = VFLAG_SET;
\r
4327 remainder = dividend % divisor;
\r
4332 dividend = REG_D[(word2 >> 12) & 7];
\r
4333 if(BIT_B(word2)) /* signed */
\r
4335 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4336 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4338 else /* unsigned */
\r
4340 quotient = dividend / divisor;
\r
4341 remainder = dividend % divisor;
\r
4345 REG_D[word2 & 7] = remainder;
\r
4346 REG_D[(word2 >> 12) & 7] = quotient;
\r
4348 FLAG_N = NFLAG_32(quotient);
\r
4349 FLAG_Z = quotient;
\r
4350 FLAG_V = VFLAG_CLEAR;
\r
4351 FLAG_C = CFLAG_CLEAR;
\r
4354 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4357 m68ki_exception_illegal();
\r
4361 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4363 uint word2 = OPER_I_16();
\r
4364 uint divisor = DY;
\r
4365 uint dividend_hi = REG_D[word2 & 7];
\r
4366 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4367 uint quotient = 0;
\r
4368 uint remainder = 0;
\r
4369 uint dividend_neg = 0;
\r
4370 uint divisor_neg = 0;
\r
4376 /* quad / long : long quotient, long remainder */
\r
4379 if(BIT_B(word2)) /* signed */
\r
4381 /* special case in signed divide */
\r
4382 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4384 REG_D[word2 & 7] = 0;
\r
4385 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4387 FLAG_N = NFLAG_SET;
\r
4388 FLAG_Z = ZFLAG_CLEAR;
\r
4389 FLAG_V = VFLAG_CLEAR;
\r
4390 FLAG_C = CFLAG_CLEAR;
\r
4393 if(GET_MSB_32(dividend_hi))
\r
4396 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4397 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4399 if(GET_MSB_32(divisor))
\r
4402 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4407 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4408 if(dividend_hi >= divisor)
\r
4410 FLAG_V = VFLAG_SET;
\r
4414 for(i = 31; i >= 0; i--)
\r
4417 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4418 if(remainder >= divisor)
\r
4420 remainder -= divisor;
\r
4424 for(i = 31; i >= 0; i--)
\r
4427 overflow = GET_MSB_32(remainder);
\r
4428 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4429 if(remainder >= divisor || overflow)
\r
4431 remainder -= divisor;
\r
4436 if(BIT_B(word2)) /* signed */
\r
4438 if(quotient > 0x7fffffff)
\r
4440 FLAG_V = VFLAG_SET;
\r
4445 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4446 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4449 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4452 REG_D[word2 & 7] = remainder;
\r
4453 REG_D[(word2 >> 12) & 7] = quotient;
\r
4455 FLAG_N = NFLAG_32(quotient);
\r
4456 FLAG_Z = quotient;
\r
4457 FLAG_V = VFLAG_CLEAR;
\r
4458 FLAG_C = CFLAG_CLEAR;
\r
4462 /* long / long: long quotient, maybe long remainder */
\r
4463 if(BIT_B(word2)) /* signed */
\r
4465 /* Special case in divide */
\r
4466 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4468 FLAG_N = NFLAG_SET;
\r
4469 FLAG_Z = ZFLAG_CLEAR;
\r
4470 FLAG_V = VFLAG_CLEAR;
\r
4471 FLAG_C = CFLAG_CLEAR;
\r
4472 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4473 REG_D[word2 & 7] = 0;
\r
4476 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4477 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4481 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4482 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4485 FLAG_N = NFLAG_32(quotient);
\r
4486 FLAG_Z = quotient;
\r
4487 FLAG_V = VFLAG_CLEAR;
\r
4488 FLAG_C = CFLAG_CLEAR;
\r
4491 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4494 m68ki_exception_illegal();
\r
4500 M68KMAKE_OP(divl, 32, ., .)
\r
4502 #if M68K_USE_64_BIT
\r
4504 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4506 uint word2 = OPER_I_16();
\r
4507 uint64 divisor = M68KMAKE_GET_OPER_AY_32;
\r
4508 uint64 dividend = 0;
\r
4509 uint64 quotient = 0;
\r
4510 uint64 remainder = 0;
\r
4514 if(BIT_A(word2)) /* 64 bit */
\r
4516 dividend = REG_D[word2 & 7];
\r
4518 dividend |= REG_D[(word2 >> 12) & 7];
\r
4520 if(BIT_B(word2)) /* signed */
\r
4522 quotient = (uint64)((sint64)dividend / (sint64)((sint32)divisor));
\r
4523 remainder = (uint64)((sint64)dividend % (sint64)((sint32)divisor));
\r
4524 if((sint64)quotient != (sint64)((sint32)quotient))
\r
4526 FLAG_V = VFLAG_SET;
\r
4530 else /* unsigned */
\r
4532 quotient = dividend / divisor;
\r
4533 if(quotient > 0xffffffff)
\r
4535 FLAG_V = VFLAG_SET;
\r
4538 remainder = dividend % divisor;
\r
4543 dividend = REG_D[(word2 >> 12) & 7];
\r
4544 if(BIT_B(word2)) /* signed */
\r
4546 quotient = (uint64)((sint64)((sint32)dividend) / (sint64)((sint32)divisor));
\r
4547 remainder = (uint64)((sint64)((sint32)dividend) % (sint64)((sint32)divisor));
\r
4549 else /* unsigned */
\r
4551 quotient = dividend / divisor;
\r
4552 remainder = dividend % divisor;
\r
4556 REG_D[word2 & 7] = remainder;
\r
4557 REG_D[(word2 >> 12) & 7] = quotient;
\r
4559 FLAG_N = NFLAG_32(quotient);
\r
4560 FLAG_Z = quotient;
\r
4561 FLAG_V = VFLAG_CLEAR;
\r
4562 FLAG_C = CFLAG_CLEAR;
\r
4565 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4568 m68ki_exception_illegal();
\r
4572 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4574 uint word2 = OPER_I_16();
\r
4575 uint divisor = M68KMAKE_GET_OPER_AY_32;
\r
4576 uint dividend_hi = REG_D[word2 & 7];
\r
4577 uint dividend_lo = REG_D[(word2 >> 12) & 7];
\r
4578 uint quotient = 0;
\r
4579 uint remainder = 0;
\r
4580 uint dividend_neg = 0;
\r
4581 uint divisor_neg = 0;
\r
4587 /* quad / long : long quotient, long remainder */
\r
4590 if(BIT_B(word2)) /* signed */
\r
4592 /* special case in signed divide */
\r
4593 if(dividend_hi == 0 && dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4595 REG_D[word2 & 7] = 0;
\r
4596 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4598 FLAG_N = NFLAG_SET;
\r
4599 FLAG_Z = ZFLAG_CLEAR;
\r
4600 FLAG_V = VFLAG_CLEAR;
\r
4601 FLAG_C = CFLAG_CLEAR;
\r
4604 if(GET_MSB_32(dividend_hi))
\r
4607 dividend_hi = (uint)MASK_OUT_ABOVE_32((-(sint)dividend_hi) - (dividend_lo != 0));
\r
4608 dividend_lo = (uint)MASK_OUT_ABOVE_32(-(sint)dividend_lo);
\r
4610 if(GET_MSB_32(divisor))
\r
4613 divisor = (uint)MASK_OUT_ABOVE_32(-(sint)divisor);
\r
4618 /* if the upper long is greater than the divisor, we're overflowing. */
\r
4619 if(dividend_hi >= divisor)
\r
4621 FLAG_V = VFLAG_SET;
\r
4625 for(i = 31; i >= 0; i--)
\r
4628 remainder = (remainder << 1) + ((dividend_hi >> i) & 1);
\r
4629 if(remainder >= divisor)
\r
4631 remainder -= divisor;
\r
4635 for(i = 31; i >= 0; i--)
\r
4638 overflow = GET_MSB_32(remainder);
\r
4639 remainder = (remainder << 1) + ((dividend_lo >> i) & 1);
\r
4640 if(remainder >= divisor || overflow)
\r
4642 remainder -= divisor;
\r
4647 if(BIT_B(word2)) /* signed */
\r
4649 if(quotient > 0x7fffffff)
\r
4651 FLAG_V = VFLAG_SET;
\r
4656 remainder = (uint)MASK_OUT_ABOVE_32(-(sint)remainder);
\r
4657 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4660 quotient = (uint)MASK_OUT_ABOVE_32(-(sint)quotient);
\r
4663 REG_D[word2 & 7] = remainder;
\r
4664 REG_D[(word2 >> 12) & 7] = quotient;
\r
4666 FLAG_N = NFLAG_32(quotient);
\r
4667 FLAG_Z = quotient;
\r
4668 FLAG_V = VFLAG_CLEAR;
\r
4669 FLAG_C = CFLAG_CLEAR;
\r
4673 /* long / long: long quotient, maybe long remainder */
\r
4674 if(BIT_B(word2)) /* signed */
\r
4676 /* Special case in divide */
\r
4677 if(dividend_lo == 0x80000000 && divisor == 0xffffffff)
\r
4679 FLAG_N = NFLAG_SET;
\r
4680 FLAG_Z = ZFLAG_CLEAR;
\r
4681 FLAG_V = VFLAG_CLEAR;
\r
4682 FLAG_C = CFLAG_CLEAR;
\r
4683 REG_D[(word2 >> 12) & 7] = 0x80000000;
\r
4684 REG_D[word2 & 7] = 0;
\r
4687 REG_D[word2 & 7] = MAKE_INT_32(dividend_lo) % MAKE_INT_32(divisor);
\r
4688 quotient = REG_D[(word2 >> 12) & 7] = MAKE_INT_32(dividend_lo) / MAKE_INT_32(divisor);
\r
4692 REG_D[word2 & 7] = MASK_OUT_ABOVE_32(dividend_lo) % MASK_OUT_ABOVE_32(divisor);
\r
4693 quotient = REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(dividend_lo) / MASK_OUT_ABOVE_32(divisor);
\r
4696 FLAG_N = NFLAG_32(quotient);
\r
4697 FLAG_Z = quotient;
\r
4698 FLAG_V = VFLAG_CLEAR;
\r
4699 FLAG_C = CFLAG_CLEAR;
\r
4702 m68ki_exception_trap(EXCEPTION_ZERO_DIVIDE);
\r
4705 m68ki_exception_illegal();
\r
4711 M68KMAKE_OP(eor, 8, ., d)
\r
4713 uint res = MASK_OUT_ABOVE_8(DY ^= MASK_OUT_ABOVE_8(DX));
\r
4715 FLAG_N = NFLAG_8(res);
\r
4717 FLAG_C = CFLAG_CLEAR;
\r
4718 FLAG_V = VFLAG_CLEAR;
\r
4722 M68KMAKE_OP(eor, 8, ., .)
\r
4724 uint ea = M68KMAKE_GET_EA_AY_8;
\r
4725 uint res = MASK_OUT_ABOVE_8(DX ^ m68ki_read_8(ea));
\r
4727 m68ki_write_8(ea, res);
\r
4729 FLAG_N = NFLAG_8(res);
\r
4731 FLAG_C = CFLAG_CLEAR;
\r
4732 FLAG_V = VFLAG_CLEAR;
\r
4736 M68KMAKE_OP(eor, 16, ., d)
\r
4738 uint res = MASK_OUT_ABOVE_16(DY ^= MASK_OUT_ABOVE_16(DX));
\r
4740 FLAG_N = NFLAG_16(res);
\r
4742 FLAG_C = CFLAG_CLEAR;
\r
4743 FLAG_V = VFLAG_CLEAR;
\r
4747 M68KMAKE_OP(eor, 16, ., .)
\r
4749 uint ea = M68KMAKE_GET_EA_AY_16;
\r
4750 uint res = MASK_OUT_ABOVE_16(DX ^ m68ki_read_16(ea));
\r
4752 m68ki_write_16(ea, res);
\r
4754 FLAG_N = NFLAG_16(res);
\r
4756 FLAG_C = CFLAG_CLEAR;
\r
4757 FLAG_V = VFLAG_CLEAR;
\r
4761 M68KMAKE_OP(eor, 32, ., d)
\r
4763 uint res = DY ^= DX;
\r
4765 FLAG_N = NFLAG_32(res);
\r
4767 FLAG_C = CFLAG_CLEAR;
\r
4768 FLAG_V = VFLAG_CLEAR;
\r
4772 M68KMAKE_OP(eor, 32, ., .)
\r
4774 uint ea = M68KMAKE_GET_EA_AY_32;
\r
4775 uint res = DX ^ m68ki_read_32(ea);
\r
4777 m68ki_write_32(ea, res);
\r
4779 FLAG_N = NFLAG_32(res);
\r
4781 FLAG_C = CFLAG_CLEAR;
\r
4782 FLAG_V = VFLAG_CLEAR;
\r
4786 M68KMAKE_OP(eori, 8, ., d)
\r
4788 uint res = MASK_OUT_ABOVE_8(DY ^= OPER_I_8());
\r
4790 FLAG_N = NFLAG_8(res);
\r
4792 FLAG_C = CFLAG_CLEAR;
\r
4793 FLAG_V = VFLAG_CLEAR;
\r
4797 M68KMAKE_OP(eori, 8, ., .)
\r
4799 uint src = OPER_I_8();
\r
4800 uint ea = M68KMAKE_GET_EA_AY_8;
\r
4801 uint res = src ^ m68ki_read_8(ea);
\r
4803 m68ki_write_8(ea, res);
\r
4805 FLAG_N = NFLAG_8(res);
\r
4807 FLAG_C = CFLAG_CLEAR;
\r
4808 FLAG_V = VFLAG_CLEAR;
\r
4812 M68KMAKE_OP(eori, 16, ., d)
\r
4814 uint res = MASK_OUT_ABOVE_16(DY ^= OPER_I_16());
\r
4816 FLAG_N = NFLAG_16(res);
\r
4818 FLAG_C = CFLAG_CLEAR;
\r
4819 FLAG_V = VFLAG_CLEAR;
\r
4823 M68KMAKE_OP(eori, 16, ., .)
\r
4825 uint src = OPER_I_16();
\r
4826 uint ea = M68KMAKE_GET_EA_AY_16;
\r
4827 uint res = src ^ m68ki_read_16(ea);
\r
4829 m68ki_write_16(ea, res);
\r
4831 FLAG_N = NFLAG_16(res);
\r
4833 FLAG_C = CFLAG_CLEAR;
\r
4834 FLAG_V = VFLAG_CLEAR;
\r
4838 M68KMAKE_OP(eori, 32, ., d)
\r
4840 uint res = DY ^= OPER_I_32();
\r
4842 FLAG_N = NFLAG_32(res);
\r
4844 FLAG_C = CFLAG_CLEAR;
\r
4845 FLAG_V = VFLAG_CLEAR;
\r
4849 M68KMAKE_OP(eori, 32, ., .)
\r
4851 uint src = OPER_I_32();
\r
4852 uint ea = M68KMAKE_GET_EA_AY_32;
\r
4853 uint res = src ^ m68ki_read_32(ea);
\r
4855 m68ki_write_32(ea, res);
\r
4857 FLAG_N = NFLAG_32(res);
\r
4859 FLAG_C = CFLAG_CLEAR;
\r
4860 FLAG_V = VFLAG_CLEAR;
\r
4864 M68KMAKE_OP(eori, 16, toc, .)
\r
4866 m68ki_set_ccr(m68ki_get_ccr() ^ OPER_I_16());
\r
4870 M68KMAKE_OP(eori, 16, tos, .)
\r
4874 uint src = OPER_I_16();
\r
4875 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4876 m68ki_set_sr(m68ki_get_sr() ^ src);
\r
4879 m68ki_exception_privilege_violation();
\r
4883 M68KMAKE_OP(exg, 32, dd, .)
\r
4885 uint* reg_a = &DX;
\r
4886 uint* reg_b = &DY;
\r
4887 uint tmp = *reg_a;
\r
4893 M68KMAKE_OP(exg, 32, aa, .)
\r
4895 uint* reg_a = &AX;
\r
4896 uint* reg_b = &AY;
\r
4897 uint tmp = *reg_a;
\r
4903 M68KMAKE_OP(exg, 32, da, .)
\r
4905 uint* reg_a = &DX;
\r
4906 uint* reg_b = &AY;
\r
4907 uint tmp = *reg_a;
\r
4913 M68KMAKE_OP(ext, 16, ., .)
\r
4915 uint* r_dst = &DY;
\r
4917 *r_dst = MASK_OUT_BELOW_16(*r_dst) | MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xff00 : 0);
\r
4919 FLAG_N = NFLAG_16(*r_dst);
\r
4920 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
4921 FLAG_V = VFLAG_CLEAR;
\r
4922 FLAG_C = CFLAG_CLEAR;
\r
4926 M68KMAKE_OP(ext, 32, ., .)
\r
4928 uint* r_dst = &DY;
\r
4930 *r_dst = MASK_OUT_ABOVE_16(*r_dst) | (GET_MSB_16(*r_dst) ? 0xffff0000 : 0);
\r
4932 FLAG_N = NFLAG_32(*r_dst);
\r
4934 FLAG_V = VFLAG_CLEAR;
\r
4935 FLAG_C = CFLAG_CLEAR;
\r
4939 M68KMAKE_OP(extb, 32, ., .)
\r
4941 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
4943 uint* r_dst = &DY;
\r
4945 *r_dst = MASK_OUT_ABOVE_8(*r_dst) | (GET_MSB_8(*r_dst) ? 0xffffff00 : 0);
\r
4947 FLAG_N = NFLAG_32(*r_dst);
\r
4949 FLAG_V = VFLAG_CLEAR;
\r
4950 FLAG_C = CFLAG_CLEAR;
\r
4953 m68ki_exception_illegal();
\r
4957 M68KMAKE_OP(illegal, 0, ., .)
\r
4959 m68ki_exception_illegal();
\r
4962 M68KMAKE_OP(jmp, 32, ., .)
\r
4964 m68ki_jump(M68KMAKE_GET_EA_AY_32);
\r
4965 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4966 if(REG_PC == REG_PPC)
\r
4971 M68KMAKE_OP(jsr, 32, ., .)
\r
4973 uint ea = M68KMAKE_GET_EA_AY_32;
\r
4974 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
4975 m68ki_push_32(REG_PC);
\r
4980 M68KMAKE_OP(lea, 32, ., .)
\r
4982 AX = M68KMAKE_GET_EA_AY_32;
\r
4986 M68KMAKE_OP(link, 16, ., a7)
\r
4989 m68ki_write_32(REG_A[7], REG_A[7]);
\r
4990 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
4994 M68KMAKE_OP(link, 16, ., .)
\r
4996 uint* r_dst = &AY;
\r
4998 m68ki_push_32(*r_dst);
\r
4999 *r_dst = REG_A[7];
\r
5000 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
5004 M68KMAKE_OP(link, 32, ., a7)
\r
5006 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5009 m68ki_write_32(REG_A[7], REG_A[7]);
\r
5010 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5013 m68ki_exception_illegal();
\r
5017 M68KMAKE_OP(link, 32, ., .)
\r
5019 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
5021 uint* r_dst = &AY;
\r
5023 m68ki_push_32(*r_dst);
\r
5024 *r_dst = REG_A[7];
\r
5025 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + OPER_I_32());
\r
5028 m68ki_exception_illegal();
\r
5032 M68KMAKE_OP(lsr, 8, s, .)
\r
5034 uint* r_dst = &DY;
\r
5035 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5036 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5037 uint res = src >> shift;
\r
5039 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5041 FLAG_N = NFLAG_CLEAR;
\r
5043 FLAG_X = FLAG_C = src << (9-shift);
\r
5044 FLAG_V = VFLAG_CLEAR;
\r
5048 M68KMAKE_OP(lsr, 16, s, .)
\r
5050 uint* r_dst = &DY;
\r
5051 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5052 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5053 uint res = src >> shift;
\r
5055 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5057 FLAG_N = NFLAG_CLEAR;
\r
5059 FLAG_X = FLAG_C = src << (9-shift);
\r
5060 FLAG_V = VFLAG_CLEAR;
\r
5064 M68KMAKE_OP(lsr, 32, s, .)
\r
5066 uint* r_dst = &DY;
\r
5067 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5068 uint src = *r_dst;
\r
5069 uint res = src >> shift;
\r
5073 FLAG_N = NFLAG_CLEAR;
\r
5075 FLAG_X = FLAG_C = src << (9-shift);
\r
5076 FLAG_V = VFLAG_CLEAR;
\r
5080 M68KMAKE_OP(lsr, 8, r, .)
\r
5082 uint* r_dst = &DY;
\r
5083 uint shift = DX & 0x3f;
\r
5084 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5085 uint res = src >> shift;
\r
5089 USE_CYCLES(shift<<CYC_SHIFT);
\r
5093 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5094 FLAG_X = FLAG_C = src << (9-shift);
\r
5095 FLAG_N = NFLAG_CLEAR;
\r
5097 FLAG_V = VFLAG_CLEAR;
\r
5101 *r_dst &= 0xffffff00;
\r
5102 FLAG_X = XFLAG_CLEAR;
\r
5103 FLAG_C = CFLAG_CLEAR;
\r
5104 FLAG_N = NFLAG_CLEAR;
\r
5105 FLAG_Z = ZFLAG_SET;
\r
5106 FLAG_V = VFLAG_CLEAR;
\r
5110 FLAG_C = CFLAG_CLEAR;
\r
5111 FLAG_N = NFLAG_8(src);
\r
5113 FLAG_V = VFLAG_CLEAR;
\r
5117 M68KMAKE_OP(lsr, 16, r, .)
\r
5119 uint* r_dst = &DY;
\r
5120 uint shift = DX & 0x3f;
\r
5121 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5122 uint res = src >> shift;
\r
5126 USE_CYCLES(shift<<CYC_SHIFT);
\r
5130 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5131 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5132 FLAG_N = NFLAG_CLEAR;
\r
5134 FLAG_V = VFLAG_CLEAR;
\r
5138 *r_dst &= 0xffff0000;
\r
5139 FLAG_X = XFLAG_CLEAR;
\r
5140 FLAG_C = CFLAG_CLEAR;
\r
5141 FLAG_N = NFLAG_CLEAR;
\r
5142 FLAG_Z = ZFLAG_SET;
\r
5143 FLAG_V = VFLAG_CLEAR;
\r
5147 FLAG_C = CFLAG_CLEAR;
\r
5148 FLAG_N = NFLAG_16(src);
\r
5150 FLAG_V = VFLAG_CLEAR;
\r
5154 M68KMAKE_OP(lsr, 32, r, .)
\r
5156 uint* r_dst = &DY;
\r
5157 uint shift = DX & 0x3f;
\r
5158 uint src = *r_dst;
\r
5159 uint res = src >> shift;
\r
5163 USE_CYCLES(shift<<CYC_SHIFT);
\r
5168 FLAG_C = FLAG_X = (src >> (shift - 1))<<8;
\r
5169 FLAG_N = NFLAG_CLEAR;
\r
5171 FLAG_V = VFLAG_CLEAR;
\r
5176 FLAG_X = FLAG_C = (shift == 32 ? GET_MSB_32(src)>>23 : 0);
\r
5177 FLAG_N = NFLAG_CLEAR;
\r
5178 FLAG_Z = ZFLAG_SET;
\r
5179 FLAG_V = VFLAG_CLEAR;
\r
5183 FLAG_C = CFLAG_CLEAR;
\r
5184 FLAG_N = NFLAG_32(src);
\r
5186 FLAG_V = VFLAG_CLEAR;
\r
5190 M68KMAKE_OP(lsr, 16, ., .)
\r
5192 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5193 uint src = m68ki_read_16(ea);
\r
5194 uint res = src >> 1;
\r
5196 m68ki_write_16(ea, res);
\r
5198 FLAG_N = NFLAG_CLEAR;
\r
5200 FLAG_C = FLAG_X = src << 8;
\r
5201 FLAG_V = VFLAG_CLEAR;
\r
5205 M68KMAKE_OP(lsl, 8, s, .)
\r
5207 uint* r_dst = &DY;
\r
5208 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5209 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5210 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5212 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5214 FLAG_N = NFLAG_8(res);
\r
5216 FLAG_X = FLAG_C = src << shift;
\r
5217 FLAG_V = VFLAG_CLEAR;
\r
5221 M68KMAKE_OP(lsl, 16, s, .)
\r
5223 uint* r_dst = &DY;
\r
5224 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5225 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5226 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5228 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5230 FLAG_N = NFLAG_16(res);
\r
5232 FLAG_X = FLAG_C = src >> (8-shift);
\r
5233 FLAG_V = VFLAG_CLEAR;
\r
5237 M68KMAKE_OP(lsl, 32, s, .)
\r
5239 uint* r_dst = &DY;
\r
5240 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
5241 uint src = *r_dst;
\r
5242 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5246 FLAG_N = NFLAG_32(res);
\r
5248 FLAG_X = FLAG_C = src >> (24-shift);
\r
5249 FLAG_V = VFLAG_CLEAR;
\r
5253 M68KMAKE_OP(lsl, 8, r, .)
\r
5255 uint* r_dst = &DY;
\r
5256 uint shift = DX & 0x3f;
\r
5257 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
5258 uint res = MASK_OUT_ABOVE_8(src << shift);
\r
5262 USE_CYCLES(shift<<CYC_SHIFT);
\r
5266 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5267 FLAG_X = FLAG_C = src << shift;
\r
5268 FLAG_N = NFLAG_8(res);
\r
5270 FLAG_V = VFLAG_CLEAR;
\r
5274 *r_dst &= 0xffffff00;
\r
5275 FLAG_X = XFLAG_CLEAR;
\r
5276 FLAG_C = CFLAG_CLEAR;
\r
5277 FLAG_N = NFLAG_CLEAR;
\r
5278 FLAG_Z = ZFLAG_SET;
\r
5279 FLAG_V = VFLAG_CLEAR;
\r
5283 FLAG_C = CFLAG_CLEAR;
\r
5284 FLAG_N = NFLAG_8(src);
\r
5286 FLAG_V = VFLAG_CLEAR;
\r
5290 M68KMAKE_OP(lsl, 16, r, .)
\r
5292 uint* r_dst = &DY;
\r
5293 uint shift = DX & 0x3f;
\r
5294 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
5295 uint res = MASK_OUT_ABOVE_16(src << shift);
\r
5299 USE_CYCLES(shift<<CYC_SHIFT);
\r
5303 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5304 FLAG_X = FLAG_C = (src << shift) >> 8;
\r
5305 FLAG_N = NFLAG_16(res);
\r
5307 FLAG_V = VFLAG_CLEAR;
\r
5311 *r_dst &= 0xffff0000;
\r
5312 FLAG_X = XFLAG_CLEAR;
\r
5313 FLAG_C = CFLAG_CLEAR;
\r
5314 FLAG_N = NFLAG_CLEAR;
\r
5315 FLAG_Z = ZFLAG_SET;
\r
5316 FLAG_V = VFLAG_CLEAR;
\r
5320 FLAG_C = CFLAG_CLEAR;
\r
5321 FLAG_N = NFLAG_16(src);
\r
5323 FLAG_V = VFLAG_CLEAR;
\r
5327 M68KMAKE_OP(lsl, 32, r, .)
\r
5329 uint* r_dst = &DY;
\r
5330 uint shift = DX & 0x3f;
\r
5331 uint src = *r_dst;
\r
5332 uint res = MASK_OUT_ABOVE_32(src << shift);
\r
5336 USE_CYCLES(shift<<CYC_SHIFT);
\r
5341 FLAG_X = FLAG_C = (src >> (32 - shift)) << 8;
\r
5342 FLAG_N = NFLAG_32(res);
\r
5344 FLAG_V = VFLAG_CLEAR;
\r
5349 FLAG_X = FLAG_C = ((shift == 32 ? src & 1 : 0))<<8;
\r
5350 FLAG_N = NFLAG_CLEAR;
\r
5351 FLAG_Z = ZFLAG_SET;
\r
5352 FLAG_V = VFLAG_CLEAR;
\r
5356 FLAG_C = CFLAG_CLEAR;
\r
5357 FLAG_N = NFLAG_32(src);
\r
5359 FLAG_V = VFLAG_CLEAR;
\r
5363 M68KMAKE_OP(lsl, 16, ., .)
\r
5365 uint ea = M68KMAKE_GET_EA_AY_16;
\r
5366 uint src = m68ki_read_16(ea);
\r
5367 uint res = MASK_OUT_ABOVE_16(src << 1);
\r
5369 m68ki_write_16(ea, res);
\r
5371 FLAG_N = NFLAG_16(res);
\r
5373 FLAG_X = FLAG_C = src >> 7;
\r
5374 FLAG_V = VFLAG_CLEAR;
\r
5378 M68KMAKE_OP(move, 8, d, d)
\r
5380 uint res = MASK_OUT_ABOVE_8(DY);
\r
5381 uint* r_dst = &DX;
\r
5383 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5385 FLAG_N = NFLAG_8(res);
\r
5387 FLAG_V = VFLAG_CLEAR;
\r
5388 FLAG_C = CFLAG_CLEAR;
\r
5392 M68KMAKE_OP(move, 8, d, .)
\r
5394 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5395 uint* r_dst = &DX;
\r
5397 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
5399 FLAG_N = NFLAG_8(res);
\r
5401 FLAG_V = VFLAG_CLEAR;
\r
5402 FLAG_C = CFLAG_CLEAR;
\r
5406 M68KMAKE_OP(move, 8, ai, d)
\r
5408 uint res = MASK_OUT_ABOVE_8(DY);
\r
5409 uint ea = EA_AX_AI_8();
\r
5411 m68ki_write_8(ea, res);
\r
5413 FLAG_N = NFLAG_8(res);
\r
5415 FLAG_V = VFLAG_CLEAR;
\r
5416 FLAG_C = CFLAG_CLEAR;
\r
5420 M68KMAKE_OP(move, 8, ai, .)
\r
5422 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5423 uint ea = EA_AX_AI_8();
\r
5425 m68ki_write_8(ea, res);
\r
5427 FLAG_N = NFLAG_8(res);
\r
5429 FLAG_V = VFLAG_CLEAR;
\r
5430 FLAG_C = CFLAG_CLEAR;
\r
5434 M68KMAKE_OP(move, 8, pi7, d)
\r
5436 uint res = MASK_OUT_ABOVE_8(DY);
\r
5437 uint ea = EA_A7_PI_8();
\r
5439 m68ki_write_8(ea, res);
\r
5441 FLAG_N = NFLAG_8(res);
\r
5443 FLAG_V = VFLAG_CLEAR;
\r
5444 FLAG_C = CFLAG_CLEAR;
\r
5448 M68KMAKE_OP(move, 8, pi, d)
\r
5450 uint res = MASK_OUT_ABOVE_8(DY);
\r
5451 uint ea = EA_AX_PI_8();
\r
5453 m68ki_write_8(ea, res);
\r
5455 FLAG_N = NFLAG_8(res);
\r
5457 FLAG_V = VFLAG_CLEAR;
\r
5458 FLAG_C = CFLAG_CLEAR;
\r
5462 M68KMAKE_OP(move, 8, pi7, .)
\r
5464 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5465 uint ea = EA_A7_PI_8();
\r
5467 m68ki_write_8(ea, res);
\r
5469 FLAG_N = NFLAG_8(res);
\r
5471 FLAG_V = VFLAG_CLEAR;
\r
5472 FLAG_C = CFLAG_CLEAR;
\r
5476 M68KMAKE_OP(move, 8, pi, .)
\r
5478 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5479 uint ea = EA_AX_PI_8();
\r
5481 m68ki_write_8(ea, res);
\r
5483 FLAG_N = NFLAG_8(res);
\r
5485 FLAG_V = VFLAG_CLEAR;
\r
5486 FLAG_C = CFLAG_CLEAR;
\r
5490 M68KMAKE_OP(move, 8, pd7, d)
\r
5492 uint res = MASK_OUT_ABOVE_8(DY);
\r
5493 uint ea = EA_A7_PD_8();
\r
5495 m68ki_write_8(ea, res);
\r
5497 FLAG_N = NFLAG_8(res);
\r
5499 FLAG_V = VFLAG_CLEAR;
\r
5500 FLAG_C = CFLAG_CLEAR;
\r
5504 M68KMAKE_OP(move, 8, pd, d)
\r
5506 uint res = MASK_OUT_ABOVE_8(DY);
\r
5507 uint ea = EA_AX_PD_8();
\r
5509 m68ki_write_8(ea, res);
\r
5511 FLAG_N = NFLAG_8(res);
\r
5513 FLAG_V = VFLAG_CLEAR;
\r
5514 FLAG_C = CFLAG_CLEAR;
\r
5518 M68KMAKE_OP(move, 8, pd7, .)
\r
5520 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5521 uint ea = EA_A7_PD_8();
\r
5523 m68ki_write_8(ea, res);
\r
5525 FLAG_N = NFLAG_8(res);
\r
5527 FLAG_V = VFLAG_CLEAR;
\r
5528 FLAG_C = CFLAG_CLEAR;
\r
5532 M68KMAKE_OP(move, 8, pd, .)
\r
5534 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5535 uint ea = EA_AX_PD_8();
\r
5537 m68ki_write_8(ea, res);
\r
5539 FLAG_N = NFLAG_8(res);
\r
5541 FLAG_V = VFLAG_CLEAR;
\r
5542 FLAG_C = CFLAG_CLEAR;
\r
5546 M68KMAKE_OP(move, 8, di, d)
\r
5548 uint res = MASK_OUT_ABOVE_8(DY);
\r
5549 uint ea = EA_AX_DI_8();
\r
5551 m68ki_write_8(ea, res);
\r
5553 FLAG_N = NFLAG_8(res);
\r
5555 FLAG_V = VFLAG_CLEAR;
\r
5556 FLAG_C = CFLAG_CLEAR;
\r
5560 M68KMAKE_OP(move, 8, di, .)
\r
5562 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5563 uint ea = EA_AX_DI_8();
\r
5565 m68ki_write_8(ea, res);
\r
5567 FLAG_N = NFLAG_8(res);
\r
5569 FLAG_V = VFLAG_CLEAR;
\r
5570 FLAG_C = CFLAG_CLEAR;
\r
5574 M68KMAKE_OP(move, 8, ix, d)
\r
5576 uint res = MASK_OUT_ABOVE_8(DY);
\r
5577 uint ea = EA_AX_IX_8();
\r
5579 m68ki_write_8(ea, res);
\r
5581 FLAG_N = NFLAG_8(res);
\r
5583 FLAG_V = VFLAG_CLEAR;
\r
5584 FLAG_C = CFLAG_CLEAR;
\r
5588 M68KMAKE_OP(move, 8, ix, .)
\r
5590 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5591 uint ea = EA_AX_IX_8();
\r
5593 m68ki_write_8(ea, res);
\r
5595 FLAG_N = NFLAG_8(res);
\r
5597 FLAG_V = VFLAG_CLEAR;
\r
5598 FLAG_C = CFLAG_CLEAR;
\r
5602 M68KMAKE_OP(move, 8, aw, d)
\r
5604 uint res = MASK_OUT_ABOVE_8(DY);
\r
5605 uint ea = EA_AW_8();
\r
5607 m68ki_write_8(ea, res);
\r
5609 FLAG_N = NFLAG_8(res);
\r
5611 FLAG_V = VFLAG_CLEAR;
\r
5612 FLAG_C = CFLAG_CLEAR;
\r
5616 M68KMAKE_OP(move, 8, aw, .)
\r
5618 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5619 uint ea = EA_AW_8();
\r
5621 m68ki_write_8(ea, res);
\r
5623 FLAG_N = NFLAG_8(res);
\r
5625 FLAG_V = VFLAG_CLEAR;
\r
5626 FLAG_C = CFLAG_CLEAR;
\r
5630 M68KMAKE_OP(move, 8, al, d)
\r
5632 uint res = MASK_OUT_ABOVE_8(DY);
\r
5633 uint ea = EA_AL_8();
\r
5635 m68ki_write_8(ea, res);
\r
5637 FLAG_N = NFLAG_8(res);
\r
5639 FLAG_V = VFLAG_CLEAR;
\r
5640 FLAG_C = CFLAG_CLEAR;
\r
5644 M68KMAKE_OP(move, 8, al, .)
\r
5646 uint res = M68KMAKE_GET_OPER_AY_8;
\r
5647 uint ea = EA_AL_8();
\r
5649 m68ki_write_8(ea, res);
\r
5651 FLAG_N = NFLAG_8(res);
\r
5653 FLAG_V = VFLAG_CLEAR;
\r
5654 FLAG_C = CFLAG_CLEAR;
\r
5658 M68KMAKE_OP(move, 16, d, d)
\r
5660 uint res = MASK_OUT_ABOVE_16(DY);
\r
5661 uint* r_dst = &DX;
\r
5663 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5665 FLAG_N = NFLAG_16(res);
\r
5667 FLAG_V = VFLAG_CLEAR;
\r
5668 FLAG_C = CFLAG_CLEAR;
\r
5672 M68KMAKE_OP(move, 16, d, a)
\r
5674 uint res = MASK_OUT_ABOVE_16(AY);
\r
5675 uint* r_dst = &DX;
\r
5677 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5679 FLAG_N = NFLAG_16(res);
\r
5681 FLAG_V = VFLAG_CLEAR;
\r
5682 FLAG_C = CFLAG_CLEAR;
\r
5686 M68KMAKE_OP(move, 16, d, .)
\r
5688 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5689 uint* r_dst = &DX;
\r
5691 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
5693 FLAG_N = NFLAG_16(res);
\r
5695 FLAG_V = VFLAG_CLEAR;
\r
5696 FLAG_C = CFLAG_CLEAR;
\r
5700 M68KMAKE_OP(move, 16, ai, d)
\r
5702 uint res = MASK_OUT_ABOVE_16(DY);
\r
5703 uint ea = EA_AX_AI_16();
\r
5705 m68ki_write_16(ea, res);
\r
5707 FLAG_N = NFLAG_16(res);
\r
5709 FLAG_V = VFLAG_CLEAR;
\r
5710 FLAG_C = CFLAG_CLEAR;
\r
5714 M68KMAKE_OP(move, 16, ai, a)
\r
5716 uint res = MASK_OUT_ABOVE_16(AY);
\r
5717 uint ea = EA_AX_AI_16();
\r
5719 m68ki_write_16(ea, res);
\r
5721 FLAG_N = NFLAG_16(res);
\r
5723 FLAG_V = VFLAG_CLEAR;
\r
5724 FLAG_C = CFLAG_CLEAR;
\r
5728 M68KMAKE_OP(move, 16, ai, .)
\r
5730 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5731 uint ea = EA_AX_AI_16();
\r
5733 m68ki_write_16(ea, res);
\r
5735 FLAG_N = NFLAG_16(res);
\r
5737 FLAG_V = VFLAG_CLEAR;
\r
5738 FLAG_C = CFLAG_CLEAR;
\r
5742 M68KMAKE_OP(move, 16, pi, d)
\r
5744 uint res = MASK_OUT_ABOVE_16(DY);
\r
5745 uint ea = EA_AX_PI_16();
\r
5747 m68ki_write_16(ea, res);
\r
5749 FLAG_N = NFLAG_16(res);
\r
5751 FLAG_V = VFLAG_CLEAR;
\r
5752 FLAG_C = CFLAG_CLEAR;
\r
5756 M68KMAKE_OP(move, 16, pi, a)
\r
5758 uint res = MASK_OUT_ABOVE_16(AY);
\r
5759 uint ea = EA_AX_PI_16();
\r
5761 m68ki_write_16(ea, res);
\r
5763 FLAG_N = NFLAG_16(res);
\r
5765 FLAG_V = VFLAG_CLEAR;
\r
5766 FLAG_C = CFLAG_CLEAR;
\r
5770 M68KMAKE_OP(move, 16, pi, .)
\r
5772 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5773 uint ea = EA_AX_PI_16();
\r
5775 m68ki_write_16(ea, res);
\r
5777 FLAG_N = NFLAG_16(res);
\r
5779 FLAG_V = VFLAG_CLEAR;
\r
5780 FLAG_C = CFLAG_CLEAR;
\r
5784 M68KMAKE_OP(move, 16, pd, d)
\r
5786 uint res = MASK_OUT_ABOVE_16(DY);
\r
5787 uint ea = EA_AX_PD_16();
\r
5789 m68ki_write_16(ea, res);
\r
5791 FLAG_N = NFLAG_16(res);
\r
5793 FLAG_V = VFLAG_CLEAR;
\r
5794 FLAG_C = CFLAG_CLEAR;
\r
5798 M68KMAKE_OP(move, 16, pd, a)
\r
5800 uint res = MASK_OUT_ABOVE_16(AY);
\r
5801 uint ea = EA_AX_PD_16();
\r
5803 m68ki_write_16(ea, res);
\r
5805 FLAG_N = NFLAG_16(res);
\r
5807 FLAG_V = VFLAG_CLEAR;
\r
5808 FLAG_C = CFLAG_CLEAR;
\r
5812 M68KMAKE_OP(move, 16, pd, .)
\r
5814 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5815 uint ea = EA_AX_PD_16();
\r
5817 m68ki_write_16(ea, res);
\r
5819 FLAG_N = NFLAG_16(res);
\r
5821 FLAG_V = VFLAG_CLEAR;
\r
5822 FLAG_C = CFLAG_CLEAR;
\r
5826 M68KMAKE_OP(move, 16, di, d)
\r
5828 uint res = MASK_OUT_ABOVE_16(DY);
\r
5829 uint ea = EA_AX_DI_16();
\r
5831 m68ki_write_16(ea, res);
\r
5833 FLAG_N = NFLAG_16(res);
\r
5835 FLAG_V = VFLAG_CLEAR;
\r
5836 FLAG_C = CFLAG_CLEAR;
\r
5840 M68KMAKE_OP(move, 16, di, a)
\r
5842 uint res = MASK_OUT_ABOVE_16(AY);
\r
5843 uint ea = EA_AX_DI_16();
\r
5845 m68ki_write_16(ea, res);
\r
5847 FLAG_N = NFLAG_16(res);
\r
5849 FLAG_V = VFLAG_CLEAR;
\r
5850 FLAG_C = CFLAG_CLEAR;
\r
5854 M68KMAKE_OP(move, 16, di, .)
\r
5856 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5857 uint ea = EA_AX_DI_16();
\r
5859 m68ki_write_16(ea, res);
\r
5861 FLAG_N = NFLAG_16(res);
\r
5863 FLAG_V = VFLAG_CLEAR;
\r
5864 FLAG_C = CFLAG_CLEAR;
\r
5868 M68KMAKE_OP(move, 16, ix, d)
\r
5870 uint res = MASK_OUT_ABOVE_16(DY);
\r
5871 uint ea = EA_AX_IX_16();
\r
5873 m68ki_write_16(ea, res);
\r
5875 FLAG_N = NFLAG_16(res);
\r
5877 FLAG_V = VFLAG_CLEAR;
\r
5878 FLAG_C = CFLAG_CLEAR;
\r
5882 M68KMAKE_OP(move, 16, ix, a)
\r
5884 uint res = MASK_OUT_ABOVE_16(AY);
\r
5885 uint ea = EA_AX_IX_16();
\r
5887 m68ki_write_16(ea, res);
\r
5889 FLAG_N = NFLAG_16(res);
\r
5891 FLAG_V = VFLAG_CLEAR;
\r
5892 FLAG_C = CFLAG_CLEAR;
\r
5896 M68KMAKE_OP(move, 16, ix, .)
\r
5898 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5899 uint ea = EA_AX_IX_16();
\r
5901 m68ki_write_16(ea, res);
\r
5903 FLAG_N = NFLAG_16(res);
\r
5905 FLAG_V = VFLAG_CLEAR;
\r
5906 FLAG_C = CFLAG_CLEAR;
\r
5910 M68KMAKE_OP(move, 16, aw, d)
\r
5912 uint res = MASK_OUT_ABOVE_16(DY);
\r
5913 uint ea = EA_AW_16();
\r
5915 m68ki_write_16(ea, res);
\r
5917 FLAG_N = NFLAG_16(res);
\r
5919 FLAG_V = VFLAG_CLEAR;
\r
5920 FLAG_C = CFLAG_CLEAR;
\r
5924 M68KMAKE_OP(move, 16, aw, a)
\r
5926 uint res = MASK_OUT_ABOVE_16(AY);
\r
5927 uint ea = EA_AW_16();
\r
5929 m68ki_write_16(ea, res);
\r
5931 FLAG_N = NFLAG_16(res);
\r
5933 FLAG_V = VFLAG_CLEAR;
\r
5934 FLAG_C = CFLAG_CLEAR;
\r
5938 M68KMAKE_OP(move, 16, aw, .)
\r
5940 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5941 uint ea = EA_AW_16();
\r
5943 m68ki_write_16(ea, res);
\r
5945 FLAG_N = NFLAG_16(res);
\r
5947 FLAG_V = VFLAG_CLEAR;
\r
5948 FLAG_C = CFLAG_CLEAR;
\r
5952 M68KMAKE_OP(move, 16, al, d)
\r
5954 uint res = MASK_OUT_ABOVE_16(DY);
\r
5955 uint ea = EA_AL_16();
\r
5957 m68ki_write_16(ea, res);
\r
5959 FLAG_N = NFLAG_16(res);
\r
5961 FLAG_V = VFLAG_CLEAR;
\r
5962 FLAG_C = CFLAG_CLEAR;
\r
5966 M68KMAKE_OP(move, 16, al, a)
\r
5968 uint res = MASK_OUT_ABOVE_16(AY);
\r
5969 uint ea = EA_AL_16();
\r
5971 m68ki_write_16(ea, res);
\r
5973 FLAG_N = NFLAG_16(res);
\r
5975 FLAG_V = VFLAG_CLEAR;
\r
5976 FLAG_C = CFLAG_CLEAR;
\r
5980 M68KMAKE_OP(move, 16, al, .)
\r
5982 uint res = M68KMAKE_GET_OPER_AY_16;
\r
5983 uint ea = EA_AL_16();
\r
5985 m68ki_write_16(ea, res);
\r
5987 FLAG_N = NFLAG_16(res);
\r
5989 FLAG_V = VFLAG_CLEAR;
\r
5990 FLAG_C = CFLAG_CLEAR;
\r
5994 M68KMAKE_OP(move, 32, d, d)
\r
5997 uint* r_dst = &DX;
\r
6001 FLAG_N = NFLAG_32(res);
\r
6003 FLAG_V = VFLAG_CLEAR;
\r
6004 FLAG_C = CFLAG_CLEAR;
\r
6008 M68KMAKE_OP(move, 32, d, a)
\r
6011 uint* r_dst = &DX;
\r
6015 FLAG_N = NFLAG_32(res);
\r
6017 FLAG_V = VFLAG_CLEAR;
\r
6018 FLAG_C = CFLAG_CLEAR;
\r
6022 M68KMAKE_OP(move, 32, d, .)
\r
6024 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6025 uint* r_dst = &DX;
\r
6029 FLAG_N = NFLAG_32(res);
\r
6031 FLAG_V = VFLAG_CLEAR;
\r
6032 FLAG_C = CFLAG_CLEAR;
\r
6036 M68KMAKE_OP(move, 32, ai, d)
\r
6039 uint ea = EA_AX_AI_32();
\r
6041 m68ki_write_32(ea, res);
\r
6043 FLAG_N = NFLAG_32(res);
\r
6045 FLAG_V = VFLAG_CLEAR;
\r
6046 FLAG_C = CFLAG_CLEAR;
\r
6050 M68KMAKE_OP(move, 32, ai, a)
\r
6053 uint ea = EA_AX_AI_32();
\r
6055 m68ki_write_32(ea, res);
\r
6057 FLAG_N = NFLAG_32(res);
\r
6059 FLAG_V = VFLAG_CLEAR;
\r
6060 FLAG_C = CFLAG_CLEAR;
\r
6064 M68KMAKE_OP(move, 32, ai, .)
\r
6066 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6067 uint ea = EA_AX_AI_32();
\r
6069 m68ki_write_32(ea, res);
\r
6071 FLAG_N = NFLAG_32(res);
\r
6073 FLAG_V = VFLAG_CLEAR;
\r
6074 FLAG_C = CFLAG_CLEAR;
\r
6078 M68KMAKE_OP(move, 32, pi, d)
\r
6081 uint ea = EA_AX_PI_32();
\r
6083 m68ki_write_32(ea, res);
\r
6085 FLAG_N = NFLAG_32(res);
\r
6087 FLAG_V = VFLAG_CLEAR;
\r
6088 FLAG_C = CFLAG_CLEAR;
\r
6092 M68KMAKE_OP(move, 32, pi, a)
\r
6095 uint ea = EA_AX_PI_32();
\r
6097 m68ki_write_32(ea, res);
\r
6099 FLAG_N = NFLAG_32(res);
\r
6101 FLAG_V = VFLAG_CLEAR;
\r
6102 FLAG_C = CFLAG_CLEAR;
\r
6106 M68KMAKE_OP(move, 32, pi, .)
\r
6108 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6109 uint ea = EA_AX_PI_32();
\r
6111 m68ki_write_32(ea, res);
\r
6113 FLAG_N = NFLAG_32(res);
\r
6115 FLAG_V = VFLAG_CLEAR;
\r
6116 FLAG_C = CFLAG_CLEAR;
\r
6120 M68KMAKE_OP(move, 32, pd, d)
\r
6123 uint ea = EA_AX_PD_32();
\r
6125 m68ki_write_32(ea, res);
\r
6127 FLAG_N = NFLAG_32(res);
\r
6129 FLAG_V = VFLAG_CLEAR;
\r
6130 FLAG_C = CFLAG_CLEAR;
\r
6134 M68KMAKE_OP(move, 32, pd, a)
\r
6137 uint ea = EA_AX_PD_32();
\r
6139 m68ki_write_32(ea, res);
\r
6141 FLAG_N = NFLAG_32(res);
\r
6143 FLAG_V = VFLAG_CLEAR;
\r
6144 FLAG_C = CFLAG_CLEAR;
\r
6148 M68KMAKE_OP(move, 32, pd, .)
\r
6150 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6151 uint ea = EA_AX_PD_32();
\r
6153 m68ki_write_32(ea, res);
\r
6155 FLAG_N = NFLAG_32(res);
\r
6157 FLAG_V = VFLAG_CLEAR;
\r
6158 FLAG_C = CFLAG_CLEAR;
\r
6162 M68KMAKE_OP(move, 32, di, d)
\r
6165 uint ea = EA_AX_DI_32();
\r
6167 m68ki_write_32(ea, res);
\r
6169 FLAG_N = NFLAG_32(res);
\r
6171 FLAG_V = VFLAG_CLEAR;
\r
6172 FLAG_C = CFLAG_CLEAR;
\r
6176 M68KMAKE_OP(move, 32, di, a)
\r
6179 uint ea = EA_AX_DI_32();
\r
6181 m68ki_write_32(ea, res);
\r
6183 FLAG_N = NFLAG_32(res);
\r
6185 FLAG_V = VFLAG_CLEAR;
\r
6186 FLAG_C = CFLAG_CLEAR;
\r
6190 M68KMAKE_OP(move, 32, di, .)
\r
6192 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6193 uint ea = EA_AX_DI_32();
\r
6195 m68ki_write_32(ea, res);
\r
6197 FLAG_N = NFLAG_32(res);
\r
6199 FLAG_V = VFLAG_CLEAR;
\r
6200 FLAG_C = CFLAG_CLEAR;
\r
6204 M68KMAKE_OP(move, 32, ix, d)
\r
6207 uint ea = EA_AX_IX_32();
\r
6209 m68ki_write_32(ea, res);
\r
6211 FLAG_N = NFLAG_32(res);
\r
6213 FLAG_V = VFLAG_CLEAR;
\r
6214 FLAG_C = CFLAG_CLEAR;
\r
6218 M68KMAKE_OP(move, 32, ix, a)
\r
6221 uint ea = EA_AX_IX_32();
\r
6223 m68ki_write_32(ea, res);
\r
6225 FLAG_N = NFLAG_32(res);
\r
6227 FLAG_V = VFLAG_CLEAR;
\r
6228 FLAG_C = CFLAG_CLEAR;
\r
6232 M68KMAKE_OP(move, 32, ix, .)
\r
6234 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6235 uint ea = EA_AX_IX_32();
\r
6237 m68ki_write_32(ea, res);
\r
6239 FLAG_N = NFLAG_32(res);
\r
6241 FLAG_V = VFLAG_CLEAR;
\r
6242 FLAG_C = CFLAG_CLEAR;
\r
6246 M68KMAKE_OP(move, 32, aw, d)
\r
6249 uint ea = EA_AW_32();
\r
6251 m68ki_write_32(ea, res);
\r
6253 FLAG_N = NFLAG_32(res);
\r
6255 FLAG_V = VFLAG_CLEAR;
\r
6256 FLAG_C = CFLAG_CLEAR;
\r
6260 M68KMAKE_OP(move, 32, aw, a)
\r
6263 uint ea = EA_AW_32();
\r
6265 m68ki_write_32(ea, res);
\r
6267 FLAG_N = NFLAG_32(res);
\r
6269 FLAG_V = VFLAG_CLEAR;
\r
6270 FLAG_C = CFLAG_CLEAR;
\r
6274 M68KMAKE_OP(move, 32, aw, .)
\r
6276 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6277 uint ea = EA_AW_32();
\r
6279 m68ki_write_32(ea, res);
\r
6281 FLAG_N = NFLAG_32(res);
\r
6283 FLAG_V = VFLAG_CLEAR;
\r
6284 FLAG_C = CFLAG_CLEAR;
\r
6288 M68KMAKE_OP(move, 32, al, d)
\r
6291 uint ea = EA_AL_32();
\r
6293 m68ki_write_32(ea, res);
\r
6295 FLAG_N = NFLAG_32(res);
\r
6297 FLAG_V = VFLAG_CLEAR;
\r
6298 FLAG_C = CFLAG_CLEAR;
\r
6302 M68KMAKE_OP(move, 32, al, a)
\r
6305 uint ea = EA_AL_32();
\r
6307 m68ki_write_32(ea, res);
\r
6309 FLAG_N = NFLAG_32(res);
\r
6311 FLAG_V = VFLAG_CLEAR;
\r
6312 FLAG_C = CFLAG_CLEAR;
\r
6316 M68KMAKE_OP(move, 32, al, .)
\r
6318 uint res = M68KMAKE_GET_OPER_AY_32;
\r
6319 uint ea = EA_AL_32();
\r
6321 m68ki_write_32(ea, res);
\r
6323 FLAG_N = NFLAG_32(res);
\r
6325 FLAG_V = VFLAG_CLEAR;
\r
6326 FLAG_C = CFLAG_CLEAR;
\r
6330 M68KMAKE_OP(movea, 16, ., d)
\r
6332 AX = MAKE_INT_16(DY);
\r
6336 M68KMAKE_OP(movea, 16, ., a)
\r
6338 AX = MAKE_INT_16(AY);
\r
6342 M68KMAKE_OP(movea, 16, ., .)
\r
6344 AX = MAKE_INT_16(M68KMAKE_GET_OPER_AY_16);
\r
6348 M68KMAKE_OP(movea, 32, ., d)
\r
6354 M68KMAKE_OP(movea, 32, ., a)
\r
6360 M68KMAKE_OP(movea, 32, ., .)
\r
6362 AX = M68KMAKE_GET_OPER_AY_32;
\r
6366 M68KMAKE_OP(move, 16, frc, d)
\r
6368 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6370 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_ccr();
\r
6373 m68ki_exception_illegal();
\r
6377 M68KMAKE_OP(move, 16, frc, .)
\r
6379 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6381 m68ki_write_16(M68KMAKE_GET_EA_AY_16, m68ki_get_ccr());
\r
6384 m68ki_exception_illegal();
\r
6388 M68KMAKE_OP(move, 16, toc, d)
\r
6390 m68ki_set_ccr(DY);
\r
6394 M68KMAKE_OP(move, 16, toc, .)
\r
6396 m68ki_set_ccr(M68KMAKE_GET_OPER_AY_16);
\r
6400 M68KMAKE_OP(move, 16, frs, d)
\r
6402 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6404 DY = MASK_OUT_BELOW_16(DY) | m68ki_get_sr();
\r
6407 m68ki_exception_privilege_violation();
\r
6411 M68KMAKE_OP(move, 16, frs, .)
\r
6413 if(CPU_TYPE_IS_000(CPU_TYPE) || FLAG_S) /* NS990408 */
\r
6415 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6416 m68ki_write_16(ea, m68ki_get_sr());
\r
6419 m68ki_exception_privilege_violation();
\r
6423 M68KMAKE_OP(move, 16, tos, d)
\r
6430 m68ki_exception_privilege_violation();
\r
6434 M68KMAKE_OP(move, 16, tos, .)
\r
6438 uint new_sr = M68KMAKE_GET_OPER_AY_16;
\r
6439 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6440 m68ki_set_sr(new_sr);
\r
6443 m68ki_exception_privilege_violation();
\r
6447 M68KMAKE_OP(move, 32, fru, .)
\r
6454 m68ki_exception_privilege_violation();
\r
6458 M68KMAKE_OP(move, 32, tou, .)
\r
6462 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6466 m68ki_exception_privilege_violation();
\r
6470 M68KMAKE_OP(movec, 32, cr, .)
\r
6472 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6476 uint word2 = OPER_I_16();
\r
6478 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6479 switch (word2 & 0xfff)
\r
6481 case 0x000: /* SFC */
\r
6482 REG_DA[(word2 >> 12) & 15] = REG_SFC;
\r
6484 case 0x001: /* DFC */
\r
6485 REG_DA[(word2 >> 12) & 15] = REG_DFC;
\r
6487 case 0x002: /* CACR */
\r
6488 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6490 REG_DA[(word2 >> 12) & 15] = REG_CACR;
\r
6494 case 0x800: /* USP */
\r
6495 REG_DA[(word2 >> 12) & 15] = REG_USP;
\r
6497 case 0x801: /* VBR */
\r
6498 REG_DA[(word2 >> 12) & 15] = REG_VBR;
\r
6500 case 0x802: /* CAAR */
\r
6501 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6503 REG_DA[(word2 >> 12) & 15] = REG_CAAR;
\r
6506 m68ki_exception_illegal();
\r
6508 case 0x803: /* MSP */
\r
6509 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6511 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_SP : REG_MSP;
\r
6514 m68ki_exception_illegal();
\r
6516 case 0x804: /* ISP */
\r
6517 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6519 REG_DA[(word2 >> 12) & 15] = FLAG_M ? REG_ISP : REG_SP;
\r
6522 m68ki_exception_illegal();
\r
6525 m68ki_exception_illegal();
\r
6529 m68ki_exception_privilege_violation();
\r
6532 m68ki_exception_illegal();
\r
6536 M68KMAKE_OP(movec, 32, rc, .)
\r
6538 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6542 uint word2 = OPER_I_16();
\r
6544 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6545 switch (word2 & 0xfff)
\r
6547 case 0x000: /* SFC */
\r
6548 REG_SFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6550 case 0x001: /* DFC */
\r
6551 REG_DFC = REG_DA[(word2 >> 12) & 15] & 7;
\r
6553 case 0x002: /* CACR */
\r
6554 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6556 REG_CACR = REG_DA[(word2 >> 12) & 15];
\r
6559 m68ki_exception_illegal();
\r
6561 case 0x800: /* USP */
\r
6562 REG_USP = REG_DA[(word2 >> 12) & 15];
\r
6564 case 0x801: /* VBR */
\r
6565 REG_VBR = REG_DA[(word2 >> 12) & 15];
\r
6567 case 0x802: /* CAAR */
\r
6568 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6570 REG_CAAR = REG_DA[(word2 >> 12) & 15];
\r
6573 m68ki_exception_illegal();
\r
6575 case 0x803: /* MSP */
\r
6576 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6578 /* we are in supervisor mode so just check for M flag */
\r
6581 REG_MSP = REG_DA[(word2 >> 12) & 15];
\r
6584 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
6587 m68ki_exception_illegal();
\r
6589 case 0x804: /* ISP */
\r
6590 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6594 REG_SP = REG_DA[(word2 >> 12) & 15];
\r
6597 REG_ISP = REG_DA[(word2 >> 12) & 15];
\r
6600 m68ki_exception_illegal();
\r
6603 m68ki_exception_illegal();
\r
6607 m68ki_exception_privilege_violation();
\r
6610 m68ki_exception_illegal();
\r
6614 M68KMAKE_OP(movem, 16, re, pd)
\r
6617 uint register_list = OPER_I_16();
\r
6621 for(; i < 16; i++)
\r
6622 if(register_list & (1 << i))
\r
6625 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[15-i]));
\r
6630 USE_CYCLES(count<<CYC_MOVEM_W);
\r
6634 M68KMAKE_OP(movem, 16, re, .)
\r
6637 uint register_list = OPER_I_16();
\r
6638 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6641 for(; i < 16; i++)
\r
6642 if(register_list & (1 << i))
\r
6644 m68ki_write_16(ea, MASK_OUT_ABOVE_16(REG_DA[i]));
\r
6649 USE_CYCLES(count<<CYC_MOVEM_W);
\r
6653 M68KMAKE_OP(movem, 32, re, pd)
\r
6656 uint register_list = OPER_I_16();
\r
6660 for(; i < 16; i++)
\r
6661 if(register_list & (1 << i))
\r
6664 m68ki_write_32(ea, REG_DA[15-i]);
\r
6669 USE_CYCLES(count<<CYC_MOVEM_L);
\r
6673 M68KMAKE_OP(movem, 32, re, .)
\r
6676 uint register_list = OPER_I_16();
\r
6677 uint ea = M68KMAKE_GET_EA_AY_32;
\r
6680 for(; i < 16; i++)
\r
6681 if(register_list & (1 << i))
\r
6683 m68ki_write_32(ea, REG_DA[i]);
\r
6688 USE_CYCLES(count<<CYC_MOVEM_L);
\r
6692 M68KMAKE_OP(movem, 16, er, pi)
\r
6695 uint register_list = OPER_I_16();
\r
6699 for(; i < 16; i++)
\r
6700 if(register_list & (1 << i))
\r
6702 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
6708 USE_CYCLES(count<<CYC_MOVEM_W);
\r
6712 M68KMAKE_OP(movem, 16, er, .)
\r
6715 uint register_list = OPER_I_16();
\r
6716 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6719 for(; i < 16; i++)
\r
6720 if(register_list & (1 << i))
\r
6722 REG_DA[i] = MAKE_INT_16(MASK_OUT_ABOVE_16(m68ki_read_16(ea)));
\r
6727 USE_CYCLES(count<<CYC_MOVEM_W);
\r
6731 M68KMAKE_OP(movem, 32, er, pi)
\r
6734 uint register_list = OPER_I_16();
\r
6738 for(; i < 16; i++)
\r
6739 if(register_list & (1 << i))
\r
6741 REG_DA[i] = m68ki_read_32(ea);
\r
6747 USE_CYCLES(count<<CYC_MOVEM_L);
\r
6751 M68KMAKE_OP(movem, 32, er, .)
\r
6754 uint register_list = OPER_I_16();
\r
6755 uint ea = M68KMAKE_GET_EA_AY_32;
\r
6758 for(; i < 16; i++)
\r
6759 if(register_list & (1 << i))
\r
6761 REG_DA[i] = m68ki_read_32(ea);
\r
6766 USE_CYCLES(count<<CYC_MOVEM_L);
\r
6770 M68KMAKE_OP(movep, 16, re, .)
\r
6772 uint ea = EA_AY_DI_16();
\r
6775 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 8));
\r
6776 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
6780 M68KMAKE_OP(movep, 32, re, .)
\r
6782 uint ea = EA_AY_DI_32();
\r
6785 m68ki_write_8(ea, MASK_OUT_ABOVE_8(src >> 24));
\r
6786 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 16));
\r
6787 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src >> 8));
\r
6788 m68ki_write_8(ea += 2, MASK_OUT_ABOVE_8(src));
\r
6792 M68KMAKE_OP(movep, 16, er, .)
\r
6794 uint ea = EA_AY_DI_16();
\r
6795 uint* r_dst = &DX;
\r
6797 *r_dst = MASK_OUT_BELOW_16(*r_dst) | ((m68ki_read_8(ea) << 8) + m68ki_read_8(ea + 2));
\r
6801 M68KMAKE_OP(movep, 32, er, .)
\r
6803 uint ea = EA_AY_DI_32();
\r
6805 DX = (m68ki_read_8(ea) << 24) + (m68ki_read_8(ea + 2) << 16)
\r
6806 + (m68ki_read_8(ea + 4) << 8) + m68ki_read_8(ea + 6);
\r
6810 M68KMAKE_OP(moves, 8, ., .)
\r
6812 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6816 uint word2 = OPER_I_16();
\r
6817 uint ea = M68KMAKE_GET_EA_AY_8;
\r
6819 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6820 if(BIT_B(word2)) /* Register to memory */
\r
6822 m68ki_write_8_fc(ea, REG_DFC, MASK_OUT_ABOVE_8(REG_DA[(word2 >> 12) & 15]));
\r
6825 if(BIT_F(word2)) /* Memory to address register */
\r
6827 REG_A[(word2 >> 12) & 7] = MAKE_INT_8(m68ki_read_8_fc(ea, REG_SFC));
\r
6828 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
6832 /* Memory to data register */
\r
6833 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_8(REG_D[(word2 >> 12) & 7]) | m68ki_read_8_fc(ea, REG_SFC);
\r
6834 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
6838 m68ki_exception_privilege_violation();
\r
6841 m68ki_exception_illegal();
\r
6845 M68KMAKE_OP(moves, 16, ., .)
\r
6847 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6851 uint word2 = OPER_I_16();
\r
6852 uint ea = M68KMAKE_GET_EA_AY_16;
\r
6854 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6855 if(BIT_B(word2)) /* Register to memory */
\r
6857 m68ki_write_16_fc(ea, REG_DFC, MASK_OUT_ABOVE_16(REG_DA[(word2 >> 12) & 15]));
\r
6860 if(BIT_F(word2)) /* Memory to address register */
\r
6862 REG_A[(word2 >> 12) & 7] = MAKE_INT_16(m68ki_read_16_fc(ea, REG_SFC));
\r
6863 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
6867 /* Memory to data register */
\r
6868 REG_D[(word2 >> 12) & 7] = MASK_OUT_BELOW_16(REG_D[(word2 >> 12) & 7]) | m68ki_read_16_fc(ea, REG_SFC);
\r
6869 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
6873 m68ki_exception_privilege_violation();
\r
6876 m68ki_exception_illegal();
\r
6880 M68KMAKE_OP(moves, 32, ., .)
\r
6882 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
6886 uint word2 = OPER_I_16();
\r
6887 uint ea = M68KMAKE_GET_EA_AY_32;
\r
6889 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
6890 if(BIT_B(word2)) /* Register to memory */
\r
6892 m68ki_write_32_fc(ea, REG_DFC, REG_DA[(word2 >> 12) & 15]);
\r
6893 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
6897 /* Memory to register */
\r
6898 REG_DA[(word2 >> 12) & 15] = m68ki_read_32_fc(ea, REG_SFC);
\r
6899 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
6903 m68ki_exception_privilege_violation();
\r
6906 m68ki_exception_illegal();
\r
6910 M68KMAKE_OP(moveq, 32, ., .)
\r
6912 uint res = DX = MAKE_INT_8(MASK_OUT_ABOVE_8(REG_IR));
\r
6914 FLAG_N = NFLAG_32(res);
\r
6916 FLAG_V = VFLAG_CLEAR;
\r
6917 FLAG_C = CFLAG_CLEAR;
\r
6921 M68KMAKE_OP(muls, 16, ., d)
\r
6923 uint* r_dst = &DX;
\r
6924 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(DY) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
6929 FLAG_N = NFLAG_32(res);
\r
6930 FLAG_V = VFLAG_CLEAR;
\r
6931 FLAG_C = CFLAG_CLEAR;
\r
6935 M68KMAKE_OP(muls, 16, ., .)
\r
6937 uint* r_dst = &DX;
\r
6938 uint res = MASK_OUT_ABOVE_32(MAKE_INT_16(M68KMAKE_GET_OPER_AY_16) * MAKE_INT_16(MASK_OUT_ABOVE_16(*r_dst)));
\r
6943 FLAG_N = NFLAG_32(res);
\r
6944 FLAG_V = VFLAG_CLEAR;
\r
6945 FLAG_C = CFLAG_CLEAR;
\r
6949 M68KMAKE_OP(mulu, 16, ., d)
\r
6951 uint* r_dst = &DX;
\r
6952 uint res = MASK_OUT_ABOVE_16(DY) * MASK_OUT_ABOVE_16(*r_dst);
\r
6957 FLAG_N = NFLAG_32(res);
\r
6958 FLAG_V = VFLAG_CLEAR;
\r
6959 FLAG_C = CFLAG_CLEAR;
\r
6963 M68KMAKE_OP(mulu, 16, ., .)
\r
6965 uint* r_dst = &DX;
\r
6966 uint res = M68KMAKE_GET_OPER_AY_16 * MASK_OUT_ABOVE_16(*r_dst);
\r
6971 FLAG_N = NFLAG_32(res);
\r
6972 FLAG_V = VFLAG_CLEAR;
\r
6973 FLAG_C = CFLAG_CLEAR;
\r
6977 M68KMAKE_OP(mull, 32, ., d)
\r
6979 #if M68K_USE_64_BIT
\r
6981 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
6983 uint word2 = OPER_I_16();
\r
6985 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
6988 FLAG_C = CFLAG_CLEAR;
\r
6990 if(BIT_B(word2)) /* signed */
\r
6992 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
6995 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
6996 FLAG_N = NFLAG_32(res);
\r
6997 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
6998 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7001 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7002 FLAG_N = NFLAG_64(res);
\r
7003 FLAG_V = VFLAG_CLEAR;
\r
7004 REG_D[word2 & 7] = (res >> 32);
\r
7005 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7012 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7013 FLAG_N = NFLAG_32(res);
\r
7014 FLAG_V = (res > 0xffffffff)<<7;
\r
7015 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7018 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7019 FLAG_N = NFLAG_64(res);
\r
7020 FLAG_V = VFLAG_CLEAR;
\r
7021 REG_D[word2 & 7] = (res >> 32);
\r
7022 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7025 m68ki_exception_illegal();
\r
7029 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7031 uint word2 = OPER_I_16();
\r
7033 uint dst = REG_D[(word2 >> 12) & 7];
\r
7034 uint neg = GET_MSB_32(src ^ dst);
\r
7046 FLAG_C = CFLAG_CLEAR;
\r
7048 if(BIT_B(word2)) /* signed */
\r
7050 if(GET_MSB_32(src))
\r
7051 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7052 if(GET_MSB_32(dst))
\r
7053 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7056 src1 = MASK_OUT_ABOVE_16(src);
\r
7058 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7067 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7068 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7070 if(BIT_B(word2) && neg)
\r
7072 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7073 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7078 REG_D[word2 & 7] = hi;
\r
7079 REG_D[(word2 >> 12) & 7] = lo;
\r
7080 FLAG_N = NFLAG_32(hi);
\r
7082 FLAG_V = VFLAG_CLEAR;
\r
7086 REG_D[(word2 >> 12) & 7] = lo;
\r
7087 FLAG_N = NFLAG_32(lo);
\r
7090 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7092 FLAG_V = (hi != 0) << 7;
\r
7095 m68ki_exception_illegal();
\r
7101 M68KMAKE_OP(mull, 32, ., .)
\r
7103 #if M68K_USE_64_BIT
\r
7105 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7107 uint word2 = OPER_I_16();
\r
7108 uint64 src = M68KMAKE_GET_OPER_AY_32;
\r
7109 uint64 dst = REG_D[(word2 >> 12) & 7];
\r
7112 FLAG_C = CFLAG_CLEAR;
\r
7114 if(BIT_B(word2)) /* signed */
\r
7116 res = (sint64)((sint32)src) * (sint64)((sint32)dst);
\r
7119 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7120 FLAG_N = NFLAG_32(res);
\r
7121 FLAG_V = ((sint64)res != (sint32)res)<<7;
\r
7122 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7125 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7126 FLAG_N = NFLAG_64(res);
\r
7127 FLAG_V = VFLAG_CLEAR;
\r
7128 REG_D[word2 & 7] = (res >> 32);
\r
7129 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7136 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7137 FLAG_N = NFLAG_32(res);
\r
7138 FLAG_V = (res > 0xffffffff)<<7;
\r
7139 REG_D[(word2 >> 12) & 7] = FLAG_Z;
\r
7142 FLAG_Z = MASK_OUT_ABOVE_32(res) | (res>>32);
\r
7143 FLAG_N = NFLAG_64(res);
\r
7144 FLAG_V = VFLAG_CLEAR;
\r
7145 REG_D[word2 & 7] = (res >> 32);
\r
7146 REG_D[(word2 >> 12) & 7] = MASK_OUT_ABOVE_32(res);
\r
7149 m68ki_exception_illegal();
\r
7153 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7155 uint word2 = OPER_I_16();
\r
7156 uint src = M68KMAKE_GET_OPER_AY_32;
\r
7157 uint dst = REG_D[(word2 >> 12) & 7];
\r
7158 uint neg = GET_MSB_32(src ^ dst);
\r
7170 FLAG_C = CFLAG_CLEAR;
\r
7172 if(BIT_B(word2)) /* signed */
\r
7174 if(GET_MSB_32(src))
\r
7175 src = (uint)MASK_OUT_ABOVE_32(-(sint)src);
\r
7176 if(GET_MSB_32(dst))
\r
7177 dst = (uint)MASK_OUT_ABOVE_32(-(sint)dst);
\r
7180 src1 = MASK_OUT_ABOVE_16(src);
\r
7182 dst1 = MASK_OUT_ABOVE_16(dst);
\r
7191 lo = r1 + (MASK_OUT_ABOVE_16(r2)<<16) + (MASK_OUT_ABOVE_16(r3)<<16);
\r
7192 hi = r4 + (r2>>16) + (r3>>16) + (((r1>>16) + MASK_OUT_ABOVE_16(r2) + MASK_OUT_ABOVE_16(r3)) >> 16);
\r
7194 if(BIT_B(word2) && neg)
\r
7196 hi = (uint)MASK_OUT_ABOVE_32((-(sint)hi) - (lo != 0));
\r
7197 lo = (uint)MASK_OUT_ABOVE_32(-(sint)lo);
\r
7202 REG_D[word2 & 7] = hi;
\r
7203 REG_D[(word2 >> 12) & 7] = lo;
\r
7204 FLAG_N = NFLAG_32(hi);
\r
7206 FLAG_V = VFLAG_CLEAR;
\r
7210 REG_D[(word2 >> 12) & 7] = lo;
\r
7211 FLAG_N = NFLAG_32(lo);
\r
7214 FLAG_V = (!((GET_MSB_32(lo) && hi == 0xffffffff) || (!GET_MSB_32(lo) && !hi)))<<7;
\r
7216 FLAG_V = (hi != 0) << 7;
\r
7219 m68ki_exception_illegal();
\r
7225 M68KMAKE_OP(nbcd, 8, ., d)
\r
7227 uint* r_dst = &DY;
\r
7228 uint dst = *r_dst;
\r
7229 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7233 if((res & 0x0f) == 0xa)
\r
7234 res = (res & 0xf0) + 0x10;
\r
7236 res = MASK_OUT_ABOVE_8(res);
\r
7238 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7241 FLAG_C = CFLAG_SET;
\r
7242 FLAG_X = XFLAG_SET;
\r
7246 FLAG_C = CFLAG_CLEAR;
\r
7247 FLAG_X = XFLAG_CLEAR;
\r
7249 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
7253 M68KMAKE_OP(nbcd, 8, ., .)
\r
7255 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7256 uint dst = m68ki_read_8(ea);
\r
7257 uint res = MASK_OUT_ABOVE_8(0x9a - dst - XFLAG_AS_1());
\r
7261 if((res & 0x0f) == 0xa)
\r
7262 res = (res & 0xf0) + 0x10;
\r
7264 res = MASK_OUT_ABOVE_8(res);
\r
7266 m68ki_write_8(ea, MASK_OUT_ABOVE_8(res));
\r
7269 FLAG_C = CFLAG_SET;
\r
7270 FLAG_X = XFLAG_SET;
\r
7274 FLAG_C = CFLAG_CLEAR;
\r
7275 FLAG_X = XFLAG_CLEAR;
\r
7277 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
7281 M68KMAKE_OP(neg, 8, ., d)
\r
7283 uint* r_dst = &DY;
\r
7284 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst);
\r
7286 FLAG_N = NFLAG_8(res);
\r
7287 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7288 FLAG_V = *r_dst & res;
\r
7289 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7291 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
7295 M68KMAKE_OP(neg, 8, ., .)
\r
7297 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7298 uint src = m68ki_read_8(ea);
\r
7299 uint res = 0 - src;
\r
7301 FLAG_N = NFLAG_8(res);
\r
7302 FLAG_C = FLAG_X = CFLAG_8(res);
\r
7303 FLAG_V = src & res;
\r
7304 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
7306 m68ki_write_8(ea, FLAG_Z);
\r
7310 M68KMAKE_OP(neg, 16, ., d)
\r
7312 uint* r_dst = &DY;
\r
7313 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst);
\r
7315 FLAG_N = NFLAG_16(res);
\r
7316 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7317 FLAG_V = (*r_dst & res)>>8;
\r
7318 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7320 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
7324 M68KMAKE_OP(neg, 16, ., .)
\r
7326 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7327 uint src = m68ki_read_16(ea);
\r
7328 uint res = 0 - src;
\r
7330 FLAG_N = NFLAG_16(res);
\r
7331 FLAG_C = FLAG_X = CFLAG_16(res);
\r
7332 FLAG_V = (src & res)>>8;
\r
7333 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
7335 m68ki_write_16(ea, FLAG_Z);
\r
7339 M68KMAKE_OP(neg, 32, ., d)
\r
7341 uint* r_dst = &DY;
\r
7342 uint res = 0 - *r_dst;
\r
7344 FLAG_N = NFLAG_32(res);
\r
7345 FLAG_C = FLAG_X = CFLAG_SUB_32(*r_dst, 0, res);
\r
7346 FLAG_V = (*r_dst & res)>>24;
\r
7347 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7353 M68KMAKE_OP(neg, 32, ., .)
\r
7355 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7356 uint src = m68ki_read_32(ea);
\r
7357 uint res = 0 - src;
\r
7359 FLAG_N = NFLAG_32(res);
\r
7360 FLAG_C = FLAG_X = CFLAG_SUB_32(src, 0, res);
\r
7361 FLAG_V = (src & res)>>24;
\r
7362 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
7364 m68ki_write_32(ea, FLAG_Z);
\r
7368 M68KMAKE_OP(negx, 8, ., d)
\r
7370 uint* r_dst = &DY;
\r
7371 uint res = 0 - MASK_OUT_ABOVE_8(*r_dst) - XFLAG_AS_1();
\r
7373 FLAG_N = NFLAG_8(res);
\r
7374 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7375 FLAG_V = *r_dst & res;
\r
7377 res = MASK_OUT_ABOVE_8(res);
\r
7380 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7384 M68KMAKE_OP(negx, 8, ., .)
\r
7386 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7387 uint src = m68ki_read_8(ea);
\r
7388 uint res = 0 - src - XFLAG_AS_1();
\r
7390 FLAG_N = NFLAG_8(res);
\r
7391 FLAG_X = FLAG_C = CFLAG_8(res);
\r
7392 FLAG_V = src & res;
\r
7394 res = MASK_OUT_ABOVE_8(res);
\r
7397 m68ki_write_8(ea, res);
\r
7401 M68KMAKE_OP(negx, 16, ., d)
\r
7403 uint* r_dst = &DY;
\r
7404 uint res = 0 - MASK_OUT_ABOVE_16(*r_dst) - XFLAG_AS_1();
\r
7406 FLAG_N = NFLAG_16(res);
\r
7407 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7408 FLAG_V = (*r_dst & res)>>8;
\r
7410 res = MASK_OUT_ABOVE_16(res);
\r
7413 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
7417 M68KMAKE_OP(negx, 16, ., .)
\r
7419 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7420 uint src = m68ki_read_16(ea);
\r
7421 uint res = 0 - MASK_OUT_ABOVE_16(src) - XFLAG_AS_1();
\r
7423 FLAG_N = NFLAG_16(res);
\r
7424 FLAG_X = FLAG_C = CFLAG_16(res);
\r
7425 FLAG_V = (src & res)>>8;
\r
7427 res = MASK_OUT_ABOVE_16(res);
\r
7430 m68ki_write_16(ea, res);
\r
7434 M68KMAKE_OP(negx, 32, ., d)
\r
7436 uint* r_dst = &DY;
\r
7437 uint res = 0 - MASK_OUT_ABOVE_32(*r_dst) - XFLAG_AS_1();
\r
7439 FLAG_N = NFLAG_32(res);
\r
7440 FLAG_X = FLAG_C = CFLAG_SUB_32(*r_dst, 0, res);
\r
7441 FLAG_V = (*r_dst & res)>>24;
\r
7443 res = MASK_OUT_ABOVE_32(res);
\r
7450 M68KMAKE_OP(negx, 32, ., .)
\r
7452 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7453 uint src = m68ki_read_32(ea);
\r
7454 uint res = 0 - MASK_OUT_ABOVE_32(src) - XFLAG_AS_1();
\r
7456 FLAG_N = NFLAG_32(res);
\r
7457 FLAG_X = FLAG_C = CFLAG_SUB_32(src, 0, res);
\r
7458 FLAG_V = (src & res)>>24;
\r
7460 res = MASK_OUT_ABOVE_32(res);
\r
7463 m68ki_write_32(ea, res);
\r
7467 M68KMAKE_OP(nop, 0, ., .)
\r
7469 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7473 M68KMAKE_OP(not, 8, ., d)
\r
7475 uint* r_dst = &DY;
\r
7476 uint res = MASK_OUT_ABOVE_8(~*r_dst);
\r
7478 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7480 FLAG_N = NFLAG_8(res);
\r
7482 FLAG_C = CFLAG_CLEAR;
\r
7483 FLAG_V = VFLAG_CLEAR;
\r
7487 M68KMAKE_OP(not, 8, ., .)
\r
7489 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7490 uint res = MASK_OUT_ABOVE_8(~m68ki_read_8(ea));
\r
7492 m68ki_write_8(ea, res);
\r
7494 FLAG_N = NFLAG_8(res);
\r
7496 FLAG_C = CFLAG_CLEAR;
\r
7497 FLAG_V = VFLAG_CLEAR;
\r
7501 M68KMAKE_OP(not, 16, ., d)
\r
7503 uint* r_dst = &DY;
\r
7504 uint res = MASK_OUT_ABOVE_16(~*r_dst);
\r
7506 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
7508 FLAG_N = NFLAG_16(res);
\r
7510 FLAG_C = CFLAG_CLEAR;
\r
7511 FLAG_V = VFLAG_CLEAR;
\r
7515 M68KMAKE_OP(not, 16, ., .)
\r
7517 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7518 uint res = MASK_OUT_ABOVE_16(~m68ki_read_16(ea));
\r
7520 m68ki_write_16(ea, res);
\r
7522 FLAG_N = NFLAG_16(res);
\r
7524 FLAG_C = CFLAG_CLEAR;
\r
7525 FLAG_V = VFLAG_CLEAR;
\r
7529 M68KMAKE_OP(not, 32, ., d)
\r
7531 uint* r_dst = &DY;
\r
7532 uint res = *r_dst = MASK_OUT_ABOVE_32(~*r_dst);
\r
7534 FLAG_N = NFLAG_32(res);
\r
7536 FLAG_C = CFLAG_CLEAR;
\r
7537 FLAG_V = VFLAG_CLEAR;
\r
7541 M68KMAKE_OP(not, 32, ., .)
\r
7543 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7544 uint res = MASK_OUT_ABOVE_32(~m68ki_read_32(ea));
\r
7546 m68ki_write_32(ea, res);
\r
7548 FLAG_N = NFLAG_32(res);
\r
7550 FLAG_C = CFLAG_CLEAR;
\r
7551 FLAG_V = VFLAG_CLEAR;
\r
7555 M68KMAKE_OP(or, 8, er, d)
\r
7557 uint res = MASK_OUT_ABOVE_8((DX |= MASK_OUT_ABOVE_8(DY)));
\r
7559 FLAG_N = NFLAG_8(res);
\r
7561 FLAG_C = CFLAG_CLEAR;
\r
7562 FLAG_V = VFLAG_CLEAR;
\r
7566 M68KMAKE_OP(or, 8, er, .)
\r
7568 uint res = MASK_OUT_ABOVE_8((DX |= M68KMAKE_GET_OPER_AY_8));
\r
7570 FLAG_N = NFLAG_8(res);
\r
7572 FLAG_C = CFLAG_CLEAR;
\r
7573 FLAG_V = VFLAG_CLEAR;
\r
7577 M68KMAKE_OP(or, 16, er, d)
\r
7579 uint res = MASK_OUT_ABOVE_16((DX |= MASK_OUT_ABOVE_16(DY)));
\r
7581 FLAG_N = NFLAG_16(res);
\r
7583 FLAG_C = CFLAG_CLEAR;
\r
7584 FLAG_V = VFLAG_CLEAR;
\r
7588 M68KMAKE_OP(or, 16, er, .)
\r
7590 uint res = MASK_OUT_ABOVE_16((DX |= M68KMAKE_GET_OPER_AY_16));
\r
7592 FLAG_N = NFLAG_16(res);
\r
7594 FLAG_C = CFLAG_CLEAR;
\r
7595 FLAG_V = VFLAG_CLEAR;
\r
7599 M68KMAKE_OP(or, 32, er, d)
\r
7601 uint res = DX |= DY;
\r
7603 FLAG_N = NFLAG_32(res);
\r
7605 FLAG_C = CFLAG_CLEAR;
\r
7606 FLAG_V = VFLAG_CLEAR;
\r
7610 M68KMAKE_OP(or, 32, er, .)
\r
7612 uint res = DX |= M68KMAKE_GET_OPER_AY_32;
\r
7614 FLAG_N = NFLAG_32(res);
\r
7616 FLAG_C = CFLAG_CLEAR;
\r
7617 FLAG_V = VFLAG_CLEAR;
\r
7621 M68KMAKE_OP(or, 8, re, .)
\r
7623 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7624 uint res = MASK_OUT_ABOVE_8(DX | m68ki_read_8(ea));
\r
7626 m68ki_write_8(ea, res);
\r
7628 FLAG_N = NFLAG_8(res);
\r
7630 FLAG_C = CFLAG_CLEAR;
\r
7631 FLAG_V = VFLAG_CLEAR;
\r
7635 M68KMAKE_OP(or, 16, re, .)
\r
7637 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7638 uint res = MASK_OUT_ABOVE_16(DX | m68ki_read_16(ea));
\r
7640 m68ki_write_16(ea, res);
\r
7642 FLAG_N = NFLAG_16(res);
\r
7644 FLAG_C = CFLAG_CLEAR;
\r
7645 FLAG_V = VFLAG_CLEAR;
\r
7649 M68KMAKE_OP(or, 32, re, .)
\r
7651 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7652 uint res = DX | m68ki_read_32(ea);
\r
7654 m68ki_write_32(ea, res);
\r
7656 FLAG_N = NFLAG_32(res);
\r
7658 FLAG_C = CFLAG_CLEAR;
\r
7659 FLAG_V = VFLAG_CLEAR;
\r
7663 M68KMAKE_OP(ori, 8, ., d)
\r
7665 uint res = MASK_OUT_ABOVE_8((DY |= OPER_I_8()));
\r
7667 FLAG_N = NFLAG_8(res);
\r
7669 FLAG_C = CFLAG_CLEAR;
\r
7670 FLAG_V = VFLAG_CLEAR;
\r
7674 M68KMAKE_OP(ori, 8, ., .)
\r
7676 uint src = OPER_I_8();
\r
7677 uint ea = M68KMAKE_GET_EA_AY_8;
\r
7678 uint res = MASK_OUT_ABOVE_8(src | m68ki_read_8(ea));
\r
7680 m68ki_write_8(ea, res);
\r
7682 FLAG_N = NFLAG_8(res);
\r
7684 FLAG_C = CFLAG_CLEAR;
\r
7685 FLAG_V = VFLAG_CLEAR;
\r
7689 M68KMAKE_OP(ori, 16, ., d)
\r
7691 uint res = MASK_OUT_ABOVE_16(DY |= OPER_I_16());
\r
7693 FLAG_N = NFLAG_16(res);
\r
7695 FLAG_C = CFLAG_CLEAR;
\r
7696 FLAG_V = VFLAG_CLEAR;
\r
7700 M68KMAKE_OP(ori, 16, ., .)
\r
7702 uint src = OPER_I_16();
\r
7703 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7704 uint res = MASK_OUT_ABOVE_16(src | m68ki_read_16(ea));
\r
7706 m68ki_write_16(ea, res);
\r
7708 FLAG_N = NFLAG_16(res);
\r
7710 FLAG_C = CFLAG_CLEAR;
\r
7711 FLAG_V = VFLAG_CLEAR;
\r
7715 M68KMAKE_OP(ori, 32, ., d)
\r
7717 uint res = DY |= OPER_I_32();
\r
7719 FLAG_N = NFLAG_32(res);
\r
7721 FLAG_C = CFLAG_CLEAR;
\r
7722 FLAG_V = VFLAG_CLEAR;
\r
7726 M68KMAKE_OP(ori, 32, ., .)
\r
7728 uint src = OPER_I_32();
\r
7729 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7730 uint res = src | m68ki_read_32(ea);
\r
7732 m68ki_write_32(ea, res);
\r
7734 FLAG_N = NFLAG_32(res);
\r
7736 FLAG_C = CFLAG_CLEAR;
\r
7737 FLAG_V = VFLAG_CLEAR;
\r
7741 M68KMAKE_OP(ori, 16, toc, .)
\r
7743 m68ki_set_ccr(m68ki_get_ccr() | OPER_I_16());
\r
7747 M68KMAKE_OP(ori, 16, tos, .)
\r
7751 uint src = OPER_I_16();
\r
7752 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
7753 m68ki_set_sr(m68ki_get_sr() | src);
\r
7756 m68ki_exception_privilege_violation();
\r
7760 M68KMAKE_OP(pack, 16, rr, .)
\r
7762 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7764 /* Note: DX and DY are reversed in Motorola's docs */
\r
7765 uint src = DY + OPER_I_16();
\r
7766 uint* r_dst = &DX;
\r
7768 *r_dst = MASK_OUT_BELOW_8(*r_dst) | ((src >> 4) & 0x00f0) | (src & 0x000f);
\r
7771 m68ki_exception_illegal();
\r
7775 M68KMAKE_OP(pack, 16, mm, ax7)
\r
7777 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7779 /* Note: AX and AY are reversed in Motorola's docs */
\r
7780 uint ea_src = EA_AY_PD_8();
\r
7781 uint src = m68ki_read_8(ea_src);
\r
7782 ea_src = EA_AY_PD_8();
\r
7783 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
7785 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
7788 m68ki_exception_illegal();
\r
7792 M68KMAKE_OP(pack, 16, mm, ay7)
\r
7794 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7796 /* Note: AX and AY are reversed in Motorola's docs */
\r
7797 uint ea_src = EA_A7_PD_8();
\r
7798 uint src = m68ki_read_8(ea_src);
\r
7799 ea_src = EA_A7_PD_8();
\r
7800 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
7802 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
7805 m68ki_exception_illegal();
\r
7809 M68KMAKE_OP(pack, 16, mm, axy7)
\r
7811 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7813 uint ea_src = EA_A7_PD_8();
\r
7814 uint src = m68ki_read_8(ea_src);
\r
7815 ea_src = EA_A7_PD_8();
\r
7816 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
7818 m68ki_write_8(EA_A7_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
7821 m68ki_exception_illegal();
\r
7825 M68KMAKE_OP(pack, 16, mm, .)
\r
7827 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
7829 /* Note: AX and AY are reversed in Motorola's docs */
\r
7830 uint ea_src = EA_AY_PD_8();
\r
7831 uint src = m68ki_read_8(ea_src);
\r
7832 ea_src = EA_AY_PD_8();
\r
7833 src = ((src << 8) | m68ki_read_8(ea_src)) + OPER_I_16();
\r
7835 m68ki_write_8(EA_AX_PD_8(), ((src >> 4) & 0x00f0) | (src & 0x000f));
\r
7838 m68ki_exception_illegal();
\r
7842 M68KMAKE_OP(pea, 32, ., .)
\r
7844 uint ea = M68KMAKE_GET_EA_AY_32;
\r
7846 m68ki_push_32(ea);
\r
7850 M68KMAKE_OP(reset, 0, ., .)
\r
7854 m68ki_output_reset(); /* auto-disable (see m68kcpu.h) */
\r
7855 USE_CYCLES(CYC_RESET);
\r
7858 m68ki_exception_privilege_violation();
\r
7862 M68KMAKE_OP(ror, 8, s, .)
\r
7864 uint* r_dst = &DY;
\r
7865 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
7866 uint shift = orig_shift & 7;
\r
7867 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
7868 uint res = ROR_8(src, shift);
\r
7870 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7872 FLAG_N = NFLAG_8(res);
\r
7874 FLAG_C = src << (9-orig_shift);
\r
7875 FLAG_V = VFLAG_CLEAR;
\r
7879 M68KMAKE_OP(ror, 16, s, .)
\r
7881 uint* r_dst = &DY;
\r
7882 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
7883 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
7884 uint res = ROR_16(src, shift);
\r
7886 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
7888 FLAG_N = NFLAG_16(res);
\r
7890 FLAG_C = src << (9-shift);
\r
7891 FLAG_V = VFLAG_CLEAR;
\r
7895 M68KMAKE_OP(ror, 32, s, .)
\r
7897 uint* r_dst = &DY;
\r
7898 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
7899 uint64 src = *r_dst;
\r
7900 uint res = ROR_32(src, shift);
\r
7904 FLAG_N = NFLAG_32(res);
\r
7906 FLAG_C = src << (9-shift);
\r
7907 FLAG_V = VFLAG_CLEAR;
\r
7911 M68KMAKE_OP(ror, 8, r, .)
\r
7913 uint* r_dst = &DY;
\r
7914 uint orig_shift = DX & 0x3f;
\r
7915 uint shift = orig_shift & 7;
\r
7916 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
7917 uint res = ROR_8(src, shift);
\r
7919 if(orig_shift != 0)
\r
7921 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
7923 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
7924 FLAG_C = src << (8-((shift-1)&7));
\r
7925 FLAG_N = NFLAG_8(res);
\r
7927 FLAG_V = VFLAG_CLEAR;
\r
7931 FLAG_C = CFLAG_CLEAR;
\r
7932 FLAG_N = NFLAG_8(src);
\r
7934 FLAG_V = VFLAG_CLEAR;
\r
7938 M68KMAKE_OP(ror, 16, r, .)
\r
7940 uint* r_dst = &DY;
\r
7941 uint orig_shift = DX & 0x3f;
\r
7942 uint shift = orig_shift & 15;
\r
7943 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
7944 uint res = ROR_16(src, shift);
\r
7946 if(orig_shift != 0)
\r
7948 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
7950 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
7951 FLAG_C = (src >> ((shift - 1) & 15)) << 8;
\r
7952 FLAG_N = NFLAG_16(res);
\r
7954 FLAG_V = VFLAG_CLEAR;
\r
7958 FLAG_C = CFLAG_CLEAR;
\r
7959 FLAG_N = NFLAG_16(src);
\r
7961 FLAG_V = VFLAG_CLEAR;
\r
7965 M68KMAKE_OP(ror, 32, r, .)
\r
7967 uint* r_dst = &DY;
\r
7968 uint orig_shift = DX & 0x3f;
\r
7969 uint shift = orig_shift & 31;
\r
7970 uint64 src = *r_dst;
\r
7971 uint res = ROR_32(src, shift);
\r
7973 if(orig_shift != 0)
\r
7975 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
7978 FLAG_C = (src >> ((shift - 1) & 31)) << 8;
\r
7979 FLAG_N = NFLAG_32(res);
\r
7981 FLAG_V = VFLAG_CLEAR;
\r
7985 FLAG_C = CFLAG_CLEAR;
\r
7986 FLAG_N = NFLAG_32(src);
\r
7988 FLAG_V = VFLAG_CLEAR;
\r
7992 M68KMAKE_OP(ror, 16, ., .)
\r
7994 uint ea = M68KMAKE_GET_EA_AY_16;
\r
7995 uint src = m68ki_read_16(ea);
\r
7996 uint res = ROR_16(src, 1);
\r
7998 m68ki_write_16(ea, res);
\r
8000 FLAG_N = NFLAG_16(res);
\r
8002 FLAG_C = src << 8;
\r
8003 FLAG_V = VFLAG_CLEAR;
\r
8007 M68KMAKE_OP(rol, 8, s, .)
\r
8009 uint* r_dst = &DY;
\r
8010 uint orig_shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8011 uint shift = orig_shift & 7;
\r
8012 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8013 uint res = ROL_8(src, shift);
\r
8015 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8017 FLAG_N = NFLAG_8(res);
\r
8019 FLAG_C = src << orig_shift;
\r
8020 FLAG_V = VFLAG_CLEAR;
\r
8024 M68KMAKE_OP(rol, 16, s, .)
\r
8026 uint* r_dst = &DY;
\r
8027 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8028 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8029 uint res = ROL_16(src, shift);
\r
8031 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8033 FLAG_N = NFLAG_16(res);
\r
8035 FLAG_C = src >> (8-shift);
\r
8036 FLAG_V = VFLAG_CLEAR;
\r
8040 M68KMAKE_OP(rol, 32, s, .)
\r
8042 uint* r_dst = &DY;
\r
8043 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8044 uint64 src = *r_dst;
\r
8045 uint res = ROL_32(src, shift);
\r
8049 FLAG_N = NFLAG_32(res);
\r
8051 FLAG_C = src >> (24-shift);
\r
8052 FLAG_V = VFLAG_CLEAR;
\r
8056 M68KMAKE_OP(rol, 8, r, .)
\r
8058 uint* r_dst = &DY;
\r
8059 uint orig_shift = DX & 0x3f;
\r
8060 uint shift = orig_shift & 7;
\r
8061 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8062 uint res = ROL_8(src, shift);
\r
8064 if(orig_shift != 0)
\r
8066 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8070 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8071 FLAG_C = src << shift;
\r
8072 FLAG_N = NFLAG_8(res);
\r
8074 FLAG_V = VFLAG_CLEAR;
\r
8077 FLAG_C = (src & 1)<<8;
\r
8078 FLAG_N = NFLAG_8(src);
\r
8080 FLAG_V = VFLAG_CLEAR;
\r
8084 FLAG_C = CFLAG_CLEAR;
\r
8085 FLAG_N = NFLAG_8(src);
\r
8087 FLAG_V = VFLAG_CLEAR;
\r
8091 M68KMAKE_OP(rol, 16, r, .)
\r
8093 uint* r_dst = &DY;
\r
8094 uint orig_shift = DX & 0x3f;
\r
8095 uint shift = orig_shift & 15;
\r
8096 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8097 uint res = MASK_OUT_ABOVE_16(ROL_16(src, shift));
\r
8099 if(orig_shift != 0)
\r
8101 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8105 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8106 FLAG_C = (src << shift) >> 8;
\r
8107 FLAG_N = NFLAG_16(res);
\r
8109 FLAG_V = VFLAG_CLEAR;
\r
8112 FLAG_C = (src & 1)<<8;
\r
8113 FLAG_N = NFLAG_16(src);
\r
8115 FLAG_V = VFLAG_CLEAR;
\r
8119 FLAG_C = CFLAG_CLEAR;
\r
8120 FLAG_N = NFLAG_16(src);
\r
8122 FLAG_V = VFLAG_CLEAR;
\r
8126 M68KMAKE_OP(rol, 32, r, .)
\r
8128 uint* r_dst = &DY;
\r
8129 uint orig_shift = DX & 0x3f;
\r
8130 uint shift = orig_shift & 31;
\r
8131 uint64 src = *r_dst;
\r
8132 uint res = ROL_32(src, shift);
\r
8134 if(orig_shift != 0)
\r
8136 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8140 FLAG_C = (src >> (32 - shift)) << 8;
\r
8141 FLAG_N = NFLAG_32(res);
\r
8143 FLAG_V = VFLAG_CLEAR;
\r
8147 FLAG_C = CFLAG_CLEAR;
\r
8148 FLAG_N = NFLAG_32(src);
\r
8150 FLAG_V = VFLAG_CLEAR;
\r
8154 M68KMAKE_OP(rol, 16, ., .)
\r
8156 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8157 uint src = m68ki_read_16(ea);
\r
8158 uint res = MASK_OUT_ABOVE_16(ROL_16(src, 1));
\r
8160 m68ki_write_16(ea, res);
\r
8162 FLAG_N = NFLAG_16(res);
\r
8164 FLAG_C = src >> 7;
\r
8165 FLAG_V = VFLAG_CLEAR;
\r
8169 M68KMAKE_OP(roxr, 8, s, .)
\r
8171 uint* r_dst = &DY;
\r
8172 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8173 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8174 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8176 FLAG_C = FLAG_X = res;
\r
8177 res = MASK_OUT_ABOVE_8(res);
\r
8179 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8181 FLAG_N = NFLAG_8(res);
\r
8183 FLAG_V = VFLAG_CLEAR;
\r
8187 M68KMAKE_OP(roxr, 16, s, .)
\r
8189 uint* r_dst = &DY;
\r
8190 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8191 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8192 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8194 FLAG_C = FLAG_X = res >> 8;
\r
8195 res = MASK_OUT_ABOVE_16(res);
\r
8197 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8199 FLAG_N = NFLAG_16(res);
\r
8201 FLAG_V = VFLAG_CLEAR;
\r
8205 M68KMAKE_OP(roxr, 32, s, .)
\r
8207 #if M68K_USE_64_BIT
\r
8209 uint* r_dst = &DY;
\r
8210 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8211 uint64 src = *r_dst;
\r
8212 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8214 res = ROR_33_64(res, shift);
\r
8216 FLAG_C = FLAG_X = res >> 24;
\r
8217 res = MASK_OUT_ABOVE_32(res);
\r
8221 FLAG_N = NFLAG_32(res);
\r
8223 FLAG_V = VFLAG_CLEAR;
\r
8227 uint* r_dst = &DY;
\r
8228 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8229 uint src = *r_dst;
\r
8230 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8231 uint new_x_flag = src & (1 << (shift - 1));
\r
8235 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
8236 FLAG_N = NFLAG_32(res);
\r
8238 FLAG_V = VFLAG_CLEAR;
\r
8244 M68KMAKE_OP(roxr, 8, r, .)
\r
8246 uint* r_dst = &DY;
\r
8247 uint orig_shift = DX & 0x3f;
\r
8249 if(orig_shift != 0)
\r
8251 uint shift = orig_shift % 9;
\r
8252 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8253 uint res = ROR_9(src | (XFLAG_AS_1() << 8), shift);
\r
8255 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8257 FLAG_C = FLAG_X = res;
\r
8258 res = MASK_OUT_ABOVE_8(res);
\r
8260 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8261 FLAG_N = NFLAG_8(res);
\r
8263 FLAG_V = VFLAG_CLEAR;
\r
8268 FLAG_N = NFLAG_8(*r_dst);
\r
8269 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
8270 FLAG_V = VFLAG_CLEAR;
\r
8274 M68KMAKE_OP(roxr, 16, r, .)
\r
8276 uint* r_dst = &DY;
\r
8277 uint orig_shift = DX & 0x3f;
\r
8279 if(orig_shift != 0)
\r
8281 uint shift = orig_shift % 17;
\r
8282 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8283 uint res = ROR_17(src | (XFLAG_AS_1() << 16), shift);
\r
8285 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8287 FLAG_C = FLAG_X = res >> 8;
\r
8288 res = MASK_OUT_ABOVE_16(res);
\r
8290 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8291 FLAG_N = NFLAG_16(res);
\r
8293 FLAG_V = VFLAG_CLEAR;
\r
8298 FLAG_N = NFLAG_16(*r_dst);
\r
8299 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
8300 FLAG_V = VFLAG_CLEAR;
\r
8304 M68KMAKE_OP(roxr, 32, r, .)
\r
8306 #if M68K_USE_64_BIT
\r
8308 uint* r_dst = &DY;
\r
8309 uint orig_shift = DX & 0x3f;
\r
8311 if(orig_shift != 0)
\r
8313 uint shift = orig_shift % 33;
\r
8314 uint64 src = *r_dst;
\r
8315 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8317 res = ROR_33_64(res, shift);
\r
8319 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8321 FLAG_C = FLAG_X = res >> 24;
\r
8322 res = MASK_OUT_ABOVE_32(res);
\r
8325 FLAG_N = NFLAG_32(res);
\r
8327 FLAG_V = VFLAG_CLEAR;
\r
8332 FLAG_N = NFLAG_32(*r_dst);
\r
8334 FLAG_V = VFLAG_CLEAR;
\r
8338 uint* r_dst = &DY;
\r
8339 uint orig_shift = DX & 0x3f;
\r
8340 uint shift = orig_shift % 33;
\r
8341 uint src = *r_dst;
\r
8342 uint res = MASK_OUT_ABOVE_32((ROR_33(src, shift) & ~(1 << (32 - shift))) | (XFLAG_AS_1() << (32 - shift)));
\r
8343 uint new_x_flag = src & (1 << (shift - 1));
\r
8345 if(orig_shift != 0)
\r
8346 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8351 FLAG_X = (new_x_flag != 0)<<8;
\r
8356 FLAG_N = NFLAG_32(res);
\r
8358 FLAG_V = VFLAG_CLEAR;
\r
8364 M68KMAKE_OP(roxr, 16, ., .)
\r
8366 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8367 uint src = m68ki_read_16(ea);
\r
8368 uint res = ROR_17(src | (XFLAG_AS_1() << 16), 1);
\r
8370 FLAG_C = FLAG_X = res >> 8;
\r
8371 res = MASK_OUT_ABOVE_16(res);
\r
8373 m68ki_write_16(ea, res);
\r
8375 FLAG_N = NFLAG_16(res);
\r
8377 FLAG_V = VFLAG_CLEAR;
\r
8381 M68KMAKE_OP(roxl, 8, s, .)
\r
8383 uint* r_dst = &DY;
\r
8384 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8385 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8386 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
8388 FLAG_C = FLAG_X = res;
\r
8389 res = MASK_OUT_ABOVE_8(res);
\r
8391 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8393 FLAG_N = NFLAG_8(res);
\r
8395 FLAG_V = VFLAG_CLEAR;
\r
8399 M68KMAKE_OP(roxl, 16, s, .)
\r
8401 uint* r_dst = &DY;
\r
8402 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8403 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8404 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
8406 FLAG_C = FLAG_X = res >> 8;
\r
8407 res = MASK_OUT_ABOVE_16(res);
\r
8409 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8411 FLAG_N = NFLAG_16(res);
\r
8413 FLAG_V = VFLAG_CLEAR;
\r
8417 M68KMAKE_OP(roxl, 32, s, .)
\r
8419 #if M68K_USE_64_BIT
\r
8421 uint* r_dst = &DY;
\r
8422 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8423 uint64 src = *r_dst;
\r
8424 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8426 res = ROL_33_64(res, shift);
\r
8428 FLAG_C = FLAG_X = res >> 24;
\r
8429 res = MASK_OUT_ABOVE_32(res);
\r
8433 FLAG_N = NFLAG_32(res);
\r
8435 FLAG_V = VFLAG_CLEAR;
\r
8439 uint* r_dst = &DY;
\r
8440 uint shift = (((REG_IR >> 9) - 1) & 7) + 1;
\r
8441 uint src = *r_dst;
\r
8442 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
8443 uint new_x_flag = src & (1 << (32 - shift));
\r
8447 FLAG_C = FLAG_X = (new_x_flag != 0)<<8;
\r
8448 FLAG_N = NFLAG_32(res);
\r
8450 FLAG_V = VFLAG_CLEAR;
\r
8456 M68KMAKE_OP(roxl, 8, r, .)
\r
8458 uint* r_dst = &DY;
\r
8459 uint orig_shift = DX & 0x3f;
\r
8462 if(orig_shift != 0)
\r
8464 uint shift = orig_shift % 9;
\r
8465 uint src = MASK_OUT_ABOVE_8(*r_dst);
\r
8466 uint res = ROL_9(src | (XFLAG_AS_1() << 8), shift);
\r
8468 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8470 FLAG_C = FLAG_X = res;
\r
8471 res = MASK_OUT_ABOVE_8(res);
\r
8473 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8474 FLAG_N = NFLAG_8(res);
\r
8476 FLAG_V = VFLAG_CLEAR;
\r
8481 FLAG_N = NFLAG_8(*r_dst);
\r
8482 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
8483 FLAG_V = VFLAG_CLEAR;
\r
8487 M68KMAKE_OP(roxl, 16, r, .)
\r
8489 uint* r_dst = &DY;
\r
8490 uint orig_shift = DX & 0x3f;
\r
8492 if(orig_shift != 0)
\r
8494 uint shift = orig_shift % 17;
\r
8495 uint src = MASK_OUT_ABOVE_16(*r_dst);
\r
8496 uint res = ROL_17(src | (XFLAG_AS_1() << 16), shift);
\r
8498 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8500 FLAG_C = FLAG_X = res >> 8;
\r
8501 res = MASK_OUT_ABOVE_16(res);
\r
8503 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
8504 FLAG_N = NFLAG_16(res);
\r
8506 FLAG_V = VFLAG_CLEAR;
\r
8511 FLAG_N = NFLAG_16(*r_dst);
\r
8512 FLAG_Z = MASK_OUT_ABOVE_16(*r_dst);
\r
8513 FLAG_V = VFLAG_CLEAR;
\r
8517 M68KMAKE_OP(roxl, 32, r, .)
\r
8519 #if M68K_USE_64_BIT
\r
8521 uint* r_dst = &DY;
\r
8522 uint orig_shift = DX & 0x3f;
\r
8524 if(orig_shift != 0)
\r
8526 uint shift = orig_shift % 33;
\r
8527 uint64 src = *r_dst;
\r
8528 uint64 res = src | (((uint64)XFLAG_AS_1()) << 32);
\r
8530 res = ROL_33_64(res, shift);
\r
8532 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8534 FLAG_C = FLAG_X = res >> 24;
\r
8535 res = MASK_OUT_ABOVE_32(res);
\r
8538 FLAG_N = NFLAG_32(res);
\r
8540 FLAG_V = VFLAG_CLEAR;
\r
8545 FLAG_N = NFLAG_32(*r_dst);
\r
8547 FLAG_V = VFLAG_CLEAR;
\r
8551 uint* r_dst = &DY;
\r
8552 uint orig_shift = DX & 0x3f;
\r
8553 uint shift = orig_shift % 33;
\r
8554 uint src = *r_dst;
\r
8555 uint res = MASK_OUT_ABOVE_32((ROL_33(src, shift) & ~(1 << (shift - 1))) | (XFLAG_AS_1() << (shift - 1)));
\r
8556 uint new_x_flag = src & (1 << (32 - shift));
\r
8558 if(orig_shift != 0)
\r
8559 USE_CYCLES(orig_shift<<CYC_SHIFT);
\r
8564 FLAG_X = (new_x_flag != 0)<<8;
\r
8569 FLAG_N = NFLAG_32(res);
\r
8571 FLAG_V = VFLAG_CLEAR;
\r
8577 M68KMAKE_OP(roxl, 16, ., .)
\r
8579 uint ea = M68KMAKE_GET_EA_AY_16;
\r
8580 uint src = m68ki_read_16(ea);
\r
8581 uint res = ROL_17(src | (XFLAG_AS_1() << 16), 1);
\r
8583 FLAG_C = FLAG_X = res >> 8;
\r
8584 res = MASK_OUT_ABOVE_16(res);
\r
8586 m68ki_write_16(ea, res);
\r
8588 FLAG_N = NFLAG_16(res);
\r
8590 FLAG_V = VFLAG_CLEAR;
\r
8594 M68KMAKE_OP(rtd, 32, ., .)
\r
8596 if(CPU_TYPE_IS_010_PLUS(CPU_TYPE))
\r
8598 uint new_pc = m68ki_pull_32();
\r
8600 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8601 REG_A[7] = MASK_OUT_ABOVE_32(REG_A[7] + MAKE_INT_16(OPER_I_16()));
\r
8602 m68ki_jump(new_pc);
\r
8605 m68ki_exception_illegal();
\r
8609 M68KMAKE_OP(rte, 32, ., .)
\r
8617 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8619 if(CPU_TYPE_IS_000(CPU_TYPE))
\r
8621 new_sr = m68ki_pull_16();
\r
8622 new_pc = m68ki_pull_32();
\r
8623 m68ki_jump(new_pc);
\r
8624 m68ki_set_sr(new_sr);
\r
8628 if(CPU_TYPE_IS_010(CPU_TYPE))
\r
8630 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
8631 if(format_word == 0)
\r
8633 new_sr = m68ki_pull_16();
\r
8634 new_pc = m68ki_pull_32();
\r
8635 m68ki_fake_pull_16(); /* format word */
\r
8636 m68ki_jump(new_pc);
\r
8637 m68ki_set_sr(new_sr);
\r
8640 /* Not handling bus fault (9) */
\r
8641 m68ki_exception_format_error();
\r
8645 /* Otherwise it's 020 */
\r
8647 format_word = m68ki_read_16(REG_A[7]+6) >> 12;
\r
8648 switch(format_word)
\r
8650 case 0: /* Normal */
\r
8651 new_sr = m68ki_pull_16();
\r
8652 new_pc = m68ki_pull_32();
\r
8653 m68ki_fake_pull_16(); /* format word */
\r
8654 m68ki_jump(new_pc);
\r
8655 m68ki_set_sr(new_sr);
\r
8657 case 1: /* Throwaway */
\r
8658 new_sr = m68ki_pull_16();
\r
8659 m68ki_fake_pull_32(); /* program counter */
\r
8660 m68ki_fake_pull_16(); /* format word */
\r
8661 m68ki_set_sr_noint(new_sr);
\r
8663 case 2: /* Trap */
\r
8664 new_sr = m68ki_pull_16();
\r
8665 new_pc = m68ki_pull_32();
\r
8666 m68ki_fake_pull_16(); /* format word */
\r
8667 m68ki_fake_pull_32(); /* address */
\r
8668 m68ki_jump(new_pc);
\r
8669 m68ki_set_sr(new_sr);
\r
8672 /* Not handling long or short bus fault */
\r
8673 m68ki_exception_format_error();
\r
8676 m68ki_exception_privilege_violation();
\r
8680 M68KMAKE_OP(rtm, 32, ., .)
\r
8682 if(CPU_TYPE_IS_020_VARIANT(CPU_TYPE))
\r
8684 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8685 M68K_DO_LOG((M68K_LOG_FILEHANDLE "%s at %08x: called unimplemented instruction %04x (%s)\n",
\r
8686 m68ki_cpu_names[CPU_TYPE], ADDRESS_68K(REG_PC - 2), REG_IR,
\r
8687 m68k_disassemble_quick(ADDRESS_68K(REG_PC - 2))));
\r
8690 m68ki_exception_illegal();
\r
8694 M68KMAKE_OP(rtr, 32, ., .)
\r
8696 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8697 m68ki_set_ccr(m68ki_pull_16());
\r
8698 m68ki_jump(m68ki_pull_32());
\r
8702 M68KMAKE_OP(rts, 32, ., .)
\r
8704 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8705 m68ki_jump(m68ki_pull_32());
\r
8709 M68KMAKE_OP(sbcd, 8, rr, .)
\r
8711 uint* r_dst = &DX;
\r
8713 uint dst = *r_dst;
\r
8714 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
8718 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
8719 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
8723 res = MASK_OUT_ABOVE_8(res);
\r
8725 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
8728 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
8732 M68KMAKE_OP(sbcd, 8, mm, ax7)
\r
8734 uint src = OPER_AY_PD_8();
\r
8735 uint ea = EA_A7_PD_8();
\r
8736 uint dst = m68ki_read_8(ea);
\r
8737 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
8741 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
8742 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
8746 res = MASK_OUT_ABOVE_8(res);
\r
8748 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
8751 m68ki_write_8(ea, res);
\r
8755 M68KMAKE_OP(sbcd, 8, mm, ay7)
\r
8757 uint src = OPER_A7_PD_8();
\r
8758 uint ea = EA_AX_PD_8();
\r
8759 uint dst = m68ki_read_8(ea);
\r
8760 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
8764 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
8765 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
8769 res = MASK_OUT_ABOVE_8(res);
\r
8771 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
8774 m68ki_write_8(ea, res);
\r
8778 M68KMAKE_OP(sbcd, 8, mm, axy7)
\r
8780 uint src = OPER_A7_PD_8();
\r
8781 uint ea = EA_A7_PD_8();
\r
8782 uint dst = m68ki_read_8(ea);
\r
8783 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
8787 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
8788 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
8792 res = MASK_OUT_ABOVE_8(res);
\r
8794 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
8797 m68ki_write_8(ea, res);
\r
8801 M68KMAKE_OP(sbcd, 8, mm, .)
\r
8803 uint src = OPER_AY_PD_8();
\r
8804 uint ea = EA_AX_PD_8();
\r
8805 uint dst = m68ki_read_8(ea);
\r
8806 uint res = LOW_NIBBLE(dst) - LOW_NIBBLE(src) - XFLAG_AS_1();
\r
8810 res += HIGH_NIBBLE(dst) - HIGH_NIBBLE(src);
\r
8811 FLAG_X = FLAG_C = (res > 0x99) << 8;
\r
8815 res = MASK_OUT_ABOVE_8(res);
\r
8817 FLAG_N = NFLAG_8(res); /* officially undefined */
\r
8820 m68ki_write_8(ea, res);
\r
8824 M68KMAKE_OP(st, 8, ., d)
\r
8830 M68KMAKE_OP(st, 8, ., .)
\r
8832 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0xff);
\r
8836 M68KMAKE_OP(sf, 8, ., d)
\r
8842 M68KMAKE_OP(sf, 8, ., .)
\r
8844 m68ki_write_8(M68KMAKE_GET_EA_AY_8, 0);
\r
8848 M68KMAKE_OP(scc, 8, ., d)
\r
8859 M68KMAKE_OP(scc, 8, ., .)
\r
8861 m68ki_write_8(M68KMAKE_GET_EA_AY_8, M68KMAKE_CC ? 0xff : 0);
\r
8865 M68KMAKE_OP(stop, 0, ., .)
\r
8869 uint new_sr = OPER_I_16();
\r
8870 m68ki_trace_t0(); /* auto-disable (see m68kcpu.h) */
\r
8871 CPU_STOPPED |= STOP_LEVEL_STOP;
\r
8872 m68ki_set_sr(new_sr);
\r
8873 m68ki_remaining_cycles = 0;
\r
8876 m68ki_exception_privilege_violation();
\r
8880 M68KMAKE_OP(sub, 8, er, d)
\r
8882 uint* r_dst = &DX;
\r
8883 uint src = MASK_OUT_ABOVE_8(DY);
\r
8884 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
8885 uint res = dst - src;
\r
8887 FLAG_N = NFLAG_8(res);
\r
8888 FLAG_X = FLAG_C = CFLAG_8(res);
\r
8889 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
8890 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
8892 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
8896 M68KMAKE_OP(sub, 8, er, .)
\r
8898 uint* r_dst = &DX;
\r
8899 uint src = M68KMAKE_GET_OPER_AY_8;
\r
8900 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
8901 uint res = dst - src;
\r
8903 FLAG_N = NFLAG_8(res);
\r
8904 FLAG_X = FLAG_C = CFLAG_8(res);
\r
8905 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
8906 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
8908 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
8912 M68KMAKE_OP(sub, 16, er, d)
\r
8914 uint* r_dst = &DX;
\r
8915 uint src = MASK_OUT_ABOVE_16(DY);
\r
8916 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
8917 uint res = dst - src;
\r
8919 FLAG_N = NFLAG_16(res);
\r
8920 FLAG_X = FLAG_C = CFLAG_16(res);
\r
8921 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
8922 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
8924 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
8928 M68KMAKE_OP(sub, 16, er, a)
\r
8930 uint* r_dst = &DX;
\r
8931 uint src = MASK_OUT_ABOVE_16(AY);
\r
8932 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
8933 uint res = dst - src;
\r
8935 FLAG_N = NFLAG_16(res);
\r
8936 FLAG_X = FLAG_C = CFLAG_16(res);
\r
8937 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
8938 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
8940 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
8944 M68KMAKE_OP(sub, 16, er, .)
\r
8946 uint* r_dst = &DX;
\r
8947 uint src = M68KMAKE_GET_OPER_AY_16;
\r
8948 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
8949 uint res = dst - src;
\r
8951 FLAG_N = NFLAG_16(res);
\r
8952 FLAG_X = FLAG_C = CFLAG_16(res);
\r
8953 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
8954 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
8956 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
8960 M68KMAKE_OP(sub, 32, er, d)
\r
8962 uint* r_dst = &DX;
\r
8964 uint dst = *r_dst;
\r
8965 uint res = dst - src;
\r
8967 FLAG_N = NFLAG_32(res);
\r
8968 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
8969 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
8970 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
8976 M68KMAKE_OP(sub, 32, er, a)
\r
8978 uint* r_dst = &DX;
\r
8980 uint dst = *r_dst;
\r
8981 uint res = dst - src;
\r
8983 FLAG_N = NFLAG_32(res);
\r
8984 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
8985 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
8986 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
8992 M68KMAKE_OP(sub, 32, er, .)
\r
8994 uint* r_dst = &DX;
\r
8995 uint src = M68KMAKE_GET_OPER_AY_32;
\r
8996 uint dst = *r_dst;
\r
8997 uint res = dst - src;
\r
8999 FLAG_N = NFLAG_32(res);
\r
9000 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9001 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9002 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9008 M68KMAKE_OP(sub, 8, re, .)
\r
9010 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9011 uint src = MASK_OUT_ABOVE_8(DX);
\r
9012 uint dst = m68ki_read_8(ea);
\r
9013 uint res = dst - src;
\r
9015 FLAG_N = NFLAG_8(res);
\r
9016 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9017 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9018 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9020 m68ki_write_8(ea, FLAG_Z);
\r
9024 M68KMAKE_OP(sub, 16, re, .)
\r
9026 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9027 uint src = MASK_OUT_ABOVE_16(DX);
\r
9028 uint dst = m68ki_read_16(ea);
\r
9029 uint res = dst - src;
\r
9031 FLAG_N = NFLAG_16(res);
\r
9032 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9033 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9034 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9036 m68ki_write_16(ea, FLAG_Z);
\r
9040 M68KMAKE_OP(sub, 32, re, .)
\r
9042 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9044 uint dst = m68ki_read_32(ea);
\r
9045 uint res = dst - src;
\r
9047 FLAG_N = NFLAG_32(res);
\r
9048 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9049 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9050 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9052 m68ki_write_32(ea, FLAG_Z);
\r
9056 M68KMAKE_OP(suba, 16, ., d)
\r
9058 uint* r_dst = &AX;
\r
9060 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(DY));
\r
9064 M68KMAKE_OP(suba, 16, ., a)
\r
9066 uint* r_dst = &AX;
\r
9068 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(AY));
\r
9072 M68KMAKE_OP(suba, 16, ., .)
\r
9074 uint* r_dst = &AX;
\r
9076 *r_dst = MASK_OUT_ABOVE_32(*r_dst - MAKE_INT_16(M68KMAKE_GET_OPER_AY_16));
\r
9080 M68KMAKE_OP(suba, 32, ., d)
\r
9082 uint* r_dst = &AX;
\r
9084 *r_dst = MASK_OUT_ABOVE_32(*r_dst - DY);
\r
9088 M68KMAKE_OP(suba, 32, ., a)
\r
9090 uint* r_dst = &AX;
\r
9092 *r_dst = MASK_OUT_ABOVE_32(*r_dst - AY);
\r
9096 M68KMAKE_OP(suba, 32, ., .)
\r
9098 uint* r_dst = &AX;
\r
9100 *r_dst = MASK_OUT_ABOVE_32(*r_dst - M68KMAKE_GET_OPER_AY_32);
\r
9104 M68KMAKE_OP(subi, 8, ., d)
\r
9106 uint* r_dst = &DY;
\r
9107 uint src = OPER_I_8();
\r
9108 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9109 uint res = dst - src;
\r
9111 FLAG_N = NFLAG_8(res);
\r
9112 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9113 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9114 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9116 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9120 M68KMAKE_OP(subi, 8, ., .)
\r
9122 uint src = OPER_I_8();
\r
9123 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9124 uint dst = m68ki_read_8(ea);
\r
9125 uint res = dst - src;
\r
9127 FLAG_N = NFLAG_8(res);
\r
9128 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9129 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9130 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9132 m68ki_write_8(ea, FLAG_Z);
\r
9136 M68KMAKE_OP(subi, 16, ., d)
\r
9138 uint* r_dst = &DY;
\r
9139 uint src = OPER_I_16();
\r
9140 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9141 uint res = dst - src;
\r
9143 FLAG_N = NFLAG_16(res);
\r
9144 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9145 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9146 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9148 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9152 M68KMAKE_OP(subi, 16, ., .)
\r
9154 uint src = OPER_I_16();
\r
9155 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9156 uint dst = m68ki_read_16(ea);
\r
9157 uint res = dst - src;
\r
9159 FLAG_N = NFLAG_16(res);
\r
9160 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9161 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9162 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9164 m68ki_write_16(ea, FLAG_Z);
\r
9168 M68KMAKE_OP(subi, 32, ., d)
\r
9170 uint* r_dst = &DY;
\r
9171 uint src = OPER_I_32();
\r
9172 uint dst = *r_dst;
\r
9173 uint res = dst - src;
\r
9175 FLAG_N = NFLAG_32(res);
\r
9176 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9177 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9178 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9184 M68KMAKE_OP(subi, 32, ., .)
\r
9186 uint src = OPER_I_32();
\r
9187 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9188 uint dst = m68ki_read_32(ea);
\r
9189 uint res = dst - src;
\r
9191 FLAG_N = NFLAG_32(res);
\r
9192 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9193 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9194 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9196 m68ki_write_32(ea, FLAG_Z);
\r
9200 M68KMAKE_OP(subq, 8, ., d)
\r
9202 uint* r_dst = &DY;
\r
9203 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9204 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9205 uint res = dst - src;
\r
9207 FLAG_N = NFLAG_8(res);
\r
9208 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9209 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9210 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9212 *r_dst = MASK_OUT_BELOW_8(*r_dst) | FLAG_Z;
\r
9216 M68KMAKE_OP(subq, 8, ., .)
\r
9218 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9219 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9220 uint dst = m68ki_read_8(ea);
\r
9221 uint res = dst - src;
\r
9223 FLAG_N = NFLAG_8(res);
\r
9224 FLAG_Z = MASK_OUT_ABOVE_8(res);
\r
9225 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9226 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9228 m68ki_write_8(ea, FLAG_Z);
\r
9232 M68KMAKE_OP(subq, 16, ., d)
\r
9234 uint* r_dst = &DY;
\r
9235 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9236 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9237 uint res = dst - src;
\r
9239 FLAG_N = NFLAG_16(res);
\r
9240 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9241 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9242 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9244 *r_dst = MASK_OUT_BELOW_16(*r_dst) | FLAG_Z;
\r
9248 M68KMAKE_OP(subq, 16, ., a)
\r
9250 uint* r_dst = &AY;
\r
9252 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9256 M68KMAKE_OP(subq, 16, ., .)
\r
9258 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9259 uint ea = M68KMAKE_GET_EA_AY_16;
\r
9260 uint dst = m68ki_read_16(ea);
\r
9261 uint res = dst - src;
\r
9263 FLAG_N = NFLAG_16(res);
\r
9264 FLAG_Z = MASK_OUT_ABOVE_16(res);
\r
9265 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9266 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9268 m68ki_write_16(ea, FLAG_Z);
\r
9272 M68KMAKE_OP(subq, 32, ., d)
\r
9274 uint* r_dst = &DY;
\r
9275 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9276 uint dst = *r_dst;
\r
9277 uint res = dst - src;
\r
9279 FLAG_N = NFLAG_32(res);
\r
9280 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9281 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9282 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9288 M68KMAKE_OP(subq, 32, ., a)
\r
9290 uint* r_dst = &AY;
\r
9292 *r_dst = MASK_OUT_ABOVE_32(*r_dst - ((((REG_IR >> 9) - 1) & 7) + 1));
\r
9296 M68KMAKE_OP(subq, 32, ., .)
\r
9298 uint src = (((REG_IR >> 9) - 1) & 7) + 1;
\r
9299 uint ea = M68KMAKE_GET_EA_AY_32;
\r
9300 uint dst = m68ki_read_32(ea);
\r
9301 uint res = dst - src;
\r
9303 FLAG_N = NFLAG_32(res);
\r
9304 FLAG_Z = MASK_OUT_ABOVE_32(res);
\r
9305 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9306 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9308 m68ki_write_32(ea, FLAG_Z);
\r
9312 M68KMAKE_OP(subx, 8, rr, .)
\r
9314 uint* r_dst = &DX;
\r
9315 uint src = MASK_OUT_ABOVE_8(DY);
\r
9316 uint dst = MASK_OUT_ABOVE_8(*r_dst);
\r
9317 uint res = dst - src - XFLAG_AS_1();
\r
9319 FLAG_N = NFLAG_8(res);
\r
9320 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9321 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9323 res = MASK_OUT_ABOVE_8(res);
\r
9326 *r_dst = MASK_OUT_BELOW_8(*r_dst) | res;
\r
9330 M68KMAKE_OP(subx, 16, rr, .)
\r
9332 uint* r_dst = &DX;
\r
9333 uint src = MASK_OUT_ABOVE_16(DY);
\r
9334 uint dst = MASK_OUT_ABOVE_16(*r_dst);
\r
9335 uint res = dst - src - XFLAG_AS_1();
\r
9337 FLAG_N = NFLAG_16(res);
\r
9338 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9339 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9341 res = MASK_OUT_ABOVE_16(res);
\r
9344 *r_dst = MASK_OUT_BELOW_16(*r_dst) | res;
\r
9348 M68KMAKE_OP(subx, 32, rr, .)
\r
9350 uint* r_dst = &DX;
\r
9352 uint dst = *r_dst;
\r
9353 uint res = dst - src - XFLAG_AS_1();
\r
9355 FLAG_N = NFLAG_32(res);
\r
9356 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9357 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9359 res = MASK_OUT_ABOVE_32(res);
\r
9366 M68KMAKE_OP(subx, 8, mm, ax7)
\r
9368 uint src = OPER_AY_PD_8();
\r
9369 uint ea = EA_A7_PD_8();
\r
9370 uint dst = m68ki_read_8(ea);
\r
9371 uint res = dst - src - XFLAG_AS_1();
\r
9373 FLAG_N = NFLAG_8(res);
\r
9374 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9375 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9377 res = MASK_OUT_ABOVE_8(res);
\r
9380 m68ki_write_8(ea, res);
\r
9384 M68KMAKE_OP(subx, 8, mm, ay7)
\r
9386 uint src = OPER_A7_PD_8();
\r
9387 uint ea = EA_AX_PD_8();
\r
9388 uint dst = m68ki_read_8(ea);
\r
9389 uint res = dst - src - XFLAG_AS_1();
\r
9391 FLAG_N = NFLAG_8(res);
\r
9392 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9393 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9395 res = MASK_OUT_ABOVE_8(res);
\r
9398 m68ki_write_8(ea, res);
\r
9402 M68KMAKE_OP(subx, 8, mm, axy7)
\r
9404 uint src = OPER_A7_PD_8();
\r
9405 uint ea = EA_A7_PD_8();
\r
9406 uint dst = m68ki_read_8(ea);
\r
9407 uint res = dst - src - XFLAG_AS_1();
\r
9409 FLAG_N = NFLAG_8(res);
\r
9410 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9411 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9413 res = MASK_OUT_ABOVE_8(res);
\r
9416 m68ki_write_8(ea, res);
\r
9420 M68KMAKE_OP(subx, 8, mm, .)
\r
9422 uint src = OPER_AY_PD_8();
\r
9423 uint ea = EA_AX_PD_8();
\r
9424 uint dst = m68ki_read_8(ea);
\r
9425 uint res = dst - src - XFLAG_AS_1();
\r
9427 FLAG_N = NFLAG_8(res);
\r
9428 FLAG_X = FLAG_C = CFLAG_8(res);
\r
9429 FLAG_V = VFLAG_SUB_8(src, dst, res);
\r
9431 res = MASK_OUT_ABOVE_8(res);
\r
9434 m68ki_write_8(ea, res);
\r
9438 M68KMAKE_OP(subx, 16, mm, .)
\r
9440 uint src = OPER_AY_PD_16();
\r
9441 uint ea = EA_AX_PD_16();
\r
9442 uint dst = m68ki_read_16(ea);
\r
9443 uint res = dst - src - XFLAG_AS_1();
\r
9445 FLAG_N = NFLAG_16(res);
\r
9446 FLAG_X = FLAG_C = CFLAG_16(res);
\r
9447 FLAG_V = VFLAG_SUB_16(src, dst, res);
\r
9449 res = MASK_OUT_ABOVE_16(res);
\r
9452 m68ki_write_16(ea, res);
\r
9456 M68KMAKE_OP(subx, 32, mm, .)
\r
9458 uint src = OPER_AY_PD_32();
\r
9459 uint ea = EA_AX_PD_32();
\r
9460 uint dst = m68ki_read_32(ea);
\r
9461 uint res = dst - src - XFLAG_AS_1();
\r
9463 FLAG_N = NFLAG_32(res);
\r
9464 FLAG_X = FLAG_C = CFLAG_SUB_32(src, dst, res);
\r
9465 FLAG_V = VFLAG_SUB_32(src, dst, res);
\r
9467 res = MASK_OUT_ABOVE_32(res);
\r
9470 m68ki_write_32(ea, res);
\r
9474 M68KMAKE_OP(swap, 32, ., .)
\r
9476 uint* r_dst = &DY;
\r
9478 FLAG_Z = MASK_OUT_ABOVE_32(*r_dst<<16);
\r
9479 *r_dst = (*r_dst>>16) | FLAG_Z;
\r
9482 FLAG_N = NFLAG_32(*r_dst);
\r
9483 FLAG_C = CFLAG_CLEAR;
\r
9484 FLAG_V = VFLAG_CLEAR;
\r
9488 M68KMAKE_OP(tas, 8, ., d)
\r
9490 uint* r_dst = &DY;
\r
9492 FLAG_Z = MASK_OUT_ABOVE_8(*r_dst);
\r
9493 FLAG_N = NFLAG_8(*r_dst);
\r
9494 FLAG_V = VFLAG_CLEAR;
\r
9495 FLAG_C = CFLAG_CLEAR;
\r
9500 M68KMAKE_OP(tas, 8, ., .)
\r
9502 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9503 uint dst = m68ki_read_8(ea);
\r
9506 FLAG_N = NFLAG_8(dst);
\r
9507 FLAG_V = VFLAG_CLEAR;
\r
9508 FLAG_C = CFLAG_CLEAR;
\r
9509 m68ki_write_8(ea, dst | 0x80);
\r
9513 M68KMAKE_OP(trap, 0, ., .)
\r
9515 /* Trap#n stacks exception frame type 0 */
\r
9516 m68ki_exception_trapN(EXCEPTION_TRAP_BASE + (REG_IR & 0xf)); /* HJB 990403 */
\r
9520 M68KMAKE_OP(trapt, 0, ., .)
\r
9522 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9524 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
9527 m68ki_exception_illegal();
\r
9531 M68KMAKE_OP(trapt, 16, ., .)
\r
9533 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9535 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
9538 m68ki_exception_illegal();
\r
9542 M68KMAKE_OP(trapt, 32, ., .)
\r
9544 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9546 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
9549 m68ki_exception_illegal();
\r
9553 M68KMAKE_OP(trapf, 0, ., .)
\r
9555 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9559 m68ki_exception_illegal();
\r
9563 M68KMAKE_OP(trapf, 16, ., .)
\r
9565 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9570 m68ki_exception_illegal();
\r
9574 M68KMAKE_OP(trapf, 32, ., .)
\r
9576 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9581 m68ki_exception_illegal();
\r
9585 M68KMAKE_OP(trapcc, 0, ., .)
\r
9587 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9590 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
9593 m68ki_exception_illegal();
\r
9597 M68KMAKE_OP(trapcc, 16, ., .)
\r
9599 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9603 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
9609 m68ki_exception_illegal();
\r
9613 M68KMAKE_OP(trapcc, 32, ., .)
\r
9615 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9619 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
9625 m68ki_exception_illegal();
\r
9629 M68KMAKE_OP(trapv, 0, ., .)
\r
9635 m68ki_exception_trap(EXCEPTION_TRAPV); /* HJB 990403 */
\r
9639 M68KMAKE_OP(tst, 8, ., d)
\r
9641 uint res = MASK_OUT_ABOVE_8(DY);
\r
9643 FLAG_N = NFLAG_8(res);
\r
9645 FLAG_V = VFLAG_CLEAR;
\r
9646 FLAG_C = CFLAG_CLEAR;
\r
9650 M68KMAKE_OP(tst, 8, ., .)
\r
9652 uint ea = M68KMAKE_GET_EA_AY_8;
\r
9653 uint res = m68ki_read_8(ea);
\r
9655 FLAG_N = NFLAG_8(res);
\r
9657 FLAG_V = VFLAG_CLEAR;
\r
9658 FLAG_C = CFLAG_CLEAR;
\r
9662 M68KMAKE_OP(tst, 8, ., pcdi)
\r
9664 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9666 uint res = OPER_PCDI_8();
\r
9668 FLAG_N = NFLAG_8(res);
\r
9670 FLAG_V = VFLAG_CLEAR;
\r
9671 FLAG_C = CFLAG_CLEAR;
\r
9674 m68ki_exception_illegal();
\r
9678 M68KMAKE_OP(tst, 8, ., pcix)
\r
9680 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9682 uint res = OPER_PCIX_8();
\r
9684 FLAG_N = NFLAG_8(res);
\r
9686 FLAG_V = VFLAG_CLEAR;
\r
9687 FLAG_C = CFLAG_CLEAR;
\r
9690 m68ki_exception_illegal();
\r
9694 M68KMAKE_OP(tst, 8, ., i)
\r
9696 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9698 uint res = OPER_I_8();
\r
9700 FLAG_N = NFLAG_8(res);
\r
9702 FLAG_V = VFLAG_CLEAR;
\r
9703 FLAG_C = CFLAG_CLEAR;
\r
9706 m68ki_exception_illegal();
\r
9710 M68KMAKE_OP(tst, 16, ., d)
\r
9712 uint res = MASK_OUT_ABOVE_16(DY);
\r
9714 FLAG_N = NFLAG_16(res);
\r
9716 FLAG_V = VFLAG_CLEAR;
\r
9717 FLAG_C = CFLAG_CLEAR;
\r
9721 M68KMAKE_OP(tst, 16, ., a)
\r
9723 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9725 uint res = MAKE_INT_16(AY);
\r
9727 FLAG_N = NFLAG_16(res);
\r
9729 FLAG_V = VFLAG_CLEAR;
\r
9730 FLAG_C = CFLAG_CLEAR;
\r
9733 m68ki_exception_illegal();
\r
9737 M68KMAKE_OP(tst, 16, ., .)
\r
9739 uint res = M68KMAKE_GET_OPER_AY_16;
\r
9741 FLAG_N = NFLAG_16(res);
\r
9743 FLAG_V = VFLAG_CLEAR;
\r
9744 FLAG_C = CFLAG_CLEAR;
\r
9748 M68KMAKE_OP(tst, 16, ., pcdi)
\r
9750 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9752 uint res = OPER_PCDI_16();
\r
9754 FLAG_N = NFLAG_16(res);
\r
9756 FLAG_V = VFLAG_CLEAR;
\r
9757 FLAG_C = CFLAG_CLEAR;
\r
9760 m68ki_exception_illegal();
\r
9764 M68KMAKE_OP(tst, 16, ., pcix)
\r
9766 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9768 uint res = OPER_PCIX_16();
\r
9770 FLAG_N = NFLAG_16(res);
\r
9772 FLAG_V = VFLAG_CLEAR;
\r
9773 FLAG_C = CFLAG_CLEAR;
\r
9776 m68ki_exception_illegal();
\r
9780 M68KMAKE_OP(tst, 16, ., i)
\r
9782 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9784 uint res = OPER_I_16();
\r
9786 FLAG_N = NFLAG_16(res);
\r
9788 FLAG_V = VFLAG_CLEAR;
\r
9789 FLAG_C = CFLAG_CLEAR;
\r
9792 m68ki_exception_illegal();
\r
9796 M68KMAKE_OP(tst, 32, ., d)
\r
9800 FLAG_N = NFLAG_32(res);
\r
9802 FLAG_V = VFLAG_CLEAR;
\r
9803 FLAG_C = CFLAG_CLEAR;
\r
9807 M68KMAKE_OP(tst, 32, ., a)
\r
9809 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9813 FLAG_N = NFLAG_32(res);
\r
9815 FLAG_V = VFLAG_CLEAR;
\r
9816 FLAG_C = CFLAG_CLEAR;
\r
9819 m68ki_exception_illegal();
\r
9823 M68KMAKE_OP(tst, 32, ., .)
\r
9825 uint res = M68KMAKE_GET_OPER_AY_32;
\r
9827 FLAG_N = NFLAG_32(res);
\r
9829 FLAG_V = VFLAG_CLEAR;
\r
9830 FLAG_C = CFLAG_CLEAR;
\r
9834 M68KMAKE_OP(tst, 32, ., pcdi)
\r
9836 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9838 uint res = OPER_PCDI_32();
\r
9840 FLAG_N = NFLAG_32(res);
\r
9842 FLAG_V = VFLAG_CLEAR;
\r
9843 FLAG_C = CFLAG_CLEAR;
\r
9846 m68ki_exception_illegal();
\r
9850 M68KMAKE_OP(tst, 32, ., pcix)
\r
9852 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9854 uint res = OPER_PCIX_32();
\r
9856 FLAG_N = NFLAG_32(res);
\r
9858 FLAG_V = VFLAG_CLEAR;
\r
9859 FLAG_C = CFLAG_CLEAR;
\r
9862 m68ki_exception_illegal();
\r
9866 M68KMAKE_OP(tst, 32, ., i)
\r
9868 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9870 uint res = OPER_I_32();
\r
9872 FLAG_N = NFLAG_32(res);
\r
9874 FLAG_V = VFLAG_CLEAR;
\r
9875 FLAG_C = CFLAG_CLEAR;
\r
9878 m68ki_exception_illegal();
\r
9882 M68KMAKE_OP(unlk, 32, ., a7)
\r
9884 REG_A[7] = m68ki_read_32(REG_A[7]);
\r
9888 M68KMAKE_OP(unlk, 32, ., .)
\r
9890 uint* r_dst = &AY;
\r
9892 REG_A[7] = *r_dst;
\r
9893 *r_dst = m68ki_pull_32();
\r
9897 M68KMAKE_OP(unpk, 16, rr, .)
\r
9899 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9901 /* Note: DX and DY are reversed in Motorola's docs */
\r
9903 uint* r_dst = &DX;
\r
9905 *r_dst = MASK_OUT_BELOW_16(*r_dst) | (((((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16()) & 0xffff);
\r
9908 m68ki_exception_illegal();
\r
9912 M68KMAKE_OP(unpk, 16, mm, ax7)
\r
9914 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9916 /* Note: AX and AY are reversed in Motorola's docs */
\r
9917 uint src = OPER_AY_PD_8();
\r
9920 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
9921 ea_dst = EA_A7_PD_8();
\r
9922 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
9923 ea_dst = EA_A7_PD_8();
\r
9924 m68ki_write_8(ea_dst, src & 0xff);
\r
9927 m68ki_exception_illegal();
\r
9931 M68KMAKE_OP(unpk, 16, mm, ay7)
\r
9933 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9935 /* Note: AX and AY are reversed in Motorola's docs */
\r
9936 uint src = OPER_A7_PD_8();
\r
9939 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
9940 ea_dst = EA_AX_PD_8();
\r
9941 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
9942 ea_dst = EA_AX_PD_8();
\r
9943 m68ki_write_8(ea_dst, src & 0xff);
\r
9946 m68ki_exception_illegal();
\r
9950 M68KMAKE_OP(unpk, 16, mm, axy7)
\r
9952 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9954 uint src = OPER_A7_PD_8();
\r
9957 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
9958 ea_dst = EA_A7_PD_8();
\r
9959 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
9960 ea_dst = EA_A7_PD_8();
\r
9961 m68ki_write_8(ea_dst, src & 0xff);
\r
9964 m68ki_exception_illegal();
\r
9968 M68KMAKE_OP(unpk, 16, mm, .)
\r
9970 if(CPU_TYPE_IS_EC020_PLUS(CPU_TYPE))
\r
9972 /* Note: AX and AY are reversed in Motorola's docs */
\r
9973 uint src = OPER_AY_PD_8();
\r
9976 src = (((src << 4) & 0x0f00) | (src & 0x000f)) + OPER_I_16();
\r
9977 ea_dst = EA_AX_PD_8();
\r
9978 m68ki_write_8(ea_dst, (src >> 8) & 0xff);
\r
9979 ea_dst = EA_AX_PD_8();
\r
9980 m68ki_write_8(ea_dst, src & 0xff);
\r
9983 m68ki_exception_illegal();
\r
9988 XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
\r
projects / virtualjaguar / blob