+#if 0
+
+#define PIA_IRQ1 (0x80)
+#define PIA_IRQ2 (0x40)
+
+#define IRQ1_ENABLED(c) ( (((c) >> 0) & 0x01))
+#define C1_LOW_TO_HIGH(c) ( (((c) >> 1) & 0x01))
+#define C1_HIGH_TO_LOW(c) (!(((c) >> 1) & 0x01))
+#define OUTPUT_SELECTED(c) ( (((c) >> 2) & 0x01))
+#define IRQ2_ENABLED(c) ( (((c) >> 3) & 0x01))
+#define STROBE_E_RESET(c) ( (((c) >> 3) & 0x01))
+#define STROBE_C1_RESET(c) (!(((c) >> 3) & 0x01))
+#define C2_SET(c) ( (((c) >> 3) & 0x01))
+#define C2_LOW_TO_HIGH(c) ( (((c) >> 4) & 0x01))
+#define C2_HIGH_TO_LOW(c) (!(((c) >> 4) & 0x01))
+#define C2_SET_MODE(c) ( (((c) >> 4) & 0x01))
+#define C2_STROBE_MODE(c) (!(((c) >> 4) & 0x01))
+#define C2_OUTPUT(c) ( (((c) >> 5) & 0x01))
+#define C2_INPUT(c) (!(((c) >> 5) & 0x01))
+
+WRITE8_DEVICE_HANDLER( pia6821_ca1_w )
+{
+ pia6821_state *p = get_token(device);
+
+ /* limit the data to 0 or 1 */
+ data = data ? TRUE : FALSE;
+
+ LOG(("PIA #%s: set input CA1 = %d\n", device->tag, data));
+
+ /* the new state has caused a transition */
+ if ((p->in_ca1 != data) &&
+ ((data && C1_LOW_TO_HIGH(p->ctl_a)) || (!data && C1_HIGH_TO_LOW(p->ctl_a))))
+ {
+ LOG(("PIA #%s: CA1 triggering\n", device->tag));
+
+ /* mark the IRQ */
+ p->irq_a1 = TRUE;
+
+ /* update externals */
+ update_interrupts(device);
+
+ /* CA2 is configured as output and in read strobe mode and cleared by a CA1 transition */
+ if (C2_OUTPUT(p->ctl_a) && C2_STROBE_MODE(p->ctl_a) && STROBE_C1_RESET(p->ctl_a))
+ set_out_ca2(device, TRUE);
+ }
+
+ /* set the new value for CA1 */
+ p->in_ca1 = data;
+ p->in_ca1_pushed = TRUE;
+}
+
+WRITE8_DEVICE_HANDLER( pia6821_cb1_w )
+{
+ pia6821_state *p = get_token(device);
+
+ /* limit the data to 0 or 1 */
+ data = data ? 1 : 0;
+
+ LOG(("PIA #%s: set input CB1 = %d\n", device->tag, data));
+
+ /* the new state has caused a transition */
+ if ((p->in_cb1 != data) &&
+ ((data && C1_LOW_TO_HIGH(p->ctl_b)) || (!data && C1_HIGH_TO_LOW(p->ctl_b))))
+ {
+ LOG(("PIA #%s: CB1 triggering\n", device->tag));
+
+ /* mark the IRQ */
+ p->irq_b1 = 1;
+
+ /* update externals */
+ update_interrupts(device);
+
+ /* If CB2 is configured as a write-strobe output which is reset by a CB1
+ transition, this reset will only happen when a read from port B implicitly
+ clears the IRQ B1 flag. So we handle the CB2 reset there. Note that this
+ is different from what happens with port A. */
+ }
+
+ /* set the new value for CB1 */
+ p->in_cb1 = data;
+ p->in_cb1_pushed = TRUE;
+}
+
+static void update_interrupts(const device_config *device)
+{
+ pia6821_state *p = get_token(device);
+ int new_state;
+
+ /* start with IRQ A */
+ new_state = (p->irq_a1 && IRQ1_ENABLED(p->ctl_a)) || (p->irq_a2 && IRQ2_ENABLED(p->ctl_a));
+
+ if (new_state != p->irq_a_state)
+ {
+ p->irq_a_state = new_state;
+ devcb_call_write_line(&p->irq_a_func, p->irq_a_state);
+ }
+
+ /* then do IRQ B */
+ new_state = (p->irq_b1 && IRQ1_ENABLED(p->ctl_b)) || (p->irq_b2 && IRQ2_ENABLED(p->ctl_b));
+
+ if (new_state != p->irq_b_state)
+ {
+ p->irq_b_state = new_state;
+ devcb_call_write_line(&p->irq_b_func, p->irq_b_state);
+ }
+}
+
+static void control_b_w(const device_config *device, UINT8 data)
+{
+ pia6821_state *p = get_token(device);
+ int temp;
+
+ /* bit 7 and 6 are read only */
+ data &= 0x3f;
+
+ LOG(("PIA #%s: control B write = %02X\n", device->tag, data));
+
+ /* update the control register */
+ p->ctl_b = data;
+
+ if (C2_SET_MODE(p->ctl_b))
+ /* set/reset mode - bit value determines the new output */
+ temp = C2_SET(p->ctl_b);
+ else
+ /* strobe mode - output is always high unless strobed */
+ temp = TRUE;
+
+ set_out_cb2(device, temp);
+
+ /* update externals */
+ update_interrupts(device);
+}
+
+static void control_a_w(const device_config *device, UINT8 data)
+{
+ pia6821_state *p = get_token(device);
+
+ /* bit 7 and 6 are read only */
+ data &= 0x3f;
+
+ LOG(("PIA #%s: control A write = %02X\n", device->tag, data));
+
+ /* update the control register */
+ p->ctl_a = data;
+
+ /* CA2 is configured as output */
+ if (C2_OUTPUT(p->ctl_a))
+ {
+ int temp;
+
+ if (C2_SET_MODE(p->ctl_a))
+ /* set/reset mode - bit value determines the new output */
+ temp = C2_SET(p->ctl_a);
+ else
+ /* strobe mode - output is always high unless strobed */
+ temp = TRUE;
+
+ set_out_ca2(device, temp);
+ }
+
+ /* update externals */
+ update_interrupts(device);
+}
+
+
+CTRL REGISTER:
+
+B7 B6 B5 B4 B3 B2 B1 B0
+--------------------------------------------------
+IRQA(B)1 IRQA(B)2 CA(B)2 Ctrl DDR CA(B)1 Ctrl
+
+Bits 6 & 7 are RO. IRQs are cleared on read of PORTA when not in DDR mode
+DDR: 0: DDR selected, 1: Output register selected
+CA1(CB1) Ctrl: B0: 0/1 Dis/enable interrupt IRQA(B)
+ B1: 0/1 IRQ set by Hi-to-Lo/Lo-to-Hi transition on CA(B)1
+CA2(CB2) Ctrl: If B5==0, B4 & B3 are similar to B1 & B0
+
+Entering main loop...
+V6809 WrMem: Writing PIA (PACTL) address C80D [->00, PC=F4DC] --> Set DDR on PORTA, IRQs off
+V6809 WrMem: Writing PIA (PORTA) address C80C [->00, PC=F4DF] --> Set DDR to all input on PORTA
+V6809 WrMem: Writing PIA (PACTL) address C80D [->3C, PC=F4E4] --> Set Output on PORTA, Set CA2 = 1, disable IRQA1
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->00, PC=F4E7] --> Set DDR on PORTB, IRQs off
+V6809 WrMem: Writing PIA (PORTB) address C80E [->C0, PC=F4EC] --> Set DDR to output on 6,7 input on 0-5 on PORTB
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->3C, PC=F4F1] --> Set Output on PORTA, Set CB2 = 1, disable IRQB1
+V6809 WrMem: Writing PIA (PORTB) address C80E [->C0, PC=F4F6] --> Send 1s on bits 6 & 7 on PORTB
+V6809 WrMem: Writing PIA (PACTL) address C80D [->34, PC=F523] --> Set Output on PORTA, Set CA2 = 0, disable IRQA1
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=F526] --> Set Output on PORTB, Set CB2 = 0, disable IRQB1
+V6809 WrMem: Writing PIA (PORTB) address C80E [->00, PC=F529] --> Send 0s on bits 6 & 7 on PORTB
+V6809 WrMem: Writing PIA (PORTA) address C80C [->00, PC=6076] --> Do nothing
+V6809 WrMem: Writing PIA (PACTL) address C80D [->00, PC=6076] --> Set DDR on PORTA, IRQs off
+V6809 WrMem: Writing PIA (PORTA) address C80C [->00, PC=607B] --> Set DDR to all input on PORTA
+V6809 WrMem: Writing PIA (PACTL) address C80D [->34, PC=607B] --> Set Output on PORTA, Set CA2 = 0, disable IRQA1
+V6809 WrMem: Writing PIA (PORTB) address C80E [->00, PC=6076] --> Send 0s on bits 6 & 7 on PORTB
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->00, PC=6076] --> Set DDR on PORTB, IRQs off
+V6809 WrMem: Writing PIA (PORTB) address C80E [->FF, PC=607B] --> Set DDR to all output on PORTB
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->35, PC=607B] --> Set Output on PORTB, Set CB2 = 0, enable IRQB1
+V6809 WrMem: Writing PIA (PORTB) address C80E [->3F, PC=6088] --> Send $3F on PORTB
+V6809 WrMem: Writing PIA (PORTB) address C80E [->0C, PC=60DB] --> Send $0C on PORTB
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=15C3] --> Set Output on PORTB, Set CB2 = 0, disable IRQB1
+ 6809 RdMem: Reading PIA (PORTB) address C80E [=0C, PC=15C6] --> Clear IRQBs
+ 6809 RdMem: Reading PIA (PORTA) address C80C [=00, PC=075B] --> Clear IRQAs
+ 6809 RdMem: Reading PIA (PORTA) address C80C [=00, PC=07B9] --> Clear IRQAs
+
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->35, PC=1644] --> Set Output on PORTB, Set CB2 = 0, enable IRQB1
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=15C3] --> Set Output on PORTB, Set CB2 = 0, disable IRQB1
+ 6809 RdMem: Reading PIA (PORTB) address C80E [=0C, PC=15C6] --> Clear IRQBs
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->35, PC=1644]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=15C3]
+ 6809 RdMem: Reading PIA (PORTB) address C80E [=0C, PC=15C6]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->35, PC=1644]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=15C3]
+ 6809 RdMem: Reading PIA (PORTB) address C80E [=0C, PC=15C6]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->35, PC=1644]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=15C3]
+ 6809 RdMem: Reading PIA (PORTB) address C80E [=0C, PC=15C6]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->35, PC=1644]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=15C3]
+ 6809 RdMem: Reading PIA (PORTB) address C80E [=0C, PC=15C6]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->35, PC=1644]
+V6809 WrMem: Writing PIA (PBCTL) address C80F [->34, PC=15C3]
+ 6809 RdMem: Reading PIA (PORTB) address C80E [=0C, PC=15C6]
+
+#endif