2 // Virtual 6809 v1.2P (Last build: 2/2/2004)
6 // (c) 1997 Underground Software
9 #include <string> // To make this really clean, we'd have to make our own memcpy, etc...
12 // Global defs (needed because functions can only return one value.
13 // Maybe you could use a struct to pass multiple values, but
14 // what a pain in the ass! This way makes a little more sense
17 //BYTE * ram, * rom; // RAM & ROM image spaces (64K each)
18 WORD pcr, xr, yr, sr, ur; // Double byte registers
19 BYTE ccr, ar, br, dpr;
21 bool /*color_reg = false,*/ illegal = false, inter;
23 // Instead of the above, we can use a private struct for our CPU state...
25 static V6809REGS regs;
27 static WORD addr; // Temporary variables common to all funcs...
30 extern BYTE Fetch(); // You need to define these functions
31 //extern WORD FetchW(); // externally because every hardware situation
32 extern BYTE RdMem(WORD); // is going to be different...
33 extern void WrMem(WORD, BYTE);
35 // Internal function prototypes
37 WORD ReadEXG(BYTE); // Read TFR/EXG post byte
38 void WriteEXG(BYTE, WORD); // Set TFR/EXG data
39 WORD DecodeReg(BYTE); // Decode register data
40 WORD DecodeIDX(BYTE); // Decode IDX data
43 // Fetch word function
47 return (WORD)(Fetch() << 8) | Fetch();
51 // Return signed byte from unsigned
55 return (b & 0x80 ? b - 256 : b);
59 // Return signed word from unsigned
63 return (w & 0x8000 ? w - 65536 : w);
67 // Function to read TFR/EXG post byte
69 WORD ReadEXG(BYTE code)
75 case 0: retval = (ar<<8) | br; break;
76 case 1: retval = xr; break;
77 case 2: retval = yr; break;
78 case 3: retval = ur; break;
79 case 4: retval = sr; break;
80 case 5: retval = pcr; break;
81 case 8: retval = ar; break;
82 case 9: retval = br; break;
83 case 10: retval = ccr; break;
84 case 11: retval = dpr; break;
85 default: retval = 0xFF;
91 // Function to set TFR/EXG data
93 void WriteEXG(BYTE code, WORD data)
98 ar = data >> 8, br = data & 0xFF; break;
110 ar = data & 0xFF; break;
112 br = data & 0xFF; break;
114 ccr = data & 0xFF; break;
116 dpr = data & 0xFF; break;
121 // Function to decode register data
123 WORD DecodeReg(BYTE reg)
143 // Function to decode IDX data
145 WORD DecodeIDX(BYTE code)
148 BYTE reg = (code&0x60)>>5, idxind = (code&0x10)>>4, lo_nyb = code&0x0F;
150 if (!(code&0x80)) // Hi bit unset? Then decode 4 bit offset
152 addr = DecodeReg(reg) + (idxind ? lo_nyb-16 : lo_nyb);
160 case 1: { woff = DecodeReg(reg);
161 addr = (RdMem(woff)<<8) | RdMem(woff+1);
164 case 0: xr++; xr++; break;
165 case 1: yr++; yr++; break;
166 case 2: ur++; ur++; break;
167 case 3: sr++; sr++; break;
170 case 3: { switch(reg)
172 case 0: xr--; xr--; break;
173 case 1: yr--; yr--; break;
174 case 2: ur--; ur--; break;
175 case 3: sr--; sr--; break;
177 woff = DecodeReg(reg);
178 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
179 case 4: { woff = DecodeReg(reg);
180 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
181 case 5: { woff = DecodeReg(reg) + SignedB(br);
182 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
183 case 6: { woff = DecodeReg(reg) + SignedB(ar);
184 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
185 case 8: { woff = DecodeReg(reg) + SignedB(Fetch());
186 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
187 case 9: { woff = DecodeReg(reg) + SignedW(FetchW());
188 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
189 case 11: { woff = DecodeReg(reg) + SignedW((ar<<8) | br);
190 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
191 case 12: { woff = pcr + SignedB(Fetch());
192 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
193 case 13: { woff = pcr + SignedW(FetchW());
194 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
195 case 15: { woff = FetchW();
196 addr = (RdMem(woff)<<8) | RdMem(woff+1); break; }
203 case 0: { addr = DecodeReg(reg);
212 case 1: { addr = DecodeReg(reg);
215 case 0: xr++; xr++; break;
216 case 1: yr++; yr++; break;
217 case 2: ur++; ur++; break;
218 case 3: sr++; sr++; break;
221 case 2: { switch(reg)
228 addr = DecodeReg(reg); break; }
229 case 3: { switch(reg)
231 case 0: xr--; xr--; break;
232 case 1: yr--; yr--; break;
233 case 2: ur--; ur--; break;
234 case 3: sr--; sr--; break;
236 addr = DecodeReg(reg); break; }
237 case 4: { addr = DecodeReg(reg); break; }
238 case 5: { addr = DecodeReg(reg) + SignedB(br); break; }
239 case 6: { addr = DecodeReg(reg) + SignedB(ar); break; }
240 case 8: { addr = DecodeReg(reg) + SignedB(Fetch()); break; }
241 case 9: { addr = DecodeReg(reg) + SignedW(FetchW()); break; }
242 case 11: { addr = DecodeReg(reg) + SignedW((ar<<8) | br); break; }
243 case 12: { addr = pcr + SignedB(Fetch()); break; }
244 case 13: { addr = pcr + SignedW(FetchW()); break; }
252 // Page zero instructions...
255 void Op00(void) // NEG DP
257 addr = (dpr<<8) | Fetch();
258 tmp = 256 - RdMem(addr);
260 (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
261 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
262 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
263 (tmp > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry
266 void Op03(void) // COM DP
268 addr = (dpr<<8) | Fetch();
269 tmp = 0xFF ^ RdMem(addr);
271 ccr &= 0xFD; ccr |= 0x01; // CLV SEC
272 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
273 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
276 void Op04(void) // LSR DP
278 addr = (dpr<<8) | Fetch();
280 (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry
281 tmp >>= 1; WrMem(addr, tmp);
283 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
286 void Op06(void) // ROR DP
288 addr = (dpr<<8) | Fetch(); BYTE tmp2 = RdMem(addr);
289 tmp = (tmp2>>1) + (ccr&0x01)*128;
291 (tmp2&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
292 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
293 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
296 void Op07(void) // ASR DP
298 addr = (dpr<<8) | Fetch(); tmp = RdMem(addr);
299 (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
301 if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
303 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
304 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
307 void Op08(void) // LSL DP
309 addr = (dpr<<8) | Fetch(); // NEEDS OVERFLOW ADJUSTMENT
311 (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
314 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
315 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
318 void Op09(void) // ROL DP
320 addr = (dpr<<8) | Fetch(); BYTE tmp2 = RdMem(addr);
321 tmp = (tmp2<<1) + (ccr&0x01);
323 (tmp2&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
324 ((tmp2&0x80)^((tmp2<<1)&0x80) ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
325 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
326 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
329 void Op0A(void) // DEC DP
331 addr = (dpr<<8) | Fetch();
332 tmp = RdMem(addr) - 1;
334 (tmp == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
335 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
336 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
339 void Op0C(void) // INC DP
341 addr = (dpr<<8) | Fetch();
342 tmp = RdMem(addr) + 1;
344 (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
345 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
346 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
349 void Op0D(void) // TST DP
351 tmp = RdMem((dpr<<8)|Fetch());
353 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
354 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
357 void Op0E(void) // JMP DP
359 pcr = (dpr<<8) | Fetch();
362 void Op0F(void) // CLR DP
364 WrMem((dpr<<8)|Fetch(), 0);
365 ccr &= 0xF0; ccr |= 0x04; // CLN, SEZ, CLV, CLC
368 void Op12(void) // NOP
372 void Op13(void) // SYNC
376 void Op16(void) // LBRA
378 pcr += SignedW(FetchW());
381 void Op17(void) // LBSR
384 WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8);
385 pcr += SignedW(addr);
388 void Op19(void) // DAA
390 if ((ccr&0x20) || ((ar&0x0F) > 0x09)) // H set or lo nyb too big?
392 ar += 0x06; ccr |= 0x20; // Then adjust & set half carry
394 if ((ccr&0x01) || (ar > 0x9F)) // C set or hi nyb too big?
396 ar += 0x60; ccr |= 0x01; // Then adjust & set carry
398 ccr &= 0xF1; // CL NZV
399 if (ar == 0) ccr |= 0x04; // Adjust Zero flag
400 if (ar&0x80) ccr |= 0x08; // Adjust Negative flag
403 void Op1A(void) // ORCC #
408 void Op1C(void) // ANDCC #
413 void Op1D(void) // SEX
415 (br&0x80 ? ar = 0xFF : ar = 0x00);
416 ((ar|br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
417 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
420 void Op1E(void) // EXG
423 addr = ReadEXG(tmp>>4); WriteEXG(tmp>>4, ReadEXG(tmp&0xF));
424 WriteEXG(tmp&0xF, addr);
427 void Op1F(void) // TFR
430 WriteEXG(tmp&0xF, ReadEXG(tmp>>4));
433 void Op20(void) // BRA
435 pcr += SignedB(Fetch()); // Branch always
438 void Op21(void) // BRN
443 void Op22(void) // BHI
446 if (!(ccr&0x05)) pcr += SignedB(tmp);
449 void Op23(void) // BLS
452 if (ccr&0x05) pcr += SignedB(tmp);
455 void Op24(void) // BCC (BHS)
458 if (!(ccr&0x01)) pcr += SignedB(tmp);
461 void Op25(void) // BCS (BLO)
464 if (ccr&0x01) pcr += SignedB(tmp);
467 void Op26(void) // BNE
470 if (!(ccr&0x04)) pcr += SignedB(tmp);
473 void Op27(void) // BEQ
476 if (ccr&0x04) pcr += SignedB(tmp);
479 void Op28(void) // BVC
482 if (!(ccr&0x02)) pcr += SignedB(tmp);
485 void Op29(void) // BVS
488 if (ccr&0x02) pcr += SignedB(tmp);
491 void Op2A(void) // BPL
494 if (!(ccr&0x08)) pcr += SignedB(tmp);
497 void Op2B(void) // BMI
500 if (ccr&0x08) pcr += SignedB(tmp);
503 void Op2C(void) // BGE
506 if (!(((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedB(tmp);
509 void Op2D(void) // BLT
512 if (((ccr&0x08) >> 2) ^ (ccr&0x02)) pcr += SignedB(tmp);
515 void Op2E(void) // BGT
518 if (!((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02)))) pcr += SignedB(tmp);
521 void Op2F(void) // BLE
524 if ((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedB(tmp);
527 void Op30(void) // LEAX
529 xr = DecodeIDX(Fetch());
530 (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
533 void Op31(void) // LEAY
535 yr = DecodeIDX(Fetch());
536 (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
539 void Op32(void) // LEAS
541 sr = DecodeIDX(Fetch());
542 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
545 void Op33(void) // LEAU
547 ur = DecodeIDX(Fetch());
548 (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
551 void Op34(void) // PSHS
554 if (tmp&0x80) { WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); }
555 if (tmp&0x40) { WrMem(--sr, ur&0xFF); WrMem(--sr, ur>>8); }
556 if (tmp&0x20) { WrMem(--sr, yr&0xFF); WrMem(--sr, yr>>8); }
557 if (tmp&0x10) { WrMem(--sr, xr&0xFF); WrMem(--sr, xr>>8); }
558 if (tmp&0x08) WrMem(--sr, dpr);
559 if (tmp&0x04) WrMem(--sr, br);
560 if (tmp&0x02) WrMem(--sr, ar);
561 if (tmp&0x01) WrMem(--sr, ccr);
564 void Op35(void) // PULS
567 if (tmp&0x01) ccr = RdMem(sr++);
568 if (tmp&0x02) ar = RdMem(sr++);
569 if (tmp&0x04) br = RdMem(sr++);
570 if (tmp&0x08) dpr = RdMem(sr++);
571 if (tmp&0x10) xr = (RdMem(sr++)<<8) | RdMem(sr++);
572 if (tmp&0x20) yr = (RdMem(sr++)<<8) | RdMem(sr++);
573 if (tmp&0x40) ur = (RdMem(sr++)<<8) | RdMem(sr++);
574 if (tmp&0x80) pcr = (RdMem(sr++)<<8) | RdMem(sr++);
577 void Op36(void) // PSHU
580 if (tmp&0x80) { WrMem(--ur, pcr&0xFF); WrMem(--ur, pcr>>8); }
581 if (tmp&0x40) { WrMem(--ur, sr&0xFF); WrMem(--ur, sr>>8); }
582 if (tmp&0x20) { WrMem(--ur, yr&0xFF); WrMem(--ur, yr>>8); }
583 if (tmp&0x10) { WrMem(--ur, xr&0xFF); WrMem(--ur, xr>>8); }
584 if (tmp&0x08) WrMem(--ur, dpr);
585 if (tmp&0x04) WrMem(--ur, br);
586 if (tmp&0x02) WrMem(--ur, ar);
587 if (tmp&0x01) WrMem(--ur, ccr);
590 void Op37(void) // PULU
593 if (tmp&0x01) ccr = RdMem(ur++);
594 if (tmp&0x02) ar = RdMem(ur++);
595 if (tmp&0x04) br = RdMem(ur++);
596 if (tmp&0x08) dpr = RdMem(ur++);
597 if (tmp&0x10) xr = (RdMem(ur++)<<8) | RdMem(ur++);
598 if (tmp&0x20) yr = (RdMem(ur++)<<8) | RdMem(ur++);
599 if (tmp&0x40) sr = (RdMem(ur++)<<8) | RdMem(ur++);
600 if (tmp&0x80) pcr = (RdMem(ur++)<<8) | RdMem(ur++);
603 void Op39(void) // RTS
605 pcr = (RdMem(sr++)<<8) | RdMem(sr++);
608 void Op3A(void) // ABX
613 void Op3B(void) // RTI
616 if (ccr&0x80) // If E flag set, pull all regs
618 ar = RdMem(sr++); br = RdMem(sr++); dpr = RdMem(sr++);
619 xr = (RdMem(sr++)<<8) | RdMem(sr++);
620 yr = (RdMem(sr++)<<8) | RdMem(sr++);
621 ur = (RdMem(sr++)<<8) | RdMem(sr++);
628 pcr = (RdMem(sr++)<<8) | RdMem(sr++);
630 void Op3C(void) // CWAI
632 ccr &= Fetch(); ccr |= 0x80;
633 iclock += 1000000; // Force interrupt
635 void Op3D(void) // MUL
637 addr = ar * br; ar = addr>>8; br = addr&0xFF;
638 (addr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero
639 (br&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry
642 void Op3E(void) // RESET
645 void Op3F(void) // SWI
648 void Op40(void) // NEGA
651 (ar > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry
652 (ar == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
653 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
654 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
657 void Op43(void) // COMA
660 ccr &= 0xFD; ccr |= 0x01; // CLV, SEC
661 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
662 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
665 void Op44(void) // LSRA
667 (ar&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry
669 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
670 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
673 void Op46(void) // RORA
675 tmp = ar; ar = (tmp>>1) + (ccr&0x01)*128;
676 (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
677 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
678 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
681 void Op47(void) // ASRA
683 (ar&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
684 ar >>= 1; // Do the shift
685 if (ar&0x40) ar |= 0x80; // Set neg if it was set
686 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
687 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
690 void Op48(void) // LSLA [Keep checking from here...]
692 (ar&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
694 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
695 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
698 void Op49(void) // ROLA
700 tmp = ar; ar = (tmp<<1) + (ccr&0x01);
701 (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
702 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
703 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
706 void Op4A(void) // DECA
709 (ar == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
710 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
711 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
714 void Op4C(void) // INCA
717 (ar == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
718 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
719 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
722 void Op4D(void) // TSTA
724 ccr &= 0xFD; // Clear oVerflow flag
725 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
726 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
729 void Op4F(void) // CLRA
732 ccr &= 0xF0; ccr |= 0x04; // Set NZVC
735 void Op50(void) // NEGB
738 // ((br^tmp)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Adjust H carry
739 (br == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
740 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
741 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
742 (br > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry
745 void Op53(void) // COMB
748 ccr &= 0xFD; ccr |= 0x01; // CLV, SEC
749 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
750 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
753 void Op54(void) // LSRB
755 (br&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry
757 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
758 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
761 void Op56(void) // RORB
763 tmp = br; br = (br >> 1) + (ccr&0x01)*128;
764 (tmp&0x01 ? ccr |=0x01 : ccr &= 0xFE); // Shift bit into carry
765 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
766 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
769 void Op57(void) // ASRB
771 (br&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
772 br >>= 1; // Do the shift
773 if (br&0x40) br |= 0x80; // Set neg if it was set
774 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
775 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
778 void Op58(void) // LSLB
780 (br&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
782 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
783 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
786 void Op59(void) // ROLB
789 br = (tmp<<1) + (ccr&0x01);
790 (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
791 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
792 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
795 void Op5A(void) // DECB
798 (br == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
799 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
800 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
803 void Op5C(void) // INCB
806 (br == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
807 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
808 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
811 void Op5D(void) // TSTB
813 ccr &= 0xFD; // Clear oVerflow flag
814 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
815 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
818 void Op5F(void) // CLRB
821 ccr &= 0xF0; ccr |= 0x04; // Set NZVC
824 void Op60(void) // NEG IDX
826 addr = DecodeIDX(Fetch());
827 tmp = RdMem(addr); BYTE res = 256 - tmp;
829 // ((res^tmp)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Adjust H carry
830 (res == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
831 (res == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
832 (res&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
833 (res > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry
836 void Op63(void) // COM IDX
838 addr = DecodeIDX(Fetch());
839 tmp = RdMem(addr) ^ 0xFF;
841 ccr &= 0xFD; ccr |= 0x01; // CLV, SEC
842 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
843 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
846 void Op64(void) // LSR IDX
848 addr = DecodeIDX(Fetch());
850 (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry
851 tmp >>= 1; WrMem(addr, tmp);
853 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
856 void Op66(void) // ROR IDX
858 addr = DecodeIDX(Fetch());
859 tmp = RdMem(addr); BYTE tmp2 = tmp;
860 tmp = (tmp >> 1) + (ccr&0x01)*128;
862 (tmp2&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
863 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
864 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
867 void Op67(void) // ASR IDX
869 addr = DecodeIDX(Fetch());
871 (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
873 if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
875 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
876 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
879 void Op68(void) // LSL IDX
881 addr = DecodeIDX(Fetch());
883 (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
886 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
887 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
890 void Op69(void) // ROL IDX
892 BYTE tmp2 = RdMem(DecodeIDX(Fetch()));
893 tmp = (tmp2<<1) + (ccr&0x01);
895 (tmp2&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
896 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
897 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
900 void Op6A(void) // DEC IDX
903 addr = DecodeIDX(Fetch());
904 tmp = RdMem(addr) - 1;
906 (tmp == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
907 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
908 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
911 void Op6C(void) // INC IDX
913 addr = DecodeIDX(Fetch());
914 tmp = RdMem(addr) + 1;
916 (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
917 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
918 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
921 void Op6D(void) // TST IDX
923 tmp = RdMem(DecodeIDX(Fetch()));
924 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
925 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
928 void Op6E(void) // JMP IDX
930 pcr = DecodeIDX(Fetch());
933 void Op6F(void) // CLR IDX
935 addr = DecodeIDX(Fetch());
937 ccr &= 0xF0; ccr |= 0x04; // Set NZVC
940 void Op70(void) // NEG ABS
943 tmp = RdMem(addr); BYTE res = 256 - tmp;
945 (res == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
946 (res == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
947 (res&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
948 (res > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry
951 void Op73(void) // COM ABS
954 tmp = RdMem(addr) ^ 0xFF;
956 ccr &= 0xFD; ccr |= 0x01; // CLV, SEC
957 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
958 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
961 void Op74(void) // LSR ABS
965 (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry
966 tmp >>= 1; WrMem(addr, tmp);
968 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
971 void Op76(void) // ROR ABS
975 tmp = RdMem(addr); BYTE tmp2 = tmp;
976 tmp = (tmp >> 1) + (ccr&0x01)*128;
978 (tmp2&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
979 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
980 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
983 void Op77(void) // ASR ABS
988 (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry
990 if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set
992 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
993 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
996 void Op78(void) // LSL ABS
1001 (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
1004 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1005 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1008 void Op79(void) // ROL ABS
1010 BYTE tmp2 = RdMem(FetchW());
1011 tmp = (tmp2<<1) + (ccr&0x01);
1013 (tmp2&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry
1014 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1015 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1018 void Op7A(void) // DEC ABS
1020 BYTE tmp; WORD addr;
1022 tmp = RdMem(addr) - 1;
1024 (tmp == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
1025 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1026 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1029 void Op7C(void) // INC ABS
1031 BYTE tmp; WORD addr;
1033 tmp = RdMem(addr) + 1;
1035 (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag
1036 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1037 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1041 void Op7D(void) // TST ABS
1043 BYTE tmp = RdMem(FetchW());
1045 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1046 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1051 void Op7E(void) // JMP ABS
1056 void Op7F(void) // CLR ABS
1059 ccr &= 0xF0; ccr |= 0x04; // Set NZVC
1062 void Op80(void) // SUBA #
1064 BYTE tmp = Fetch(); BYTE as = ar;
1066 (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1067 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1068 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1069 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1072 void Op81(void) // CMPA #
1076 (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1077 ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1078 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1079 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1082 void Op82(void) // SBCA #
1084 tmp = Fetch(); BYTE as = ar;
1085 ar = ar - tmp - (ccr&0x01);
1086 (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1087 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1088 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1089 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1092 void Op83(void) // SUBD #
1094 addr = FetchW(); WORD dr = (ar<<8)|br, ds = dr;
1096 (ds < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1097 ((ds^addr^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1098 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1099 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1100 ar = dr>>8; br = dr&0xFF;
1103 void Op84(void) // ANDA #
1106 ccr &= 0xFD; // Clear oVerflow flag
1107 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1108 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1111 void Op85(void) // BITA #
1114 ccr &= 0xFD; // Clear oVerflow flag
1115 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1116 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1119 void Op86(void) // LDA #
1123 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1124 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1127 void Op88(void) // EORA #
1131 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1132 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1135 void Op89(void) // ADCA #
1138 addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01);
1139 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry
1140 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1141 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1142 ar = addr & 0xFF; // Set accumulator
1143 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero
1144 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative
1147 void Op8A(void) // ORA #
1151 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1152 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1155 void Op8B(void) // ADDA #
1157 tmp = Fetch(); addr = ar + tmp;
1158 (addr > 0xFF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1159 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1160 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1161 ar = addr & 0xFF; // Set accumulator
1162 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1163 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1166 void Op8C(void) // CMPX #
1169 WORD dw = xr - addr;
1170 (xr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1171 ((xr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
1172 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1173 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1176 void Op8D(void) // BSR
1179 WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8);
1180 pcr += SignedB(tmp);
1183 void Op8E(void) // LDX #
1187 (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1188 (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1191 void Op90(void) // SUBA DP
1193 tmp = RdMem((dpr<<8)|Fetch()); BYTE as = ar;
1195 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1196 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1197 (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1198 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1201 void Op91(void) // CMPA DP
1203 tmp = RdMem((dpr<<8)|Fetch());
1205 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1206 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1207 (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1208 ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1211 void Op92(void) // SBCA DP
1213 tmp = RdMem((dpr<<8)|Fetch()); BYTE as = ar;
1214 ar = ar - tmp - (ccr&0x01);
1215 (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1216 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1217 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1218 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1221 void Op93(void) // SUBD DP
1223 addr = (dpr<<8)|Fetch(); WORD dr = (ar<<8)|br, ds = dr;
1224 WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1);
1226 (ds < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1227 ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1228 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1229 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1230 ar = dr>>8; br = dr&0xFF;
1233 void Op94(void) // ANDA DP
1235 ar &= RdMem((dpr<<8)|Fetch());
1236 ccr &= 0xF1; // CLV CLZ CLN
1237 if (ar == 0) ccr |= 0x04; // Adjust Zero flag
1238 if (ar&0x80) ccr |= 0x08; // Adjust Negative flag
1241 void Op95(void) // BITA DP
1243 tmp = ar & RdMem((dpr<<8)|Fetch());
1244 ccr &= 0xFD; // Clear oVerflow flag
1245 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1246 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1249 void Op96(void) // LDA DP
1251 ar = RdMem((dpr<<8)|Fetch());
1252 ccr &= 0xF1; // CLN CLZ CLV
1253 if (ar == 0) ccr |= 0x04; // Set Zero flag
1254 if (ar&0x80) ccr |= 0x08; // Set Negative flag
1257 void Op97(void) // STA DP
1259 WrMem((dpr<<8)|Fetch(), ar);
1261 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1262 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1265 void Op98(void) // EORA DP
1267 ar ^= RdMem((dpr<<8)|Fetch());
1269 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1270 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1273 void Op99(void) // ADCA DP
1275 tmp = RdMem((dpr<<8)|Fetch());
1276 addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01);
1277 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry
1278 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1279 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1280 ar = addr & 0xFF; // Set accumulator
1281 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero
1282 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative
1285 void Op9A(void) // ORA DP
1287 ar |= RdMem((dpr<<8)|Fetch());
1289 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1290 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1293 void Op9B(void) // ADDA DP
1295 tmp = RdMem((dpr<<8)|Fetch());
1296 addr = (WORD)ar + (WORD)tmp;
1297 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1298 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1299 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
1300 ar = addr & 0xFF; // Set accumulator
1301 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1302 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1305 void Op9C(void) // CMPX DP
1307 addr = (dpr<<8)|Fetch();
1308 WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1);
1309 WORD dw = xr - adr2;
1310 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1311 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1312 (xr < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1313 ((xr^adr2^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
1316 void Op9D(void) // JSR DP
1318 addr = (dpr<<8) | Fetch();
1319 WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8);
1320 pcr = addr; // JSR to DP location...
1323 void Op9E(void) // LDX DP
1325 addr = (dpr<<8) | Fetch();
1326 xr = (RdMem(addr) << 8) | RdMem(addr+1);
1328 (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1329 (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1332 void Op9F(void) // STX DP
1334 addr = (dpr<<8) | Fetch();
1335 WrMem(addr, xr>>8); WrMem(addr+1, xr&0xFF);
1337 (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1338 (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1341 void OpA0(void) // SUBA IDX
1343 tmp = RdMem(DecodeIDX(Fetch())); BYTE as = ar;
1345 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1346 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1347 (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1348 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1351 void OpA1(void) // CMPA IDX
1353 tmp = RdMem(DecodeIDX(Fetch()));
1355 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1356 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1357 (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1358 ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1361 void OpA2(void) // SBCA IDX
1363 tmp = RdMem(DecodeIDX(Fetch())); BYTE as = ar;
1364 ar = ar - tmp - (ccr&0x01);
1365 (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1366 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1367 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1368 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1371 void OpA3(void) // SUBD IDX
1373 addr = DecodeIDX(Fetch()); WORD dr = (ar<<8)|br, ds = dr;
1374 WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1);
1376 (ds < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1377 ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1378 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1379 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1380 ar = dr>>8; br = dr&0xFF;
1383 void OpA4(void) // ANDA IDX
1385 ar &= RdMem(DecodeIDX(Fetch()));
1386 ccr &= 0xFD; // Clear oVerflow flag
1387 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1388 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1391 void OpA5(void) // BITA IDX
1393 tmp = ar & RdMem(DecodeIDX(Fetch()));
1394 ccr &= 0xFD; // Clear oVerflow flag
1395 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1396 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1399 void OpA6(void) // LDA IDX
1401 ar = RdMem(DecodeIDX(Fetch()));
1402 ccr &= 0xF1; // CLV CLZ CLN
1403 if (ar == 0) ccr |= 0x04; // Set Zero flag
1404 if (ar&0x80) ccr |= 0x08; // Set Negative flag
1407 void OpA7(void) // STA IDX
1409 WrMem(DecodeIDX(Fetch()), ar);
1410 ccr &= 0xF1; // CLV CLZ CLN
1411 if (ar == 0) ccr |= 0x04; // Set Zero flag
1412 if (ar&0x80) ccr |= 0x08; // Set Negative flag
1415 void OpA8(void) // EORA IDX
1417 ar ^= RdMem(DecodeIDX(Fetch()));
1419 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1420 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1423 void OpA9(void) // ADCA IDX
1425 tmp = RdMem(DecodeIDX(Fetch()));
1426 addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01);
1427 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1428 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1429 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
1430 ar = addr & 0xFF; // Set accumulator
1431 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1432 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1435 void OpAA(void) // ORA IDX
1437 ar |= RdMem(DecodeIDX(Fetch()));
1439 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1440 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1443 void OpAB(void) // ADDA IDX
1445 tmp = RdMem(DecodeIDX(Fetch()));
1446 addr = (WORD)ar + (WORD)tmp;
1447 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1448 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1449 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
1450 ar = addr & 0xFF; // Set accumulator
1451 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1452 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1455 void OpAC(void) // CMPX IDX
1457 addr = DecodeIDX(Fetch());
1458 WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1);
1459 WORD dw = xr - addr2;
1460 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1461 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1462 (xr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1463 ((xr^addr2^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1466 void OpAD(void) // JSR IDX
1468 addr = DecodeIDX(Fetch());
1469 WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8);
1470 pcr = addr; // JSR directly to IDX ptr
1473 void OpAE(void) // LDX IDX
1475 addr = DecodeIDX(Fetch());
1476 xr = (RdMem(addr) << 8) | RdMem(addr+1);
1478 (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1479 (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1482 void OpAF(void) // STX IDX
1484 addr = DecodeIDX(Fetch());
1485 WrMem(addr, xr>>8); WrMem(addr+1, xr&0xFF);
1486 ccr &= 0xF1; // CLV CLZ CLN
1487 if (xr == 0) ccr |= 0x04; // Set Zero flag
1488 if (xr&0x8000) ccr |= 0x08; // Set Negative flag
1491 void OpB0(void) // SUBA ABS
1493 tmp = RdMem(FetchW()); BYTE as = ar;
1495 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1496 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1497 (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1498 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1501 void OpB1(void) // CMPA ABS
1503 tmp = RdMem(FetchW());
1505 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1506 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1507 (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1508 ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1511 void OpB2(void) // SBCA ABS
1513 tmp = RdMem(FetchW()); BYTE as = ar;
1514 ar = ar - tmp - (ccr&0x01);
1515 (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1516 ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1517 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1518 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1521 void OpB3(void) // SUBD ABS
1523 addr = FetchW(); WORD dr = (ar<<8)|br, ds = dr;
1524 WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1);
1526 (ds < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1527 ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
1528 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1529 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1530 ar = dr>>8; br = dr&0xFF;
1533 void OpB4(void) // ANDA ABS
1535 ar &= RdMem(FetchW());
1536 ccr &= 0xFD; // Clear oVerflow flag
1537 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1538 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1541 void OpB5(void) // BITA ABS
1543 tmp = ar & RdMem(FetchW());
1544 ccr &= 0xFD; // Clear oVerflow flag
1545 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1546 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1549 void OpB6(void) // LDA ABS
1551 ar = RdMem(FetchW());
1553 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1554 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1557 void OpB7(void) // STA ABS
1559 WrMem(FetchW(), ar);
1561 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1562 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1565 void OpB8(void) // EORA ABS
1567 ar ^= RdMem(FetchW());
1569 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1570 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1573 void OpB9(void) // ADCA ABS
1575 tmp = RdMem(FetchW());
1576 addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01);
1577 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1578 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1579 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1580 ar = addr; // Set accumulator
1581 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1582 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1585 void OpBA(void) // ORA ABS
1587 ar |= RdMem(FetchW());
1589 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1590 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1593 void OpBB(void) // ADDA ABS
1595 tmp = RdMem(FetchW());
1596 addr = (WORD)ar + (WORD)tmp;
1597 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1598 ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1599 ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
1600 ar = addr & 0xFF; // Set accumulator
1601 (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1602 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1605 void OpBC(void) // CMPX ABS
1607 addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1);
1608 WORD dw = xr - addr2;
1609 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1610 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1611 (xr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1612 ((xr^addr2^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1615 void OpBD(void) // JSR ABS
1618 WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8);
1619 pcr = addr; // Go to absolute address (Not indir)
1622 void OpBE(void) // LDX ABS
1625 xr = (RdMem(addr) << 8) | RdMem(addr+1);
1627 (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1628 (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1631 void OpBF(void) // STX ABS
1634 WrMem(addr, xr>>8); WrMem(addr+1, xr&0xFF);
1636 (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1637 (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1640 void OpC0(void) // SUBB #
1642 tmp = Fetch(); BYTE bs = br;
1644 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1645 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1646 (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1647 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1650 void OpC1(void) // CMPB #
1654 (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1655 ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1656 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1657 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1660 void OpC2(void) // SBCB #
1662 tmp = Fetch(); BYTE bs = br;
1663 br = br - tmp - (ccr&0x01);
1664 (bs < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1665 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1666 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1667 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1670 void OpC3(void) // ADDD #
1672 addr = FetchW(); long dr = ((ar<<8)|br)&0xFFFF, ds = dr;
1674 (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1676 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1677 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1678 ((ds^addr^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
1679 ar = dr>>8; br = dr&0xFF;
1682 void OpC4(void) // ANDB #
1685 ccr &= 0xFD; // Clear oVerflow flag
1686 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1687 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1690 void OpC5(void) // BITB #
1693 ccr &= 0xF1; // CLV CLZ CLN
1694 if (tmp == 0) ccr |= 0x04; // Set Zero flag
1695 if (tmp&0x80) ccr |= 0x08; // Set Negative flag
1698 void OpC6(void) // LDB #
1701 ccr &= 0xF1; // CLV CLZ CLN
1702 if (br == 0) ccr |= 0x04; // Set Zero flag
1703 if (br&0x80) ccr |= 0x08; // Set Negative flag
1706 void OpC8(void) // EORB #
1710 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1711 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1714 void OpC9(void) // ADCB #
1717 addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01);
1718 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1719 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1720 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
1721 br = addr & 0xFF; // Set accumulator
1722 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1723 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1726 void OpCA(void) // ORB #
1730 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1731 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1734 void OpCB(void) // ADDB #
1736 tmp = Fetch(); addr = br + tmp;
1737 (addr > 0xFF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1738 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1739 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
1740 br = addr & 0xFF; // Set accumulator
1741 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1742 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1745 void OpCC(void) // LDD #
1747 ar = Fetch(); br = Fetch();
1749 ((ar+br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1750 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1753 void OpCE(void) // LDU #
1757 (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1758 (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1761 void OpD0(void) // SUBB DP
1763 tmp = RdMem((dpr<<8)|Fetch()); BYTE bs = br;
1765 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1766 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1767 (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1768 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1771 void OpD1(void) // CMPB DP
1773 tmp = RdMem((dpr<<8)|Fetch());
1775 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1776 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1777 (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1778 ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1781 void OpD2(void) // SBCB DP
1783 tmp = RdMem((dpr<<8)|Fetch()); BYTE bs = br;
1784 br = br - tmp - (ccr&0x01);
1785 (bs < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1786 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1787 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1788 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1791 void OpD3(void) // ADDD DP
1793 addr = (dpr<<8)|Fetch(); long dr = ((ar<<8)|br)&0xFFFF, ds = dr;
1794 WORD adr2 = (RdMem(addr)<<8)|RdMem(addr+1);
1796 (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1798 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1799 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1800 ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1801 ar = dr>>8; br = dr&0xFF;
1804 void OpD4(void) // ANDB DP
1806 br &= RdMem((dpr<<8)|Fetch());
1807 ccr &= 0xFD; // Clear oVerflow flag
1808 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1809 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1812 void OpD5(void) // BITB DP
1814 tmp = br & RdMem((dpr<<8)|Fetch());
1815 ccr &= 0xFD; // Clear oVerflow flag
1816 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1817 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1820 void OpD6(void) // LDB DP
1822 br = RdMem((dpr<<8)|Fetch());
1824 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1825 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1828 void OpD7(void) // STB DP
1830 WrMem((dpr<<8)|Fetch(), br);
1832 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1833 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1836 void OpD8(void) // EORB DP
1838 br ^= RdMem((dpr<<8)|Fetch());
1840 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1841 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1844 void OpD9(void) // ADCB DP
1846 tmp = RdMem((dpr<<8)|Fetch());
1847 addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01);
1848 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1849 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1850 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1851 br = addr; // Set accumulator
1852 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1853 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1856 void OpDA(void) // ORB DP
1858 br |= RdMem((dpr<<8)|Fetch());
1860 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1861 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1864 void OpDB(void) // ADDB DP
1866 tmp = RdMem((dpr<<8)|Fetch());
1867 addr = (WORD)br + (WORD)tmp;
1868 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
1869 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
1870 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1871 br = addr & 0xFF; // Set accumulator
1872 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
1873 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
1876 void OpDC(void) // LDD DP
1878 addr = (dpr<<8)|Fetch();
1879 ar = RdMem(addr); br = RdMem(addr+1);
1881 ((ar|br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1882 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1885 void OpDD(void) // STD DP
1887 addr = (dpr<<8)|Fetch();
1888 WrMem(addr, ar); WrMem(addr+1, br);
1890 ((ar|br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1891 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1894 void OpDE(void) // LDU DP
1896 addr = (dpr<<8)|Fetch();
1897 ur = (RdMem(addr) << 8) | RdMem(addr+1);
1899 (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1900 (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1903 void OpDF(void) // STU DP
1905 addr = (dpr<<8)|Fetch();
1906 WrMem(addr, ur>>8); WrMem(addr+1, ur&0xFF);
1908 (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1909 (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1912 void OpE0(void) // SUBB IDX
1914 tmp = RdMem(DecodeIDX(Fetch())); BYTE bs = br;
1916 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1917 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1918 (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1919 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1922 void OpE1(void) // CMPB IDX
1924 tmp = RdMem(DecodeIDX(Fetch()));
1926 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1927 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1928 (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1929 ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1932 void OpE2(void) // SBCB IDX
1934 tmp = RdMem(DecodeIDX(Fetch())); BYTE bs = br;
1935 br = br - tmp - (ccr&0x01);
1936 (bs < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1937 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1938 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1939 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1942 void OpE3(void) // ADDD IDX
1944 addr = DecodeIDX(Fetch()); long dr = ((ar<<8)|br)&0xFFFF, ds = dr;
1945 WORD adr2 = (RdMem(addr)<<8)|RdMem(addr+1);
1947 (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
1949 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1950 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1951 ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
1952 ar = dr>>8; br = dr&0xFF;
1955 void OpE4(void) // ANDB IDX
1957 br &= RdMem(DecodeIDX(Fetch()));
1958 ccr &= 0xFD; // Clear oVerflow flag
1959 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1960 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1963 void OpE5(void) // BITB IDX
1965 tmp = br & RdMem(DecodeIDX(Fetch()));
1966 ccr &= 0xFD; // Clear oVerflow flag
1967 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1968 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1971 void OpE6(void) // LDB IDX
1973 br = RdMem(DecodeIDX(Fetch()));
1975 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1976 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1979 void OpE7(void) // STB IDX
1981 WrMem(DecodeIDX(Fetch()), br);
1982 ccr &= 0xF1; // CLV CLZ CLN
1983 if (br == 0) ccr |= 0x04; // Adjust Zero flag
1984 if (br&0x80) ccr |= 0x08; // Adjust Negative flag
1987 void OpE8(void) // EORB IDX
1989 br ^= RdMem(DecodeIDX(Fetch()));
1991 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
1992 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
1995 void OpE9(void) // ADCB IDX
1997 tmp = RdMem(DecodeIDX(Fetch()));
1998 addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01);
1999 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
2000 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
2001 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
2002 br = addr; // Set accumulator
2003 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
2004 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
2007 void OpEA(void) // ORB IDX
2009 br |= RdMem(DecodeIDX(Fetch()));
2011 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2012 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2015 void OpEB(void) // ADDB IDX
2017 tmp = RdMem(DecodeIDX(Fetch()));
2018 addr = (WORD)br + (WORD)tmp;
2019 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
2020 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
2021 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
2022 br = addr; // Set accumulator
2023 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
2024 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
2027 void OpEC(void) // LDD IDX
2029 addr = DecodeIDX(Fetch());
2030 ar = RdMem(addr); br = RdMem(addr+1);
2031 ccr &= 0xF1; // CLV CLZ CLN
2032 if (!(ar|br)) ccr |= 0x04; // Adjust Zero flag
2033 if (ar&0x80) ccr |= 0x08; // Adjust Negative flag
2036 void OpED(void) // STD IDX
2038 addr = DecodeIDX(Fetch());
2039 WrMem(addr, ar); WrMem(addr+1, br);
2040 ccr &= 0xF1; // CLV CLZ CLZ
2041 if (!(ar|br)) ccr |= 0x04; // Adjust Zero flag
2042 if (ar&0x80) ccr |= 0x08; // Adjust Negative flag
2045 void OpEE(void) // LDU IDX
2047 addr = DecodeIDX(Fetch());
2048 ur = (RdMem(addr) << 8) | RdMem(addr+1);
2049 ccr &= 0xF1; // CLV CLZ CLN
2050 if (ur == 0) ccr |= 0x04; // Set Zero flag
2051 if (ur&0x8000) ccr |= 0x08; // Set Negative flag
2054 void OpEF(void) // STU IDX
2056 addr = DecodeIDX(Fetch());
2057 WrMem(addr, ur>>8); WrMem(addr+1, ur&0xFF);
2058 ccr &= 0xF1; // CLV CLZ CLN
2059 if (ur == 0) ccr |= 0x04; // Set Zero flag
2060 if (ur&0x8000) ccr |= 0x08; // Set Negative flag
2063 void OpF0(void) // SUBB ABS
2065 tmp = RdMem(FetchW()); BYTE bs = br;
2067 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2068 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2069 (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2070 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
2072 void OpF1(void) // CMPB ABS
2074 tmp = RdMem(FetchW());
2076 (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2077 (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2078 (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2079 ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
2082 void OpF2(void) // SBCB ABS
2084 tmp = RdMem(FetchW()); BYTE bs = br;
2085 br = br - tmp - (ccr&0x01);
2086 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2087 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2088 (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2089 ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow
2092 void OpF3(void) // ADDD ABS
2094 addr = FetchW(); long dr = ((ar<<8)|br)&0xFFFF, ds = dr;
2095 WORD adr2 = (RdMem(addr)<<8)|RdMem(addr+1);
2097 (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2099 (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2100 (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2101 ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2102 ar = dr>>8; br = dr&0xFF;
2105 void OpF4(void) // ANDB ABS
2107 br &= RdMem(FetchW());
2108 ccr &= 0xFD; // Clear oVerflow flag
2109 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2110 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2113 void OpF5(void) // BITB ABS
2115 tmp = br & RdMem(FetchW());
2116 ccr &= 0xFD; // Clear oVerflow flag
2117 (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2118 (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2121 void OpF6(void) // LDB ABS
2123 br = RdMem(FetchW());
2125 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2126 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2129 void OpF7(void) // STB ABS
2131 WrMem(FetchW(), br);
2133 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2134 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2137 void OpF8(void) // EORB ABS
2139 br ^= RdMem(FetchW());
2141 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2142 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2145 void OpF9(void) // ADCB ABS
2147 tmp = RdMem(FetchW());
2148 addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01);
2149 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
2150 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
2151 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
2152 br = addr & 0xFF; // Set accumulator
2153 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
2154 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
2157 void OpFA(void) // ORB ABS
2159 br |= RdMem(FetchW());
2161 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2162 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2165 void OpFB(void) // ADDB ABS
2167 tmp = RdMem(FetchW());
2168 addr = (WORD)br + (WORD)tmp;
2169 (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag
2170 ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry
2171 ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo
2172 br = addr & 0xFF; // Set accumulator
2173 (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag
2174 (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag
2177 void OpFC(void) // LDD ABS
2180 ar = RdMem(addr); br = RdMem(addr+1);
2182 ((ar+br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2183 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2186 void OpFD(void) // STD ABS
2189 WrMem(addr, ar); WrMem(addr+1, br);
2191 ((ar+br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2192 (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2195 void OpFE(void) // LDU ABS
2198 ur = (RdMem(addr) << 8) | RdMem(addr+1);
2200 (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2201 (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2204 void OpFF(void) // STU ABS
2207 WrMem(addr, ur>>8); WrMem(addr+1, ur&0xFF);
2209 (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2210 (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2215 // Page one opcodes' execute code
2218 void Op1021(void) // LBRN
2223 void Op1022(void) // LBHI
2226 if (!((ccr&0x01)|(ccr&0x04))) pcr += SignedW(addr);
2229 void Op1023(void) // LBLS
2232 if ((ccr&0x01)|(ccr&0x04)) pcr += SignedW(addr);
2235 void Op1024(void) // LBCC (LBHS)
2238 if (!(ccr&0x01)) pcr += SignedW(addr);
2241 void Op1025(void) // LBCS (LBLO)
2244 if (ccr&0x01) pcr += SignedW(addr);
2247 void Op1026(void) // LBNE
2250 if (!(ccr&0x04)) pcr += SignedW(addr);
2253 void Op1027(void) // LBEQ
2256 if (ccr&0x04) pcr += SignedW(addr);
2259 void Op1028(void) // LBVC
2262 if (!(ccr&0x02)) pcr += SignedW(addr);
2265 void Op1029(void) // LBVS
2268 if (ccr&0x02) pcr += SignedW(addr);
2271 void Op102A(void) // LBPL
2274 if (!(ccr&0x08)) pcr += SignedW(addr);
2277 void Op102B(void) // LBMI
2280 if (ccr&0x08) pcr += SignedW(addr);
2283 void Op102C(void) // LBGE
2286 if (!(((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedW(addr);
2289 void Op102D(void) // LBLT
2292 if (((ccr&0x08) >> 2) ^ (ccr&0x02)) pcr += SignedW(addr);
2295 void Op102E(void) // LBGT
2298 if (!((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02)))) pcr += SignedW(addr);
2301 void Op102F(void) // LBLE
2304 if ((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedW(addr);
2307 void Op103F(void) // SWI2 (Not yet implemented)
2311 void Op1083(void) // CMPD #
2313 addr = FetchW(); WORD dr = (ar<<8)|br;
2314 WORD dw = dr - addr;
2315 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2316 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2317 (dr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2318 ((dr^addr^dw^((WORD)ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2321 void Op108C(void) // CMPY #
2324 WORD dw = yr - addr;
2325 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2326 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2327 (yr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2328 ((yr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2331 void Op108E(void) // LDY #
2335 (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2336 (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2339 void Op1093(void) // CMPD DP
2341 WORD adr2 = (dpr<<8)|Fetch(), dr = (ar<<8)|br;
2342 addr = (RdMem(adr2)<<8) | RdMem(adr2+1);
2343 WORD dw = dr - addr;
2344 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2345 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2346 (dr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2347 ((dr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2350 void Op109C(void) // CMPY DP
2352 WORD adr2 = (dpr<<8)|Fetch();
2353 addr = (RdMem(adr2)<<8) | RdMem(adr2+1);
2354 WORD dw = yr - addr;
2355 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2356 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2357 (yr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2358 ((yr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2361 void Op109E(void) // LDY DP
2363 addr = (dpr<<8)|Fetch();
2364 yr = (RdMem(addr)<<8) | RdMem(addr+1);
2366 (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2367 (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2370 void Op109F(void) // STY DP
2372 addr = (dpr<<8)|Fetch();
2373 WrMem(addr, yr>>8); WrMem(addr+1, yr&0xFF);
2375 (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2376 (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2379 void Op10A3(void) // CMPD IDX
2381 WORD adr2 = DecodeIDX(Fetch()), dr = (ar<<8)|br;
2382 addr = (RdMem(adr2)<<8) | RdMem(adr2+1);
2383 WORD dw = dr - addr;
2384 ccr &= 0xF0; // CLC CLV CLZ CLN
2385 if (dr < addr) ccr |= 0x01; // Set Carry flag
2386 if ((dr^addr^dw^(ccr<<15))&0x8000) ccr |= 0x02; // Set oVerflow
2387 if (dw == 0) ccr |= 0x04; // Set Zero flag
2388 if (dw&0x8000) ccr |= 0x08; // Set Negative flag
2391 void Op10AC(void) // CMPY IDX
2393 WORD adr2 = DecodeIDX(Fetch());
2394 addr = (RdMem(adr2)<<8) | RdMem(adr2+1);
2395 WORD dw = yr - addr;
2396 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2397 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2398 (yr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2399 (((ccr<<15)^yr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2402 void Op10AE(void) // LDY IDX
2404 addr = DecodeIDX(Fetch());
2405 yr = (RdMem(addr)<<8) | RdMem(addr+1);
2406 ccr &= 0xF1; // CLV CLZ CLN
2407 if (yr == 0) ccr |= 0x04; // Adjust Zero flag
2408 if (yr&0x8000) ccr |= 0x08; // Adjust Negative flag
2411 void Op10AF(void) // STY IDX
2413 addr = DecodeIDX(Fetch());
2414 WrMem(addr, yr>>8); WrMem(addr+1, yr&0xFF);
2416 (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2417 (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2420 void Op10B3(void) // CMPD ABS
2422 addr = FetchW(); WORD dr = (ar<<8)|br;
2423 WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1);
2424 WORD dw = dr - addr2;
2425 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2426 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2427 (dr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2428 (((ccr<<15)^dr^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2431 void Op10BC(void) // CMPY ABS
2433 addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1);
2434 WORD dw = yr - addr2;
2435 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2436 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2437 (yr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2438 (((ccr<<15)^yr^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2441 void Op10BE(void) // LDY ABS
2444 yr = (RdMem(addr)<<8) | RdMem(addr+1);
2446 (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2447 (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2450 void Op10BF(void) // STY ABS
2453 WrMem(addr, yr>>8); WrMem(addr+1, yr&0xFF);
2455 (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2456 (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2459 void Op10CE(void) // LDS #
2463 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2464 (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2467 void Op10DE(void) // LDS DP
2469 addr = (dpr<<8)|Fetch();
2470 sr = (RdMem(addr)<<8) | RdMem(addr+1);
2472 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2473 (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2476 void Op10DF(void) // STS DP
2478 addr = (dpr<<8)|Fetch();
2479 WrMem(addr, sr>>8); WrMem(addr+1, sr&0xFF);
2481 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2482 (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2485 void Op10EE(void) // LDS IDX
2487 addr = DecodeIDX(Fetch());
2488 sr = (RdMem(addr)<<8) | RdMem(addr+1);
2490 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2491 (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2494 void Op10EF(void) // STS IDX
2496 addr = DecodeIDX(Fetch());
2497 WrMem(addr, sr>>8); WrMem(addr+1, sr&0xFF);
2499 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2500 (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2503 void Op10FE(void) // LDS ABS
2506 sr = (RdMem(addr)<<8) | RdMem(addr+1);
2508 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2509 (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2512 void Op10FF(void) // STS ABS
2515 WrMem(addr, sr>>8); WrMem(addr+1, sr&0xFF);
2517 (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2518 (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2523 // Page two opcodes' execute code
2526 void Op113F(void) // SWI3
2530 void Op1183(void) // CMPU #
2533 WORD dw = ur - addr;
2534 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2535 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2536 (ur < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2537 (((ccr<<15)^ur^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2540 void Op118C(void) // CMPS #
2543 WORD dw = sr - addr;
2544 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2545 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2546 (sr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2547 (((ccr<<15)^sr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2550 void Op1193(void) // CMPU DP
2552 WORD adr2 = (dpr<<8)|Fetch();
2553 addr = (RdMem(adr2)<<8) | RdMem(adr2+1);
2554 WORD dw = ur - addr;
2555 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2556 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2557 (ur < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2558 (((ccr<<15)^ur^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2561 void Op119C(void) // CMPS DP
2563 WORD adr2 = (dpr<<8)|Fetch();
2564 addr = (RdMem(adr2)<<8) | RdMem(adr2+1);
2565 WORD dw = sr - addr;
2566 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2567 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2568 (sr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2569 (((ccr<<15)^sr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2572 void Op11A3(void) // CMPU IDX
2574 WORD addr2 = DecodeIDX(Fetch());
2575 addr = (RdMem(addr2)<<8) | RdMem(addr2+1);
2576 WORD dw = ur - addr;
2577 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2578 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2579 (ur < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2580 (((ccr<<15)^ur^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2583 void Op11AC(void) // CMPS IDX
2585 WORD addr2 = DecodeIDX(Fetch());
2586 addr = (RdMem(addr2)<<8) | RdMem(addr2+1);
2587 WORD dw = sr - addr;
2588 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2589 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2590 (sr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2591 (((ccr<<15)^sr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2594 void Op11B3(void) // CMPU ABS
2596 addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1);
2597 WORD dw = ur - addr2;
2598 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2599 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2600 (ur < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2601 (((ccr<<15)^ur^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2605 void Op11BC(void) // CMPS ABS
2607 addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1);
2608 WORD dw = sr - addr2;
2609 (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag
2610 (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag
2611 (sr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag
2612 (((ccr<<15)^sr^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl
2616 void IllegalOp(void)
2632 // Array of page zero opcode functions...
2633 void (* exec_op0[256])() = {
2634 Op00, Op__, Op__, Op03, Op04, Op__, Op06, Op07, Op08, Op09, Op0A, Op__, Op0C, Op0D, Op0E, Op0F,
2635 Op__, Op__, Op12, Op13, Op__, Op__, Op16, Op17, Op__, Op19, Op1A, Op__, Op1C, Op1D, Op1E, Op1F,
2636 Op20, Op21, Op22, Op23, Op24, Op25, Op26, Op27, Op28, Op29, Op2A, Op2B, Op2C, Op2D, Op2E, Op2F,
2637 Op30, Op31, Op32, Op33, Op34, Op35, Op36, Op37, Op__, Op39, Op3A, Op3B, Op3C, Op3D, Op3E, Op3F,
2638 Op40, Op__, Op__, Op43, Op44, Op__, Op46, Op47, Op48, Op49, Op4A, Op__, Op4C, Op4D, Op__, Op4F,
2639 Op50, Op__, Op__, Op53, Op54, Op__, Op56, Op57, Op58, Op59, Op5A, Op__, Op5C, Op5D, Op__, Op5F,
2640 Op60, Op__, Op__, Op63, Op64, Op__, Op66, Op67, Op68, Op69, Op6A, Op__, Op6C, Op6D, Op6E, Op6F,
2641 Op70, Op__, Op__, Op73, Op74, Op__, Op76, Op77, Op78, Op79, Op7A, Op__, Op7C, Op7D, Op7E, Op7F,
2642 Op80, Op81, Op82, Op83, Op84, Op85, Op86, Op__, Op88, Op89, Op8A, Op8B, Op8C, Op8D, Op8E, Op__,
2643 Op90, Op91, Op92, Op93, Op94, Op95, Op96, Op97, Op98, Op99, Op9A, Op9B, Op9C, Op9D, Op9E, Op9F,
2644 OpA0, OpA1, OpA2, OpA3, OpA4, OpA5, OpA6, OpA7, OpA8, OpA9, OpAA, OpAB, OpAC, OpAD, OpAE, OpAF,
2645 OpB0, OpB1, OpB2, OpB3, OpB4, OpB5, OpB6, OpB7, OpB8, OpB9, OpBA, OpBB, OpBC, OpBD, OpBE, OpBF,
2646 OpC0, OpC1, OpC2, OpC3, OpC4, OpC5, OpC6, Op__, OpC8, OpC9, OpCA, OpCB, OpCC, Op__, OpCE, Op__,
2647 OpD0, OpD1, OpD2, OpD3, OpD4, OpD5, OpD6, OpD7, OpD8, OpD9, OpDA, OpDB, OpDC, OpDD, OpDE, OpDF,
2648 OpE0, OpE1, OpE2, OpE3, OpE4, OpE5, OpE6, OpE7, OpE8, OpE9, OpEA, OpEB, OpEC, OpED, OpEE, OpEF,
2649 OpF0, OpF1, OpF2, OpF3, OpF4, OpF5, OpF6, OpF7, OpF8, OpF9, OpFA, OpFB, OpFC, OpFD, OpFE, OpFF
2652 // Array of page one opcode functions...
2653 void (* exec_op1[256])() = {
2654 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2655 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2656 Op__, Op1021, Op1022, Op1023, Op1024, Op1025, Op1026, Op1027, Op1028, Op1029, Op102A, Op102B, Op102C, Op102D, Op102E, Op102F,
2657 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op103F,
2658 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2659 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2660 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2661 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2662 Op__, Op__, Op__, Op1083, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op108C, Op__, Op108E, Op__,
2663 Op__, Op__, Op__, Op1093, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op109C, Op__, Op109E, Op109F,
2664 Op__, Op__, Op__, Op10A3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10AC, Op__, Op10AE, Op10AF,
2665 Op__, Op__, Op__, Op10B3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10BC, Op__, Op10BE, Op10BF,
2666 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10CE, Op__,
2667 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10DE, Op10DF,
2668 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10EE, Op10EF,
2669 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10FE, Op10FF
2671 // Array of page two opcode functions...
2672 void (* exec_op2[256])() = {
2673 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2674 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2675 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2676 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op113F,
2677 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2678 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2679 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2680 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2681 Op__, Op__, Op__, Op1183, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op118C, Op__, Op__, Op__,
2682 Op__, Op__, Op__, Op1193, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op119C, Op__, Op__, Op__,
2683 Op__, Op__, Op__, Op11A3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op11AC, Op__, Op__, Op__,
2684 Op__, Op__, Op__, Op11B3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op11BC, Op__, Op__, Op__,
2685 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2686 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2687 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__,
2688 Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__
2692 // Initialize 6809 function adressess
2695 void Init_6809(void)
2699 for(int i=0; i<256; i++) // Set all functions to illegal
2700 exec_op0[i] = exec_op1[i] = exec_op2[i] = IllegalOp;
2702 exec_op0[0x00] = Op00; exec_op0[0x03] = Op03; exec_op0[0x04] = Op04;
2703 exec_op0[0x06] = Op06; exec_op0[0x07] = Op07; exec_op0[0x08] = Op08;
2704 exec_op0[0x09] = Op09; exec_op0[0x0A] = Op0A; exec_op0[0x0C] = Op0C;
2705 exec_op0[0x0D] = Op0D; exec_op0[0x0E] = Op0E; exec_op0[0x0F] = Op0F;
2706 exec_op0[0x12] = Op12; exec_op0[0x13] = Op13; exec_op0[0x16] = Op16;
2707 exec_op0[0x17] = Op17; exec_op0[0x19] = Op19; exec_op0[0x1A] = Op1A;
2708 exec_op0[0x1C] = Op1C; exec_op0[0x1D] = Op1D; exec_op0[0x1E] = Op1E;
2709 exec_op0[0x1F] = Op1F; exec_op0[0x20] = Op20; exec_op0[0x21] = Op21;
2710 exec_op0[0x22] = Op22; exec_op0[0x23] = Op23; exec_op0[0x24] = Op24;
2711 exec_op0[0x25] = Op25; exec_op0[0x26] = Op26; exec_op0[0x27] = Op27;
2712 exec_op0[0x28] = Op28; exec_op0[0x29] = Op29; exec_op0[0x2A] = Op2A;
2713 exec_op0[0x2B] = Op2B; exec_op0[0x2C] = Op2C; exec_op0[0x2D] = Op2D;
2714 exec_op0[0x2E] = Op2E; exec_op0[0x2F] = Op2F; exec_op0[0x30] = Op30;
2715 exec_op0[0x31] = Op31; exec_op0[0x32] = Op32; exec_op0[0x33] = Op33;
2716 exec_op0[0x34] = Op34; exec_op0[0x35] = Op35; exec_op0[0x36] = Op36;
2717 exec_op0[0x37] = Op37; exec_op0[0x39] = Op39; exec_op0[0x3A] = Op3A;
2718 exec_op0[0x3B] = Op3B; exec_op0[0x3C] = Op3C; exec_op0[0x3D] = Op3D;
2719 exec_op0[0x3E] = Op3E; exec_op0[0x3F] = Op3F; exec_op0[0x40] = Op40;
2720 exec_op0[0x43] = Op43; exec_op0[0x44] = Op44; exec_op0[0x46] = Op46;
2721 exec_op0[0x47] = Op47; exec_op0[0x48] = Op48; exec_op0[0x49] = Op49;
2722 exec_op0[0x4A] = Op4A; exec_op0[0x4C] = Op4C; exec_op0[0x4D] = Op4D;
2723 exec_op0[0x4F] = Op4F; exec_op0[0x50] = Op50; exec_op0[0x53] = Op53;
2724 exec_op0[0x54] = Op54; exec_op0[0x56] = Op56; exec_op0[0x57] = Op57;
2725 exec_op0[0x58] = Op58; exec_op0[0x59] = Op59; exec_op0[0x5A] = Op5A;
2726 exec_op0[0x5C] = Op5C; exec_op0[0x5D] = Op5D; exec_op0[0x5F] = Op5F;
2727 exec_op0[0x60] = Op60; exec_op0[0x63] = Op63; exec_op0[0x64] = Op64;
2728 exec_op0[0x66] = Op66; exec_op0[0x67] = Op67; exec_op0[0x68] = Op68;
2729 exec_op0[0x69] = Op69; exec_op0[0x6A] = Op6A; exec_op0[0x6C] = Op6C;
2730 exec_op0[0x6D] = Op6D; exec_op0[0x6E] = Op6E; exec_op0[0x6F] = Op6F;
2731 exec_op0[0x70] = Op70; exec_op0[0x73] = Op73; exec_op0[0x74] = Op74;
2732 exec_op0[0x76] = Op76; exec_op0[0x77] = Op77; exec_op0[0x78] = Op78;
2733 exec_op0[0x79] = Op79; exec_op0[0x7A] = Op7A; exec_op0[0x7C] = Op7C;
2734 exec_op0[0x7D] = Op7D; exec_op0[0x7E] = Op7E; exec_op0[0x7F] = Op7F;
2735 exec_op0[0x80] = Op80; exec_op0[0x81] = Op81; exec_op0[0x82] = Op82;
2736 exec_op0[0x83] = Op83; exec_op0[0x84] = Op84; exec_op0[0x85] = Op85;
2737 exec_op0[0x86] = Op86; exec_op0[0x88] = Op88; exec_op0[0x89] = Op89;
2738 exec_op0[0x8A] = Op8A; exec_op0[0x8B] = Op8B; exec_op0[0x8C] = Op8C;
2739 exec_op0[0x8D] = Op8D; exec_op0[0x8E] = Op8E; exec_op0[0x90] = Op90;
2740 exec_op0[0x91] = Op91; exec_op0[0x92] = Op92; exec_op0[0x93] = Op93;
2741 exec_op0[0x94] = Op94; exec_op0[0x95] = Op95; exec_op0[0x96] = Op96;
2742 exec_op0[0x97] = Op97; exec_op0[0x98] = Op98; exec_op0[0x99] = Op99;
2743 exec_op0[0x9A] = Op9A; exec_op0[0x9B] = Op9B; exec_op0[0x9C] = Op9C;
2744 exec_op0[0x9D] = Op9D; exec_op0[0x9E] = Op9E; exec_op0[0x9F] = Op9F;
2745 exec_op0[0xA0] = OpA0; exec_op0[0xA1] = OpA1; exec_op0[0xA2] = OpA2;
2746 exec_op0[0xA3] = OpA3; exec_op0[0xA4] = OpA4; exec_op0[0xA5] = OpA5;
2747 exec_op0[0xA6] = OpA6; exec_op0[0xA7] = OpA7; exec_op0[0xA8] = OpA8;
2748 exec_op0[0xA9] = OpA9; exec_op0[0xAA] = OpAA; exec_op0[0xAB] = OpAB;
2749 exec_op0[0xAC] = OpAC; exec_op0[0xAD] = OpAD; exec_op0[0xAE] = OpAE;
2750 exec_op0[0xAF] = OpAF; exec_op0[0xB0] = OpB0; exec_op0[0xB1] = OpB1;
2751 exec_op0[0xB2] = OpB2; exec_op0[0xB3] = OpB3; exec_op0[0xB4] = OpB4;
2752 exec_op0[0xB5] = OpB5; exec_op0[0xB6] = OpB6; exec_op0[0xB7] = OpB7;
2753 exec_op0[0xB8] = OpB8; exec_op0[0xB9] = OpB9; exec_op0[0xBA] = OpBA;
2754 exec_op0[0xBB] = OpBB; exec_op0[0xBC] = OpBC; exec_op0[0xBD] = OpBD;
2755 exec_op0[0xBE] = OpBE; exec_op0[0xBF] = OpBF; exec_op0[0xC0] = OpC0;
2756 exec_op0[0xC1] = OpC1; exec_op0[0xC2] = OpC2; exec_op0[0xC3] = OpC3;
2757 exec_op0[0xC4] = OpC4; exec_op0[0xC5] = OpC5; exec_op0[0xC6] = OpC6;
2758 exec_op0[0xC8] = OpC8; exec_op0[0xC9] = OpC9; exec_op0[0xCA] = OpCA;
2759 exec_op0[0xCB] = OpCB; exec_op0[0xCC] = OpCC; exec_op0[0xCE] = OpCE;
2760 exec_op0[0xD0] = OpD0; exec_op0[0xD1] = OpD1; exec_op0[0xD2] = OpD2;
2761 exec_op0[0xD3] = OpD3; exec_op0[0xD4] = OpD4; exec_op0[0xD5] = OpD5;
2762 exec_op0[0xD6] = OpD6; exec_op0[0xD7] = OpD7; exec_op0[0xD8] = OpD8;
2763 exec_op0[0xD9] = OpD9; exec_op0[0xDA] = OpDA; exec_op0[0xDB] = OpDB;
2764 exec_op0[0xDC] = OpDC; exec_op0[0xDD] = OpDD; exec_op0[0xDE] = OpDE;
2765 exec_op0[0xDF] = OpDF; exec_op0[0xE0] = OpE0; exec_op0[0xE1] = OpE1;
2766 exec_op0[0xE2] = OpE2; exec_op0[0xE3] = OpE3; exec_op0[0xE4] = OpE4;
2767 exec_op0[0xE5] = OpE5; exec_op0[0xE6] = OpE6; exec_op0[0xE7] = OpE7;
2768 exec_op0[0xE8] = OpE8; exec_op0[0xE9] = OpE9; exec_op0[0xEA] = OpEA;
2769 exec_op0[0xEB] = OpEB; exec_op0[0xEC] = OpEC; exec_op0[0xED] = OpED;
2770 exec_op0[0xEE] = OpEE; exec_op0[0xEF] = OpEF; exec_op0[0xF0] = OpF0;
2771 exec_op0[0xF1] = OpF1; exec_op0[0xF2] = OpF2; exec_op0[0xF3] = OpF3;
2772 exec_op0[0xF4] = OpF4; exec_op0[0xF5] = OpF5; exec_op0[0xF6] = OpF6;
2773 exec_op0[0xF7] = OpF7; exec_op0[0xF8] = OpF8; exec_op0[0xF9] = OpF9;
2774 exec_op0[0xFA] = OpFA; exec_op0[0xFB] = OpFB; exec_op0[0xFC] = OpFC;
2775 exec_op0[0xFD] = OpFD; exec_op0[0xFE] = OpFE; exec_op0[0xFF] = OpFF;
2777 exec_op1[0x21] = Op1021; exec_op1[0x22] = Op1022; exec_op1[0x23] = Op1023;
2778 exec_op1[0x24] = Op1024; exec_op1[0x25] = Op1025; exec_op1[0x26] = Op1026;
2779 exec_op1[0x27] = Op1027; exec_op1[0x28] = Op1028; exec_op1[0x29] = Op1029;
2780 exec_op1[0x2A] = Op102A; exec_op1[0x2B] = Op102B; exec_op1[0x2C] = Op102C;
2781 exec_op1[0x2D] = Op102D; exec_op1[0x2E] = Op102E; exec_op1[0x2F] = Op102F;
2782 exec_op1[0x3F] = Op103F; exec_op1[0x83] = Op1083; exec_op1[0x8C] = Op108C;
2783 exec_op1[0x8E] = Op108E; exec_op1[0x93] = Op1093; exec_op1[0x9C] = Op109C;
2784 exec_op1[0x9E] = Op109E; exec_op1[0x9F] = Op109F; exec_op1[0xA3] = Op10A3;
2785 exec_op1[0xAC] = Op10AC; exec_op1[0xAE] = Op10AE; exec_op1[0xAF] = Op10AF;
2786 exec_op1[0xB3] = Op10B3; exec_op1[0xBC] = Op10BC; exec_op1[0xBE] = Op10BE;
2787 exec_op1[0xBF] = Op10BF; exec_op1[0xCE] = Op10CE; exec_op1[0xDE] = Op10DE;
2788 exec_op1[0xDF] = Op10DF; exec_op1[0xEE] = Op10EE; exec_op1[0xEF] = Op10EF;
2789 exec_op1[0xFE] = Op10FE; exec_op1[0xFF] = Op10FF;
2791 exec_op2[0x3F] = Op113F; exec_op2[0x83] = Op1183; exec_op2[0x8C] = Op118C;
2792 exec_op2[0x93] = Op1193; exec_op2[0x9C] = Op119C; exec_op2[0xA3] = Op11A3;
2793 exec_op2[0xAC] = Op11AC; exec_op2[0xB3] = Op11B3; exec_op2[0xBC] = Op11BC;*/
2797 // Function to execute one 6809 instruction
2800 void Execute_6809(long num_of_instrs_to_exec)
2802 for(long i=0; i<num_of_instrs_to_exec; i++)
2804 if (pcr == 0x164A) inter = false; // Ugly temp fix...
2806 BYTE opcode = Fetch(); // Get the opcode
2807 if (opcode == 0x10) { exec_op1[Fetch()](); goto EXE_NEXT; }
2808 if (opcode == 0x11) { exec_op2[Fetch()](); goto EXE_NEXT; }
2815 if (!(ccr&0x10) && (!inter)) // Process an interrupt?
2818 ccr |= 0x80; // Set E
2819 WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); // Save all regs...
2820 WrMem(--sr, ur&0xFF); WrMem(--sr, ur>>8);
2821 WrMem(--sr, yr&0xFF); WrMem(--sr, yr>>8);
2822 WrMem(--sr, xr&0xFF); WrMem(--sr, xr>>8);
2823 WrMem(--sr, dpr); WrMem(--sr, br);
2824 WrMem(--sr, ar); WrMem(--sr, ccr);
2825 ccr |= 0x50; // Set F,I
2826 pcr = (RdMem(0xFFF8)<<8) | RdMem(0xFFF9); // And do it!
2827 // ram[0xCB00] += 64; // Set to 64 for faster updates...
2833 void Execute6809(V6809REGS * context, DWORD cycles)
2835 memcpy(®s, context, sizeof(V6809REGS));
2839 memcpy(context, ®s, sizeof(V6809REGS));