unsigned orgaddr = 0; // Org'd address
unsigned orgwarning = 0; // Has an ORG warning been issued
int lastOpcode = -1; // Last RISC opcode assembled
unsigned orgaddr = 0; // Org'd address
unsigned orgwarning = 0; // Has an ORG warning been issued
int lastOpcode = -1; // Last RISC opcode assembled
const char condname[MAXINTERNCC][5] = {
"NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
"N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
"PL", "MI", "F"
};
const char condname[MAXINTERNCC][5] = {
"NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
"N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
"PL", "MI", "F"
};
const char condnumber[] = {
1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
const char condnumber[] = {
1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
{ MR_NORMI, RI_TWO, 56 },
{ MR_NOP, RI_NONE, 57 },
{ MR_SAT24, RI_ONE, 62 },
{ MR_NORMI, RI_TWO, 56 },
{ MR_NOP, RI_NONE, 57 },
{ MR_SAT24, RI_ONE, 62 },
- { MR_UNPACK, RI_ONE, 63 + GPUONLY },
- { MR_PACK, RI_ONE, 63 + GPUONLY },
+ { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
+ { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
{ MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
{ MR_MOVE, RI_MOVE, 0 },
{ MR_LOAD, RI_LOAD, 0 },
{ MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
{ MR_MOVE, RI_MOVE, 0 },
{ MR_LOAD, RI_LOAD, 0 },
warn("RISC code generated with no origin defined");
orgwarning = 1;
}
int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
D_word(value);
warn("RISC code generated with no origin defined");
orgwarning = 1;
}
int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
D_word(value);
// Get opcode parameter and type
unsigned short parm = (WORD)(roptbl[state - 3000].parm);
unsigned type = roptbl[state - 3000].typ;
// Get opcode parameter and type
unsigned short parm = (WORD)(roptbl[state - 3000].parm);
unsigned type = roptbl[state - 3000].typ;
// Detect whether the opcode parmeter passed determines that the opcode is
// specific to only one of the RISC processors and ensure it is legal in
// Detect whether the opcode parmeter passed determines that the opcode is
// specific to only one of the RISC processors and ensure it is legal in
- // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK
+ // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
+ // UNPACK
- // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT,
- // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
+ // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
+ // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
- // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ
+ // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
+ // RORQ
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x02);
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x02);
+ riscImmTokenSeen = 1;
+
+ // Check for equated register after # and return error if so
+ if (*tok == SYMBOL)
+ {
+ sy = lookup(string[tok[1]], LABEL, 0);
+
+ if (sy && (sy->sattre & EQUATEDREG))
+ return error("equated register in 1st operand of MOVEI instruction");
+ }
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x04);
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x04);
rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
//}
}
rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
//}
}