// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
// Source utilised with the kind permission of Landon Dyer
//
#include "riscasm.h"
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
// Source utilised with the kind permission of Landon Dyer
//
#include "riscasm.h"
#include "kwtab.h" // Incl. generated keyword tables & defs
unsigned altbankok = 0; // Ok to use alternate register bank
#include "kwtab.h" // Incl. generated keyword tables & defs
unsigned altbankok = 0; // Ok to use alternate register bank
unsigned orgaddr = 0; // Org'd address
unsigned orgwarning = 0; // Has an ORG warning been issued
int lastOpcode = -1; // Last RISC opcode assembled
unsigned orgaddr = 0; // Org'd address
unsigned orgwarning = 0; // Has an ORG warning been issued
int lastOpcode = -1; // Last RISC opcode assembled
"NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
"N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
"PL", "MI", "F"
};
"NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
"N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
"PL", "MI", "F"
};
const char condnumber[] = {
1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
const char condnumber[] = {
1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
{ MR_NORMI, RI_TWO, 56 },
{ MR_NOP, RI_NONE, 57 },
{ MR_SAT24, RI_ONE, 62 },
{ MR_NORMI, RI_TWO, 56 },
{ MR_NOP, RI_NONE, 57 },
{ MR_SAT24, RI_ONE, 62 },
- { MR_UNPACK, RI_ONE, 63 + GPUONLY },
- { MR_PACK, RI_ONE, 63 + GPUONLY },
+ { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
+ { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
{ MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
{ MR_MOVE, RI_MOVE, 0 },
{ MR_LOAD, RI_LOAD, 0 },
{ MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
{ MR_MOVE, RI_MOVE, 0 },
{ MR_LOAD, RI_LOAD, 0 },
- char buf[16];
- sprintf(buf, "%02X", signal);
- return errors("Malformed opcode [internal $%s]", buf);
+ return error("Malformed opcode [internal $%02X]", signal);
+}
+
+
+//
+// Function to return "Illegal Indexed Register" error
+// Anyone trying to index something other than R14 or R15
+//
+static inline int IllegalIndexedRegister(int reg)
+{
+ return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0);
+}
+
+
+//
+// Function to return "Illegal Indexed Register" error for EQUR scenarios
+// Trying to use register value within EQUR that isn't 14 or 15
+//
+static inline int IllegalIndexedRegisterEqur(SYM * sy)
+{
+ return error("Attempted index reference with non-indexable register within EQUR (%s = r%d)", sy->sname, sy->svalue);
warn("RISC code generated with no origin defined");
orgwarning = 1;
}
int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
D_word(value);
warn("RISC code generated with no origin defined");
orgwarning = 1;
}
int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
D_word(value);
WORD eattr; // Expression attributes
SYM * esym; // External symbol involved in expr.
TOKEN r_expr[EXPRSIZE]; // Expression token list
WORD eattr; // Expression attributes
SYM * esym; // External symbol involved in expr.
TOKEN r_expr[EXPRSIZE]; // Expression token list
WORD eattr; // Expression attributes
SYM * esym; // External symbol involved in expr.
TOKEN r_expr[EXPRSIZE]; // Expression token list
WORD eattr; // Expression attributes
SYM * esym; // External symbol involved in expr.
TOKEN r_expr[EXPRSIZE]; // Expression token list
// Get opcode parameter and type
unsigned short parm = (WORD)(roptbl[state - 3000].parm);
unsigned type = roptbl[state - 3000].typ;
// Get opcode parameter and type
unsigned short parm = (WORD)(roptbl[state - 3000].parm);
unsigned type = roptbl[state - 3000].typ;
// Detect whether the opcode parmeter passed determines that the opcode is
// specific to only one of the RISC processors and ensure it is legal in
// Detect whether the opcode parmeter passed determines that the opcode is
// specific to only one of the RISC processors and ensure it is legal in
- // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK
+ // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
+ // UNPACK
case RI_ONE:
reg2 = GetRegister(FU_REGTWO);
at_eol();
BuildRISCIntructionWord(parm, parm >> 6, reg2);
case RI_ONE:
reg2 = GetRegister(FU_REGTWO);
at_eol();
BuildRISCIntructionWord(parm, parm >> 6, reg2);
- // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT,
- // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
- case RI_TWO:
+ // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
+ // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
+ case RI_TWO:
- // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ
+ // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
+ // RORQ
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x02);
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x02);
+ riscImmTokenSeen = 1;
+
+ // Check for equated register after # and return error if so
+ if (*tok == SYMBOL)
+ {
+ sy = lookup(string[tok[1]], LABEL, 0);
+
+ if (sy && (sy->sattre & EQUATEDREG))
+ return error("equated register in 1st operand of MOVEI instruction");
+ }
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x04);
if (expr(r_expr, &eval, &eattr, &esym) != OK)
return MalformedOpcode(0x04);
-//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
- rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
+//printf("RISCASM: Doing MarkRelocatable for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
+ MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
break;
// (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
break;
// (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
- if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')'))
- indexed = (*tok - KW_R0);
+ if ((*(tok + 1) == '+') || (*(tok + 1) == '-')) {
+ // Trying to make indexed call
+ if ((*tok == KW_R14 || *tok == KW_R15)) {
+ indexed = (*tok - KW_R0);
+ } else {
+ return IllegalIndexedRegister(*tok);
+ }
+ }
- if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
- && (*(tok + 2) != ')'))
- {
- indexed = (sy->svalue & 0x1F);
- tok++;
+ if ((*(tok + 2) == '+') || (*(tok + 2) == '-')) {
+ if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) {
+ indexed = (sy->svalue & 0x1F);
+ tok++;
+ } else {
+ return IllegalIndexedRegisterEqur(sy);
+ }
break;
// Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
break;
// Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
ccsym = lookup(string[tok[1]], LABEL, 0);
if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
ccsym = lookup(string[tok[1]], LABEL, 0);
if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))