Fix for bug #34 (equated reg in 1st operand of MOVEI).

[rmac] / riscasm.c

diff --git a/riscasm.c b/riscasm.c
index 52925558f9faefb5412407ac30a958442f81f5ba..23faaee7120df76cc71cc95dadce3de262f4cf1c 100644 (file)
--- a/riscasm.c
+++ b/riscasm.c
@@ -27,17 +27,18 @@ unsigned orgactive = 0;             // RISC org directive active
 unsigned orgaddr = 0;          // Org'd address
 unsigned orgwarning = 0;       // Has an ORG warning been issued
 int lastOpcode = -1;           // Last RISC opcode assembled
+uint8_t riscImmTokenSeen;      // The '#' (immediate) token was seen
 
 const char reg_err[] = "missing register R0...R31";
 
-// Jaguar Jump Condition Names
+// Jaguar jump condition names
 const char condname[MAXINTERNCC][5] = { 
        "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
        "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
        "PL", "MI", "F"
 };
 
-// Jaguar Jump Condition Numbers
+// Jaguar jump condition numbers
 const char condnumber[] = {
        1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
        0, 0, 1, 2, 4, 4, 5,  8,  8, 20, 24, 31
@@ -100,8 +101,8 @@ const struct opcoderecord roptbl[] = {
        { MR_NORMI,   RI_TWO,    56 },
        { MR_NOP,     RI_NONE,   57 },
        { MR_SAT24,   RI_ONE,    62 },
-       { MR_UNPACK,  RI_ONE,    63 + GPUONLY },
-       { MR_PACK,    RI_ONE,    63 + GPUONLY },
+       { MR_UNPACK,  RI_ONE,    63 + GPUONLY | (0 << 6) },
+       { MR_PACK,    RI_ONE,    63 + GPUONLY | (1 << 6) },
        { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
        { MR_MOVE,    RI_MOVE,   0 },
        { MR_LOAD,    RI_LOAD,   0 },
@@ -139,13 +140,13 @@ void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
        // Check for absolute address setting
        if (!orgwarning && !orgactive)
        {
-//             warn("GPU/DSP code outside of absolute section");
                warn("RISC code generated with no origin defined");
                orgwarning = 1;
        }
 
        int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
        D_word(value);
+//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
 }
 
 
@@ -205,6 +206,7 @@ int GenerateRISCCode(int state)
        // Get opcode parameter and type
        unsigned short parm = (WORD)(roptbl[state - 3000].parm);
        unsigned type = roptbl[state - 3000].typ;
+       riscImmTokenSeen = 0;           // Set to "token not seen yet"
 
        // Detect whether the opcode parmeter passed determines that the opcode is
        // specific to only one of the RISC processors and ensure it is legal in
@@ -222,7 +224,8 @@ int GenerateRISCCode(int state)
                break;
 
        // Single operand instructions (Rd)
-       // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK
+       // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
+       // UNPACK
        case RI_ONE:
                reg2 = GetRegister(FU_REGTWO);
                at_eol();
@@ -230,8 +233,8 @@ int GenerateRISCCode(int state)
                break;   
 
        // Two operand instructions (Rs,Rd)
-       // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT, 
-       // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
+       // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
+       // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
        case RI_TWO:                      
                if (parm == 37)
                        altbankok = 1;                      // MOVEFA
@@ -256,7 +259,8 @@ int GenerateRISCCode(int state)
        case RI_NUM_31:
 
        // Numeric operand (n,Rd) where n = 1..32
-       // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ
+       // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
+       // RORQ
        case RI_NUM_32:
                switch (type)
                {
@@ -279,6 +283,7 @@ int GenerateRISCCode(int state)
                        return MalformedOpcode(0x01);
 
                tok++;
+               riscImmTokenSeen = 1;
 
                if (expr(r_expr, &eval, &eattr, &esym) != OK)
                        return MalformedOpcode(0x02);
@@ -316,6 +321,16 @@ int GenerateRISCCode(int state)
                        return MalformedOpcode(0x03);
 
                tok++;
+               riscImmTokenSeen = 1;
+
+               // Check for equated register after # and return error if so
+               if (*tok == SYMBOL)
+               {
+                       sy = lookup(string[tok[1]], LABEL, 0);
+
+                       if (sy->sattre & EQUATEDREG)
+                               return error("equated register in 1st operand of MOVEI instruction");
+               }
 
                if (expr(r_expr, &eval, &eattr, &esym) != OK)
                        return MalformedOpcode(0x04);
@@ -344,7 +359,7 @@ int GenerateRISCCode(int state)
                {
                        if (eattr & TDB)
 //{
-//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
+//printf("RISCASM: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
                                rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
 //}
                }