#include "direct.h"
#include "eagen.h"
#include "error.h"
+#include "expr.h"
#include "procln.h"
#include "riscasm.h"
#include "sect.h"
#include "token.h"
-#include "expr.h"
#define DEF_KW
#include "kwtab.h"
// Include code tables
MNTAB machtab[] = {
- { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0
- #include "68ktab.h"
- { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry
+ { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0
+#include "68ktab.h"
+ { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry
};
// Register number << 9
// Byte/Word/long size (0=.w, 1=.l) in bit 9
WORD lwsiz_9[] = {
(WORD)-1,
- 0, // Byte
- 1<<9, (WORD)-1, // Word
- 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long
- 1<<9 // Word (SIZN)
+ 0, // Byte
+ 1<<9, (WORD)-1, // Word
+ 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long
+ 1<<9 // Word (SIZN)
};
// Addressing mode in bits 6..11 (register/mode fields are reversed)
//
int m_adda(WORD inst, WORD siz)
{
+ if (a0exattr & DEFINED)
+ {
+ if (CHECK_OPTS(OPT_ADDA_ADDQ))
+ if (a0exval > 1 && a0exval <= 8)
+ // Immediate is between 1 and 8 so let's convert to addq
+ return m_addq(B16(01010000, 00000000), siz);
+ if (CHECK_OPTS(OPT_ADDA_LEA))
+ if (a0exval > 8)
+ {
+ // Immediate is larger than 8 so let's convert to lea
+ am0 = ADISP; // Change addressing mode
+ a0reg = a1reg; // In ADISP a0reg is used instead of a1reg!
+ return m_lea(B16(01000001, 11011000), SIZW);
+ }
+ }
+
inst |= am0 | a0reg | lwsiz_8[siz] | reg_9[a1reg];
D_word(inst);
ea0gen(siz); // Generate EA
return OK;
}
+
//
// Handle MOVE <C_ALL030> <C_ALTDATA>
// MOVE <C_ALL030> <M_AREG>
int m_clrd(WORD inst, WORD siz)
{
if (!CHECK_OPTS(OPT_CLR_DX))
- {
inst |= a0reg;
- D_word(inst);
-
- return OK;
- }
else
- {
inst = (a0reg << 9) | B16(01110000, 00000000);
- D_word(inst);
- return OK;
- }
+
+ D_word(inst);
+
+ return OK;
}
if (*tok != EOL)
return error("extra (unexpected) text found");
- // Reject invalud ea modes
+ // Reject invalid ea modes
amsk = amsktab[am0];
if ((amsk & (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE)) == 0)
return OK;
}
+
//
// divul.l
//
return OK;
}
+
//
// pflushr (68851)
//
int m_pload(WORD inst, WORD siz, WORD extension)
{
// TODO: 68851 support is not added yet.
- // None of the ST series of computers had a 68020 + 68551 socket and since
+ // None of the ST series of computers had a 68020 + 68851 socket and since
// this is an Atari targetted assembler...
CHECKNO30;
inst |= am1;
-
D_word(inst);
switch (am0)
return OK;
}
+
int m_ploadr(WORD inst, WORD siz)
{
return m_pload(inst, siz, 1 << 9);
}
+
int m_ploadw(WORD inst, WORD siz)
{
return m_pload(inst, siz, 0 << 9);
}
+
//
// pmove (68030/68851)
//
{
int inst2,reg;
- // TODO: 68851 support is not added yet.
- // None of the ST series of computers had
- // a 68020 + 68851 socket and since this is
- // an Atari targetted assembler....
- // (same for 68EC030)
+ // TODO: 68851 support is not added yet. None of the ST series of
+ // computers had a 68020 + 68851 socket and since this is an Atari
+ // targetted assembler.... (same for 68EC030)
CHECKNO30;
- inst2 = inst & (1 << 8); //Copy the flush bit over to inst2 in case we're called from m_pmovefd
- inst &= ~(1 << 8); //And mask it out
+ inst2 = inst & (1 << 8); // Copy the flush bit over to inst2 in case we're called from m_pmovefd
+ inst &= ~(1 << 8); // And mask it out
if (am0 == CREG)
{
if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN)))
return error(siz_error);
-
if (am0 == CREG)
{
inst |= am1 | a1reg;
return m_pmove(inst | (1 << 8), siz);
}
+
//
// ptrapcc (68851)
//
int m_ptrapcc(WORD inst, WORD siz)
{
CHECKNO20;
- // We stash the 5 condition bits
- // inside the opcode in 68ktab
- // (bits 0-4), so we need to extract
- // them first and fill in
- // the clobbered bits.
+ // We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4),
+ // so we need to extract them first and fill in the clobbered bits.
WORD opcode = inst & 0x1F;
inst = (inst & 0xFFE0) | (0x18);
D_word(inst);
D_word(opcode);
}
+
return OK;
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01011000), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01011100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01100010), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01100110), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01100000), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
//
int m_fmove(WORD inst, WORD siz)
{
-
// EA to register
if ((am0 == FREG) && (am1 < AM_USP))
{
case SIZP: inst |= (3 << 10);
// In P size we have 2 cases: {#k} where k is immediate
// and {Dn} where Dn=Data register
-
if (bfparam1)
{
// Dn
break;
}
-
// Destination specifier
inst |= (a0reg << 7);
ea0gen(siz);
return OK;
}
- else
- return error("m_fmovescr says: wut?");
+
+ return error("m_fmovescr says: wut?");
}
//
WORD regmask;
WORD datareg;
- if (siz == SIZX || siz==SIZN)
+ if (siz == SIZX || siz == SIZN)
{
if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
{
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01011110), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
//
int m_fscc(WORD inst, WORD siz)
{
- // We stash the 5 condition bits
- // inside the opcode in 68ktab
- // (bits 4-0), so we need to extract
- // them first and fill in
- // the clobbered bits.
+ // We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0),
+ // so we need to extract them first and fill in the clobbered bits.
WORD opcode = inst & 0x1F;
inst &= 0xFFE0;
inst |= am0 | a0reg;
return OK;
}
+
//
// FTRAPcc (6888X, 68040)
//
-
int m_ftrapcc(WORD inst, WORD siz)
{
- // We stash the 5 condition bits
- // inside the opcode in 68ktab
- // (bits 3-7), so we need to extract
- // them first and fill in
- // the clobbered bits.
+ // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7),
+ // so we need to extract them first and fill in the clobbered bits.
WORD opcode = (inst >> 3) & 0x1F;
inst = (inst & 0xFF07) | (0xF << 3);
+
if (siz == SIZW)
{
inst |= 2;
D_word(opcode);
return OK;
}
+
return OK;
}
+
//
// fsgldiv (6888X, 68040)
//
//
int m_fsincos(WORD inst, WORD siz)
{
- // Swap a1reg, a2reg as a2reg should be stored
- // in the bitfield gen_fpu generates
+ // Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu
+ // generates
int temp;
temp = a2reg;
a2reg = a1reg;
a1reg = temp;
+
if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK)
{
chptr[-1] |= a2reg;
return OK;
}
- else
- return ERROR;
+
+ return ERROR;
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01000101), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01101000), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
{
if (activefpu == FPU_68040)
return gen_fpu(inst, siz, B8(01101100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+
+ return error("Unsupported in current FPU");
}
projects / rmac / blobdiff