- if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
- return error(unsupport);
-
- WORD flg = inst; // Save flag bits
- inst &= ~0x3F; // Clobber flag bits in instr
-
- // Install "standard" instr size bits
- if (flg & 4)
- inst |= siz_6[siz];
-
- if (flg & 16)
- {
- // OR-in register number
- if (flg & 8)
- inst |= reg_9[a1reg]; // ea1reg in bits 9..11
- else
- inst |= reg_9[a0reg]; // ea0reg in bits 9..11
- }
-
- if (flg & 1)
- {
- // Use am1
- inst |= am1 | a1reg; // Get ea1 into instr
- D_word(inst); // Deposit instr
-
- // Generate ea0 if requested
- if (flg & 2)
- ea0gen(siz);
-
- ea1gen(siz); // Generate ea1
- }
- else
- {
- // Use am0
- inst |= am0 | a0reg; // Get ea0 into instr
- D_word(inst); // Deposit instr
- ea0gen(siz); // Generate ea0
-
- // Generate ea1 if requested
- if (flg & 2)
- ea1gen(siz);
- }
-
- inst = a1reg + (a2reg << 12);
- inst |= mulmode; // add size bit
- D_word(inst);
-
- return OK;
-}
-
-
-//
-// divsl.l
-//
-int m_divsl(WORD inst, WORD siz)
-{
- if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
- return error(unsupport);
-
- WORD flg = inst; // Save flag bits
- inst &= ~0x3F; // Clobber flag bits in instr
-
- // Install "standard" instr size bits
- if (flg & 4)
- inst |= siz_6[siz];
-
- if (flg & 16)
- {
- // OR-in register number
- if (flg & 8)
- inst |= reg_9[a1reg]; // ea1reg in bits 9..11
- else
- inst |= reg_9[a0reg]; // ea0reg in bits 9..11
- }
-
- if (flg & 1)
- {
- // Use am1
- inst |= am1 | a1reg; // Get ea1 into instr
- D_word(inst); // Deposit instr
-
- // Generate ea0 if requested
- if (flg & 2)
- ea0gen(siz);
-
- ea1gen(siz); // Generate ea1
- }
- else
- {
- // Use am0
- inst |= am0 | a0reg; // Get ea0 into instr
- D_word(inst); // Deposit instr
- ea0gen(siz); // Generate ea0
-
- // Generate ea1 if requested
- if (flg & 2)
- ea1gen(siz);
- }
-
- inst = a1reg + (a2reg << 12) + (1 << 11) + (1 << 10);
- D_word(inst);
-
- return OK;
-}
-
-
-//
-// divul.l
-//
-int m_divul(WORD inst, WORD siz)
-{
- if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
- return error(unsupport);
-
- WORD flg = inst; // Save flag bits
- inst &= ~0x3F; // Clobber flag bits in instr
-
- // Install "standard" instr size bits
- if (flg & 4)
- inst |= siz_6[siz];
-
- if (flg & 16)
- {
- // OR-in register number
- if (flg & 8)
- inst |= reg_9[a1reg]; // ea1reg in bits 9..11
- else
- inst |= reg_9[a0reg]; // ea0reg in bits 9..11
- }
-
- if (flg & 1)
- {
- // Use am1
- inst |= am1 | a1reg; // Get ea1 into instr
- D_word(inst); // Deposit instr
-
- // Generate ea0 if requested
- if (flg & 2)
- ea0gen(siz);
-
- ea1gen(siz); // Generate ea1
- }
- else
- {
- // Use am0
- inst |= am0 | a0reg; // Get ea0 into instr
- D_word(inst); // Deposit instr
- ea0gen(siz); // Generate ea0
-
- // Generate ea1 if requested
- if (flg & 2)
- ea1gen(siz);
- }
-
- inst = a1reg + (a2reg << 12) + (1 << 10);
- D_word(inst);
-
- return OK;
-}
-
-
-//
-// move16 (ax)+,(ay)+
-//
-int m_move16a(WORD inst, WORD siz)
-{
- if ((activecpu & (CPU_68040 | CPU_68060)) == 0)
- return error(unsupport);
-
- inst |= a0reg;
- D_word(inst);
- inst = (1 << 15) + (a1reg << 12);
- D_word(inst);
-
- return OK;
-}
-
-
-//
-// move16 with absolute address
-//
-int m_move16b(WORD inst, WORD siz)
-{
- if ((activecpu & (CPU_68040 | CPU_68060)) == 0)
- return error(unsupport);
-
- int v;
- inst |= a1reg;
- D_word(inst);
-
- if (am0 == APOSTINC)
- {
- if (am1 == AIND)
- return error("Wasn't this suppose to call m_move16a???");
- else
- {
- //move16 (ax)+,(xxx).L
- inst |= 0 << 3;
- v = (int)a1exval;
- }
- }
- else if (am0 == ABSL)
- {
- if (am1 == AIND)
- {
- //move16 (xxx).L,(ax)+
- inst |= 1 << 3;
- v = (int)a0exval;
- }
- else //APOSTINC
- {
- //move16 (xxx).L,(ax)
- inst |= 3 << 3;
- v = (int)a0exval;
- }
- }
- else if (am0 == AIND)
- {
- //move16 (ax),(xxx).L
- inst |= 2 << 3;
- v = (int)a1exval;
- }
-
- D_word(inst);
- D_long(v);
-
- return OK;
-}
-
-
-//
-// pack/unpack (68020/68030/68040)
-//
-int m_pack(WORD inst, WORD siz)
-{
- CHECK00;
-
- if (siz != SIZN)
- return error("bad size suffix");
-
- if (*tok >= KW_D0 && *tok <= KW_D7)
- {
- // Dx,Dy,#<adjustment>
- inst |= (0 << 3); // R/M
- inst |= (*tok++ & 7);
-
- if (*tok != ',' && tok[2] != ',')
- return error("missing comma");
-
- if (tok[1] < KW_D0 && tok[1] > KW_D7)
- return error(syntax_error);
-
- inst |= ((tok[1] & 7)<<9);
- tok = tok + 3;
- D_word(inst);
- // Fall through for adjustment (common in both valid cases)
- }
- else if (*tok == '-')
- {
- // -(Ax),-(Ay),#<adjustment>
- inst |= (1 << 3); // R/M
- tok++; // eat the minus
-
- if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ','))
- return error(syntax_error);
-
- if (tok[1] < KW_A0 && tok[1] > KW_A7)
- return error(syntax_error);
-
- if (tok[5] < KW_A0 && tok[6] > KW_A7)
- return error(syntax_error);
-
- inst |= ((tok[1] & 7) << 0);
- inst |= ((tok[6] & 7) << 9);
- tok = tok + 9;
- D_word(inst);
- // Fall through for adjustment (common in both valid cases)
- }
- else
- return error("invalid syntax");
-
- if ((*tok != CONST) && (*tok != SYMBOL) && (*tok != '-'))
- return error(syntax_error);
-
- if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR)
- return ERROR;
-
- if ((a0exattr & DEFINED) == 0)
- return error(undef_error);
-
- if (a0exval + 0x8000 > 0x10000)
- return error("");
-
- if (*tok != EOL)
- return error(extra_stuff);
-
- D_word((a0exval & 0xFFFF));
-
- return OK;
-}
-
-
-//
-// rtm Rn
-//
-int m_rtm(WORD inst, WORD siz)
-{
- CHECKNO20;