2 // RMAC - Reboot's Macro Assembler for all Atari computers
3 // AMODE.C - Addressing Modes
4 // Copyright (C) 199x Landon Dyer, 2011-2020 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
23 extern char unsupport[];
25 // Address-mode information
26 int nmodes; // Number of addr'ing modes found
27 int am0; // Addressing mode
28 int a0reg; // Register
29 TOKEN a0expr[EXPRSIZE]; // Expression
30 uint64_t a0exval; // Expression's value
31 WORD a0exattr; // Expression's attribute
32 int a0ixreg; // Index register
33 int a0ixsiz; // Index register size (and scale)
34 TOKEN a0oexpr[EXPRSIZE]; // Outer displacement expression
35 uint64_t a0oexval; // Outer displacement value
36 WORD a0oexattr; // Outer displacement attribute
37 SYM * a0esym; // External symbol involved in expr
38 TOKEN a0bexpr[EXPRSIZE]; // Base displacement expression
39 uint64_t a0bexval; // Base displacement value
40 WORD a0bexattr; // Base displacement attribute
41 WORD a0bsize; // Base displacement size
42 WORD a0extension; // 020+ extension address word
43 WORD am0_030; // ea bits for 020+ addressing modes
45 int am1; // Addressing mode
46 int a1reg; // Register
47 TOKEN a1expr[EXPRSIZE]; // Expression
48 uint64_t a1exval; // Expression's value
49 WORD a1exattr; // Expression's attribute
50 int a1ixreg; // Index register
51 int a1ixsiz; // Index register size (and scale)
52 TOKEN a1oexpr[EXPRSIZE]; // Outer displacement expression
53 uint64_t a1oexval; // Outer displacement value
54 WORD a1oexattr; // Outer displacement attribute
55 SYM * a1esym; // External symbol involved in expr
56 TOKEN a1bexpr[EXPRSIZE]; // Base displacement expression
57 uint64_t a1bexval; // Base displacement value
58 WORD a1bexattr; // Base displacement attribute
59 WORD a1bsize; // Base displacement size
60 WORD a1extension; // 020+ extension address word
61 WORD am1_030; // ea bits for 020+ addressing modes
63 int a2reg; // Register for div.l (68020+)
65 int bfparam1; // bfxxx / fmove instruction parameter 1
66 int bfparam2; // bfxxx / fmove instruction parameter 2
67 int bfval1; // bfxxx / fmove value 1
68 int bfval2; // bfxxx / fmove value 2
69 TOKEN bf0expr[EXPRSIZE]; // Expression
70 uint64_t bf0exval; // Expression's value
71 WORD bf0exattr; // Expression's attribute
72 SYM * bf0esym; // External symbol involved in expr
74 // Function prototypes
75 int Check030Bitfield(void);
79 // Parse addressing mode
83 // Initialize global return values
84 nmodes = a0reg = a1reg = 0;
86 a0expr[0] = a0oexpr[0] = a1expr[0] = a1oexpr[0] = ENDEXPR;
87 a0exattr = a0oexattr = a1exattr = a1oexattr = 0;
88 a0esym = a1esym = NULL;
89 a0bexpr[0] = a1bexpr[0] = ENDEXPR;
90 a0bexval = a1bexval = 0;
91 a0bsize = a0extension = a1bsize = a1extension = 0;
92 am0_030 = am1_030 = 0;
93 bfparam1 = bfparam2 = 0;
98 // If at EOL, then no addr modes at all
102 // Parse first addressing mode
106 #define AnIXREG a0ixreg
107 #define AnIXSIZ a0ixsiz
108 #define AnEXPR a0expr
109 #define AnEXVAL a0exval
110 #define AnEXATTR a0exattr
111 #define AnOEXPR a0oexpr
112 #define AnOEXVAL a0oexval
113 #define AnOEXATTR a0oexattr
114 #define AnESYM a0esym
115 #define AMn_IX0 am0_ix0
116 #define AMn_IXN am0_ixn
117 #define CHK_FOR_DISPn CheckForDisp0
118 #define AnBEXPR a0bexpr
119 #define AnBEXVAL a0bexval
120 #define AnBEXATTR a0bexattr
121 #define AnBZISE a0bsize
122 #define AnEXTEN a0extension
123 #define AMn_030 am0_030
124 #define IS_SUPPRESSEDn IS_SUPPRESSED0
125 #define CHECKODn CHECKOD0
128 // If caller wants only one mode, return just one (ignore comma);. If there
129 // is no second addressing mode (no comma), then return just one anyway.
132 // it's a bitfield instruction--check the parameters inside the {} block
135 if (Check030Bitfield() == ERROR)
138 if ((acount == 0) || (*tok != ','))
144 // Parse second addressing mode
148 #define AnIXREG a1ixreg
149 #define AnIXSIZ a1ixsiz
150 #define AnEXPR a1expr
151 #define AnEXVAL a1exval
152 #define AnEXATTR a1exattr
153 #define AnOEXPR a1oexpr
154 #define AnOEXVAL a1oexval
155 #define AnOEXATTR a1oexattr
156 #define AnESYM a1esym
157 #define AMn_IX0 am1_ix0
158 #define AMn_IXN am1_ixn
159 #define CHK_FOR_DISPn CheckForDisp1
160 #define AnBEXPR a1bexpr
161 #define AnBEXVAL a1bexval
162 #define AnBEXATTR a1bexattr
163 #define AnBZISE a1bsize
164 #define AnEXTEN a1extension
165 #define AMn_030 am1_030
166 #define IS_SUPPRESSEDn IS_SUPPRESSED1
167 #define CHECKODn CHECKOD1
170 // It's a bitfield instruction--check the parameters inside the {} block
173 if (Check030Bitfield() == ERROR)
176 // At this point, it is legal for 020+ to have a ':'. For example divu.l
180 if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
181 return error(unsupport);
183 // TODO: protect this from combinations like Dx:FPx etc :)
184 tok++; //eat the colon
186 if ((*tok >= KW_D0) && (*tok <= KW_D7))
187 a2reg = (*tok++) & 7;
188 else if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
189 a2reg = (*tok++) & 7;
191 return error("a data or FPU register must follow a :");
195 // If no ':' is present then maybe we have something like divs.l d0,d1
196 // which sould translate to divs.l d0,d1:d1
205 return error("addressing mode syntax");
210 // Parse register list
212 int reglist(WORD * a_rmask)
214 static WORD msktab[] = {
215 0x0001, 0x0002, 0x0004, 0x0008,
216 0x0010, 0x0020, 0x0040, 0x0080,
217 0x0100, 0x0200, 0x0400, 0x0800,
218 0x1000, 0x2000, 0x4000, 0x8000
226 if ((*tok >= KW_D0) && (*tok <= KW_A7))
235 if ((*tok >= KW_D0) && (*tok <= KW_A7))
238 return error("register list syntax");
241 return error("register list order");
249 rmask |= msktab[r++];
264 // Parse FPU register list
266 int fpu_reglist_left(WORD * a_rmask)
268 static WORD msktab_minus[] = {
269 0x0080, 0x0040, 0x0020, 0x0010,
270 0x0008, 0x0004, 0x0002, 0x0001
278 if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
287 if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
290 return error("register list syntax");
293 return error("register list order");
303 rmask |= msktab_minus[r++];
317 int fpu_reglist_right(WORD * a_rmask)
319 static WORD msktab_plus[] = {
320 0x0080, 0x0040, 0x0020, 0x0010,
321 0x0008, 0x0004, 0x0002, 0x0001
329 if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
338 if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
341 return error("register list syntax");
344 return error("register list order");
352 rmask |= msktab_plus[r++];
367 // Check for bitfield instructions extra params
368 // These are 020+ instructions and have the following syntax:
369 // bfxxx <ea>{param1,param2}
370 // param1/2 are either data registers or immediate values
372 int Check030Bitfield(void)
381 bfval1 = (int)*tp.u64++;
384 // Do=0, offset=immediate - shift it to place
385 bfparam1 = (0 << 11);
387 else if (*tok == SYMBOL)
389 if (expr(bf0expr, &bf0exval, &bf0exattr, &bf0esym) != OK)
392 if (!(bf0exattr & DEFINED))
393 return error("bfxxx offset: immediate value must evaluate");
395 bfval1 = (int)bf0exval;
397 // Do=0, offset=immediate - shift it to place
398 bfparam1 = (0 << 11);
400 else if ((*tok >= KW_D0) && (*tok <= KW_D7))
402 // Do=1, offset=data register - shift it to place
403 bfparam1 = (1 << 11);
404 bfval1 = (*(int *)tok - 128);
410 // Eat the ':', if any
414 if (*tok == '}' && tok[1] == EOL)
416 // It is ok to have }, EOL here - it might be "fmove fpn,<ea> {dx}"
424 bfval2 = (int)*tp.u64++;
427 // Do=0, offset=immediate - shift it to place
430 else if (*tok == SYMBOL)
432 if (expr(bf0expr, &bf0exval, &bf0exattr, &bf0esym) != OK)
435 bfval2 = (int)bf0exval;
437 if (!(bf0exattr & DEFINED))
438 return error("bfxxx width: immediate value must evaluate");
440 // Do=0, offset=immediate - shift it to place
443 else if ((*tok >= KW_D0) && (*tok <= KW_D7))
445 // Do=1, offset=data register - shift it to place
446 bfval2 = (*(int *)tok - 128);
453 tok++; // Eat the '}'