static void gpu_opcode_pack(void);
// This is wrong, since it doesn't take pipeline effects into account. !!! FIX !!!
-/*uint8 gpu_opcode_cycles[64] =
+/*uint8_t gpu_opcode_cycles[64] =
{
3, 3, 3, 3, 3, 3, 3, 3,
3, 3, 3, 3, 3, 3, 3, 3,
//This is wrong, wrong, WRONG, but it seems to work for the time being...
//(That is, it fixes Flip Out which relies on GPU timing rather than semaphores. Bad developers! Bad!)
//What's needed here is a way to take pipeline effects into account (including pipeline stalls!)...
-/*uint8 gpu_opcode_cycles[64] =
+/*uint8_t gpu_opcode_cycles[64] =
{
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 4, 1,
1, 1, 3, 3, 1, 1, 1, 1
};//*/
-uint8 gpu_opcode_cycles[64] =
+uint8_t gpu_opcode_cycles[64] =
{
1, 1, 1, 1, 1, 1, 1, 1,
1, 1, 1, 1, 1, 1, 1, 1,
gpu_opcode_store_r14_ri, gpu_opcode_store_r15_ri, gpu_opcode_sat24, gpu_opcode_pack,
};
-static uint8 gpu_ram_8[0x1000];
-uint32 gpu_pc;
-static uint32 gpu_acc;
-static uint32 gpu_remain;
-static uint32 gpu_hidata;
-static uint32 gpu_flags;
-static uint32 gpu_matrix_control;
-static uint32 gpu_pointer_to_matrix;
-static uint32 gpu_data_organization;
-static uint32 gpu_control;
-static uint32 gpu_div_control;
+static uint8_t gpu_ram_8[0x1000];
+uint32_t gpu_pc;
+static uint32_t gpu_acc;
+static uint32_t gpu_remain;
+static uint32_t gpu_hidata;
+static uint32_t gpu_flags;
+static uint32_t gpu_matrix_control;
+static uint32_t gpu_pointer_to_matrix;
+static uint32_t gpu_data_organization;
+static uint32_t gpu_control;
+static uint32_t gpu_div_control;
// There is a distinct advantage to having these separated out--there's no need to clear
// a bit before writing a result. I.e., if the result of an operation leaves a zero in
// the carry flag, you don't have to zero gpu_flag_c before you can write that zero!
-static uint8 gpu_flag_z, gpu_flag_n, gpu_flag_c;
-uint32 gpu_reg_bank_0[32];
-uint32 gpu_reg_bank_1[32];
-static uint32 * gpu_reg;
-static uint32 * gpu_alternate_reg;
+static uint8_t gpu_flag_z, gpu_flag_n, gpu_flag_c;
+uint32_t gpu_reg_bank_0[32];
+uint32_t gpu_reg_bank_1[32];
+static uint32_t * gpu_reg;
+static uint32_t * gpu_alternate_reg;
-static uint32 gpu_instruction;
-static uint32 gpu_opcode_first_parameter;
-static uint32 gpu_opcode_second_parameter;
+static uint32_t gpu_instruction;
+static uint32_t gpu_opcode_first_parameter;
+static uint32_t gpu_opcode_second_parameter;
#define GPU_RUNNING (gpu_control & 0x01)
#define IMM_2 gpu_opcode_second_parameter
#define SET_FLAG_Z(r) (gpu_flag_z = ((r) == 0));
-#define SET_FLAG_N(r) (gpu_flag_n = (((uint32)(r) >> 31) & 0x01));
+#define SET_FLAG_N(r) (gpu_flag_n = (((uint32_t)(r) >> 31) & 0x01));
#define RESET_FLAG_Z() gpu_flag_z = 0;
#define RESET_FLAG_N() gpu_flag_n = 0;
#define CLR_ZN (gpu_flag_z = gpu_flag_n = 0)
#define CLR_ZNC (gpu_flag_z = gpu_flag_n = gpu_flag_c = 0)
#define SET_Z(r) (gpu_flag_z = ((r) == 0))
-#define SET_N(r) (gpu_flag_n = (((uint32)(r) >> 31) & 0x01))
-#define SET_C_ADD(a,b) (gpu_flag_c = ((uint32)(b) > (uint32)(~(a))))
-#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32)(b) > (uint32)(a)))
+#define SET_N(r) (gpu_flag_n = (((uint32_t)(r) >> 31) & 0x01))
+#define SET_C_ADD(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(~(a))))
+#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(a)))
#define SET_ZN(r) SET_N(r); SET_Z(r)
#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b)
-uint32 gpu_convert_zero[32] =
+uint32_t gpu_convert_zero[32] =
{ 32,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 };
-uint8 * branch_condition_table = 0;
+uint8_t * branch_condition_table = 0;
#define BRANCH_CONDITION(x) branch_condition_table[(x) + ((jaguar_flags & 7) << 5)]
-uint32 gpu_opcode_use[64];
+uint32_t gpu_opcode_use[64];
const char * gpu_opcode_str[64]=
{
"store_r14_ri", "store_r15_ri", "sat24", "pack",
};
-static uint32 gpu_in_exec = 0;
-static uint32 gpu_releaseTimeSlice_flag = 0;
+static uint32_t gpu_in_exec = 0;
+static uint32_t gpu_releaseTimeSlice_flag = 0;
void GPUReleaseTimeslice(void)
{
gpu_releaseTimeSlice_flag = 1;
}
-uint32 GPUGetPC(void)
+uint32_t GPUGetPC(void)
{
return gpu_pc;
}
{
if (!branch_condition_table)
{
- branch_condition_table = (uint8 *)malloc(32 * 8 * sizeof(branch_condition_table[0]));
+ branch_condition_table = (uint8_t *)malloc(32 * 8 * sizeof(branch_condition_table[0]));
if (branch_condition_table)
{
//
// GPU byte access (read)
//
-uint8 GPUReadByte(uint32 offset, uint32 who/*=UNKNOWN*/)
+uint8_t GPUReadByte(uint32_t offset, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF02000 && offset <= 0xF020FF)
WriteLog("GPU: ReadByte--Attempt to read from GPU register file by %s!\n", whoName[who]);
return gpu_ram_8[offset & 0xFFF];
else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20))
{
- uint32 data = GPUReadLong(offset & 0xFFFFFFFC, who);
+ uint32_t data = GPUReadLong(offset & 0xFFFFFFFC, who);
if ((offset & 0x03) == 0)
return data >> 24;
//
// GPU word access (read)
//
-uint16 GPUReadWord(uint32 offset, uint32 who/*=UNKNOWN*/)
+uint16_t GPUReadWord(uint32_t offset, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF02000 && offset <= 0xF020FF)
WriteLog("GPU: ReadWord--Attempt to read from GPU register file by %s!\n", whoName[who]);
if ((offset >= GPU_WORK_RAM_BASE) && (offset < GPU_WORK_RAM_BASE+0x1000))
{
offset &= 0xFFF;
- uint16 data = ((uint16)gpu_ram_8[offset] << 8) | (uint16)gpu_ram_8[offset+1];
+ uint16_t data = ((uint16_t)gpu_ram_8[offset] << 8) | (uint16_t)gpu_ram_8[offset+1];
return data;
}
else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20))
if (offset & 0x01) // Catch cases 1 & 3... (unaligned read)
return (GPUReadByte(offset, who) << 8) | GPUReadByte(offset+1, who);
- uint32 data = GPUReadLong(offset & 0xFFFFFFFC, who);
+ uint32_t data = GPUReadLong(offset & 0xFFFFFFFC, who);
if (offset & 0x02) // Cases 0 & 2...
return data & 0xFFFF;
//
// GPU dword access (read)
//
-uint32 GPUReadLong(uint32 offset, uint32 who/*=UNKNOWN*/)
+uint32_t GPUReadLong(uint32_t offset, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF02000 && offset <= 0xF020FF)
{
WriteLog("GPU: ReadLong--Attempt to read from GPU register file (%X) by %s!\n", offset, whoName[who]);
- uint32 reg = (offset & 0xFC) >> 2;
+ uint32_t reg = (offset & 0xFC) >> 2;
return (reg < 32 ? gpu_reg_bank_0[reg] : gpu_reg_bank_1[reg - 32]);
}
if ((offset >= GPU_WORK_RAM_BASE) && (offset <= GPU_WORK_RAM_BASE + 0x0FFC))
{
offset &= 0xFFF;
- return ((uint32)gpu_ram_8[offset] << 24) | ((uint32)gpu_ram_8[offset+1] << 16)
- | ((uint32)gpu_ram_8[offset+2] << 8) | (uint32)gpu_ram_8[offset+3];//*/
+ return ((uint32_t)gpu_ram_8[offset] << 24) | ((uint32_t)gpu_ram_8[offset+1] << 16)
+ | ((uint32_t)gpu_ram_8[offset+2] << 8) | (uint32_t)gpu_ram_8[offset+3];//*/
// return GET32(gpu_ram_8, offset);
}
// else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset < GPU_CONTROL_RAM_BASE+0x20))
//
// GPU byte access (write)
//
-void GPUWriteByte(uint32 offset, uint8 data, uint32 who/*=UNKNOWN*/)
+void GPUWriteByte(uint32_t offset, uint8_t data, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF02000 && offset <= 0xF020FF)
WriteLog("GPU: WriteByte--Attempt to write to GPU register file by %s!\n", whoName[who]);
}
else if ((offset >= GPU_CONTROL_RAM_BASE) && (offset <= GPU_CONTROL_RAM_BASE + 0x1F))
{
- uint32 reg = offset & 0x1C;
+ uint32_t reg = offset & 0x1C;
int bytenum = offset & 0x03;
//This is definitely wrong!
gpu_div_control = (gpu_div_control & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3));
else
{
- uint32 old_data = GPUReadLong(offset & 0xFFFFFFC, who);
+ uint32_t old_data = GPUReadLong(offset & 0xFFFFFFC, who);
bytenum = 3 - bytenum; // convention motorola !!!
old_data = (old_data & (~(0xFF << (bytenum << 3)))) | (data << (bytenum << 3));
GPUWriteLong(offset & 0xFFFFFFC, old_data, who);
//
// GPU word access (write)
//
-void GPUWriteWord(uint32 offset, uint16 data, uint32 who/*=UNKNOWN*/)
+void GPUWriteWord(uint32_t offset, uint16_t data, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF02000 && offset <= 0xF020FF)
WriteLog("GPU: WriteWord--Attempt to write to GPU register file by %s!\n", whoName[who]);
else
{
//WriteLog("[GPU W16:%08X,%04X]", offset, data);
- uint32 old_data = GPUReadLong(offset & 0xFFFFFFC, who);
+ uint32_t old_data = GPUReadLong(offset & 0xFFFFFFC, who);
if (offset & 0x02)
old_data = (old_data & 0xFFFF0000) | (data & 0xFFFF);
//
// GPU dword access (write)
//
-void GPUWriteLong(uint32 offset, uint32 data, uint32 who/*=UNKNOWN*/)
+void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who/*=UNKNOWN*/)
{
if (offset >= 0xF02000 && offset <= 0xF020FF)
WriteLog("GPU: WriteLong--Attempt to write to GPU register file by %s!\n", whoName[who]);
break;
case 0x14:
{
-// uint32 gpu_was_running = GPU_RUNNING;
+// uint32_t gpu_was_running = GPU_RUNNING;
data &= ~0xF7C0; // Disable writes to INT_LAT0-4 & TOM version number
// check for GPU -> CPU interrupt
if (GPU_RUNNING && effect_start5 && gpu_pc == 0xF035D8)
{
// Let's do a dump of $6528!
-/* uint32 numItems = JaguarReadWord(0x6BD6);
+/* uint32_t numItems = JaguarReadWord(0x6BD6);
WriteLog("\nDump of $6528: %u items.\n\n", numItems);
for(int i=0; i<numItems*3*4; i+=3*4)
{
WriteLog("\t%04X: %08X %08X %08X -> ", 0x6528+i, JaguarReadLong(0x6528+i),
JaguarReadLong(0x6528+i+4), JaguarReadLong(0x6528+i+8));
- uint16 link = JaguarReadWord(0x6528+i+8+2);
+ uint16_t link = JaguarReadWord(0x6528+i+8+2);
for(int j=0; j<40; j+=4)
WriteLog("%08X ", JaguarReadLong(link + j));
WriteLog("\n");
//This isn't working the way it should! !!! FIX !!!
//Err, actually, it is.
// NOW, it works right! Problem solved!!! It's a blitter bug!
-/* uint32 src = 0x4D54, dst = 0xF03000, width = 10 * 4;
+/* uint32_t src = 0x4D54, dst = 0xF03000, width = 10 * 4;
for(int y=0; y<127; y++)
{
for(int x=0; x<2; x++)
return;
// Get the interrupt latch & enable bits
- uint32 bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F;
+ uint32_t bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F;
// Bail out if latched interrupts aren't enabled
bits &= mask;
return;
// Determine which interrupt to service
- uint32 which = 0; //Isn't there a #pragma to disable this warning???
+ uint32_t which = 0; //Isn't there a #pragma to disable this warning???
if (bits & 0x01)
which = 0;
if (bits & 0x02)
if (start_logging)
WriteLog("GPU: Setting GPU IRQ line #%i\n", irqline);
- uint32 mask = 0x0040 << irqline;
+ uint32_t mask = 0x0040 << irqline;
gpu_control &= ~mask; // Clear the interrupt latch
if (state)
void GPUInit(void)
{
// memory_malloc_secure((void **)&gpu_ram_8, 0x1000, "GPU work RAM");
-// memory_malloc_secure((void **)&gpu_reg_bank_0, 32 * sizeof(int32), "GPU bank 0 regs");
-// memory_malloc_secure((void **)&gpu_reg_bank_1, 32 * sizeof(int32), "GPU bank 1 regs");
+// memory_malloc_secure((void **)&gpu_reg_bank_0, 32 * sizeof(int32_t), "GPU bank 0 regs");
+// memory_malloc_secure((void **)&gpu_reg_bank_1, 32 * sizeof(int32_t), "GPU bank 1 regs");
build_branch_condition_table();
GPUResetStats();
}
-uint32 GPUReadPC(void)
+uint32_t GPUReadPC(void)
{
return gpu_pc;
}
void GPUResetStats(void)
{
- for(uint32 i=0; i<64; i++)
+ for(uint32_t i=0; i<64; i++)
gpu_opcode_use[i] = 0;
WriteLog("--> GPU stats were reset!\n");
}
char buffer[512];
WriteLog("\n---[GPU code at 00F03000]---------------------------\n");
- uint32 j = 0xF03000;
+ uint32_t j = 0xF03000;
while (j <= 0xF03FFF)
{
- uint32 oldj = j;
+ uint32_t oldj = j;
j += dasmjag(JAGUAR_GPU, buffer, j);
WriteLog("\t%08X: %s\n", oldj, buffer);
}
WriteLog("GPU: Stopped at PC=%08X (GPU %s running)\n", (unsigned int)gpu_pc, GPU_RUNNING ? "was" : "wasn't");
// Get the interrupt latch & enable bits
- uint8 bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F;
+ uint8_t bits = (gpu_control >> 6) & 0x1F, mask = (gpu_flags >> 4) & 0x1F;
WriteLog("GPU: Latch bits = %02X, enable bits = %02X\n", bits, mask);
GPUDumpRegisters();
static int testCount = 1;
static int len = 0;
static bool tripwire = false;
-void GPUExec(int32 cycles)
+void GPUExec(int32_t cycles)
{
if (!GPU_RUNNING)
return;
{
if (gpu_pc == 0xF03000)
{
- extern uint32 starCount;
+ extern uint32_t starCount;
starCount = 0;
/* WriteLog("GPU: Starting starfield generator... Dump of [R03=%08X]:\n", gpu_reg_bank_0[03]);
- uint32 base = gpu_reg_bank_0[3];
- for(uint32 i=0; i<0x100; i+=16)
+ uint32_t base = gpu_reg_bank_0[3];
+ for(uint32_t i=0; i<0x100; i+=16)
{
WriteLog("%02X: ", i);
- for(uint32 j=0; j<16; j++)
+ for(uint32_t j=0; j<16; j++)
{
WriteLog("%02X ", JaguarReadByte(base + i + j));
}
gpu_flag_z = (gpu_flag_z ? 1 : 0);
gpu_flag_n = (gpu_flag_n ? 1 : 0);*/
- uint16 opcode = GPUReadWord(gpu_pc, GPU);
- uint32 index = opcode >> 10;
+ uint16_t opcode = GPUReadWord(gpu_pc, GPU);
+ uint32_t index = opcode >> 10;
gpu_instruction = opcode; // Added for GPU #3...
gpu_opcode_first_parameter = (opcode >> 5) & 0x1F;
gpu_opcode_second_parameter = opcode & 0x1F;
gpu_flag_z = (gpu_flag_z ? 1 : 0);
gpu_flag_n = (gpu_flag_n ? 1 : 0);*/
// KLUDGE: Used by BRANCH_CONDITION
- uint32 jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z;
+ uint32_t jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z;
if (BRANCH_CONDITION(IMM_2))
{
#endif
if (gpu_start_log)
WriteLog(" --> JUMP: Branch taken.\n");
- uint32 delayed_pc = RM;
+ uint32_t delayed_pc = RM;
GPUExec(1);
gpu_pc = delayed_pc;
-/* uint16 opcode = GPUReadWord(gpu_pc, GPU);
+/* uint16_t opcode = GPUReadWord(gpu_pc, GPU);
gpu_opcode_first_parameter = (opcode >> 5) & 0x1F;
gpu_opcode_second_parameter = opcode & 0x1F;
#endif
/* if (CONDITION(jaguar.op & 31))
{
- int32 r1 = (INT8)((jaguar.op >> 2) & 0xF8) >> 2;
- uint32 newpc = jaguar.PC + r1;
+ int32_t r1 = (INT8)((jaguar.op >> 2) & 0xF8) >> 2;
+ uint32_t newpc = jaguar.PC + r1;
CALL_MAME_DEBUG;
jaguar.op = ROPCODE(jaguar.PC);
jaguar.PC = newpc;
gpu_flag_c = (gpu_flag_c ? 1 : 0);
gpu_flag_z = (gpu_flag_z ? 1 : 0);*/
// KLUDGE: Used by BRANCH_CONDITION
- uint32 jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z;
+ uint32_t jaguar_flags = (gpu_flag_n << 2) | (gpu_flag_c << 1) | gpu_flag_z;
if (BRANCH_CONDITION(IMM_2))
{
#endif
if (gpu_start_log)
WriteLog(" --> JR: Branch taken.\n");
- int32 offset = (IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1); // Sign extend IMM_1
- int32 delayed_pc = gpu_pc + (offset * 2);
+ int32_t offset = (IMM_1 & 0x10 ? 0xFFFFFFF0 | IMM_1 : IMM_1); // Sign extend IMM_1
+ int32_t delayed_pc = gpu_pc + (offset * 2);
GPUExec(1);
gpu_pc = delayed_pc;
-/* uint16 opcode = GPUReadWord(gpu_pc, GPU);
+/* uint16_t opcode = GPUReadWord(gpu_pc, GPU);
gpu_opcode_first_parameter = (opcode >> 5) & 0x1F;
gpu_opcode_second_parameter = opcode & 0x1F;
if (doGPUDis)
WriteLog("%06X: ADD R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- uint32 res = RN + RM;
+ uint32_t res = RN + RM;
CLR_ZNC; SET_ZNC_ADD(RN, RM, res);
RN = res;
#ifdef GPU_DIS_ADD
WriteLog("%06X: ADDC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
/* int dreg = jaguar.op & 31;
- uint32 r1 = jaguar.r[(jaguar.op >> 5) & 31];
- uint32 r2 = jaguar.r[dreg];
- uint32 res = r2 + r1 + ((jaguar.FLAGS >> 1) & 1);
+ uint32_t r1 = jaguar.r[(jaguar.op >> 5) & 31];
+ uint32_t r2 = jaguar.r[dreg];
+ uint32_t res = r2 + r1 + ((jaguar.FLAGS >> 1) & 1);
jaguar.r[dreg] = res;
CLR_ZNC; SET_ZNC_ADD(r2,r1,res);*/
- uint32 res = RN + RM + gpu_flag_c;
- uint32 carry = gpu_flag_c;
+ uint32_t res = RN + RM + gpu_flag_c;
+ uint32_t carry = gpu_flag_c;
// SET_ZNC_ADD(RN, RM, res); //???BUG??? Yes!
SET_ZNC_ADD(RN + carry, RM, res);
// SET_ZNC_ADD(RN, RM + carry, res);
if (doGPUDis)
WriteLog("%06X: ADDQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 r1 = gpu_convert_zero[IMM_1];
- uint32 res = RN + r1;
+ uint32_t r1 = gpu_convert_zero[IMM_1];
+ uint32_t res = RN + r1;
CLR_ZNC; SET_ZNC_ADD(RN, r1, res);
RN = res;
#ifdef GPU_DIS_ADDQ
if (doGPUDis)
WriteLog("%06X: SUB R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- uint32 res = RN - RM;
+ uint32_t res = RN - RM;
SET_ZNC_SUB(RN, RM, res);
RN = res;
#ifdef GPU_DIS_SUB
if (doGPUDis)
WriteLog("%06X: SUBC R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- uint32 res = RN - RM - gpu_flag_c;
- uint32 borrow = gpu_flag_c;
+ uint32_t res = RN - RM - gpu_flag_c;
+ uint32_t borrow = gpu_flag_c;
// SET_ZNC_SUB(RN, RM, res); //???BUG??? YES!!!
//No matter how you do it, there is a problem. With below, it's 0-0 with carry,
//and the one below it it's FFFFFFFF - FFFFFFFF with carry... !!! FIX !!!
N = 5, M = 3, 3 - 5 = -2, C = 1... Or, in our case:
N = 0, M = 1, 0 - 1 = -1, C = 0!
-#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32)(b) > (uint32)(a)))
+#define SET_C_SUB(a,b) (gpu_flag_c = ((uint32_t)(b) > (uint32_t)(a)))
#define SET_ZN(r) SET_N(r); SET_Z(r)
#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b)
#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b)
if (doGPUDis)
WriteLog("%06X: SUBQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 r1 = gpu_convert_zero[IMM_1];
- uint32 res = RN - r1;
+ uint32_t r1 = gpu_convert_zero[IMM_1];
+ uint32_t res = RN - r1;
SET_ZNC_SUB(RN, r1, res);
RN = res;
#ifdef GPU_DIS_SUBQ
if (doGPUDis)
WriteLog("%06X: CMP R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- uint32 res = RN - RM;
+ uint32_t res = RN - RM;
SET_ZNC_SUB(RN, RM, res);
#ifdef GPU_DIS_CMP
if (doGPUDis)
static void gpu_opcode_cmpq(void)
{
- static int32 sqtable[32] =
+ static int32_t sqtable[32] =
{ 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1 };
#ifdef GPU_DIS_CMPQ
if (doGPUDis)
WriteLog("%06X: CMPQ #%d, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, sqtable[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3;
- uint32 res = RN - r1;
+ uint32_t r1 = sqtable[IMM_1 & 0x1F]; // I like this better -> (INT8)(jaguar.op >> 2) >> 3;
+ uint32_t res = RN - r1;
SET_ZNC_SUB(RN, r1, res);
#ifdef GPU_DIS_CMPQ
if (doGPUDis)
if (doGPUDis)
WriteLog("%06X: SAT8 R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- RN = ((int32)RN < 0 ? 0 : (RN > 0xFF ? 0xFF : RN));
+ RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFF ? 0xFF : RN));
SET_ZN(RN);
#ifdef GPU_DIS_SAT8
if (doGPUDis)
static void gpu_opcode_sat16(void)
{
- RN = ((int32)RN < 0 ? 0 : (RN > 0xFFFF ? 0xFFFF : RN));
+ RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFFFF ? 0xFFFF : RN));
SET_ZN(RN);
}
static void gpu_opcode_sat24(void)
{
- RN = ((int32)RN < 0 ? 0 : (RN > 0xFFFFFF ? 0xFFFFFF : RN));
+ RN = ((int32_t)RN < 0 ? 0 : (RN > 0xFFFFFF ? 0xFFFFFF : RN));
SET_ZN(RN);
}
WriteLog("%06X: STORE R%02u, (R14+$%02X) [NCZ:%u%u%u, R%02u=%08X, R14+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2));
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2);
+ uint32_t address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2);
if (address >= 0xF03000 && address <= 0xF03FFF)
GPUWriteLong(address & 0xFFFFFFFC, RN, GPU);
WriteLog("%06X: STORE R%02u, (R15+$%02X) [NCZ:%u%u%u, R%02u=%08X, R15+$%02X=%08X]\n", gpu_pc-2, IMM_2, gpu_convert_zero[IMM_1] << 2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2));
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2);
+ uint32_t address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2);
if (address >= 0xF03000 && address <= 0xF03FFF)
GPUWriteLong(address & 0xFFFFFFFC, RN, GPU);
WriteLog("%06X: LOAD (R14+R%02u), R%02u [NCZ:%u%u%u, R14+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[14], IMM_2, RN);
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 address = gpu_reg[14] + RM;
+ uint32_t address = gpu_reg[14] + RM;
if (address >= 0xF03000 && address <= 0xF03FFF)
RN = GPUReadLong(address & 0xFFFFFFFC, GPU);
WriteLog("%06X: LOAD (R15+R%02u), R%02u [NCZ:%u%u%u, R15+R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM+gpu_reg[15], IMM_2, RN);
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 address = gpu_reg[15] + RM;
+ uint32_t address = gpu_reg[15] + RM;
if (address >= 0xF03000 && address <= 0xF03FFF)
RN = GPUReadLong(address & 0xFFFFFFFC, GPU);
WriteLog("%06X: STORE R%02u, (R14+R%02u) [NCZ:%u%u%u, R%02u=%08X, R14+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[14]);
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 address = gpu_reg[14] + RM;
+ uint32_t address = gpu_reg[14] + RM;
if (address >= 0xF03000 && address <= 0xF03FFF)
GPUWriteLong(address & 0xFFFFFFFC, RN, GPU);
WriteLog("%06X: STORE R%02u, (R15+R%02u) [NCZ:%u%u%u, R%02u=%08X, R15+R%02u=%08X]\n", gpu_pc-2, IMM_2, IMM_1, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN, IMM_1, RM+gpu_reg[15]);
#endif
#ifdef GPU_CORRECT_ALIGNMENT_STORE
- uint32 address = gpu_reg[15] + RM;
+ uint32_t address = gpu_reg[15] + RM;
if (address >= 0xF03000 && address <= 0xF03FFF)
GPUWriteLong(address & 0xFFFFFFFC, RN, GPU);
if (doGPUDis)
WriteLog("%06X: %s R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, (!IMM_1 ? "PACK " : "UNPACK"), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 val = RN;
+ uint32_t val = RN;
//BUG! if (RM == 0) // Pack
if (IMM_1 == 0) // Pack
WriteLog("%06X: LOAD (R%02u), R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 mask[4] = { 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00 };
+ uint32_t mask[4] = { 0x00000000, 0xFF000000, 0xFFFF0000, 0xFFFFFF00 };
// if ((RM >= 0xF03000) && (RM <= 0xF03FFF))
RN = GPUReadLong(RM & 0xFFFFFFFC, GPU);
// RN = GPUReadLong(RM & 0x00FFFFFC, GPU);
WriteLog("%06X: LOAD (R14+$%02X), R%02u [NCZ:%u%u%u, R14+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[14]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN);
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2);
+ uint32_t address = gpu_reg[14] + (gpu_convert_zero[IMM_1] << 2);
if ((RM >= 0xF03000) && (RM <= 0xF03FFF))
RN = GPUReadLong(address & 0xFFFFFFFC, GPU);
WriteLog("%06X: LOAD (R15+$%02X), R%02u [NCZ:%u%u%u, R15+$%02X=%08X, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1] << 2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, gpu_convert_zero[IMM_1] << 2, gpu_reg[15]+(gpu_convert_zero[IMM_1] << 2), IMM_2, RN);
#endif
#ifdef GPU_CORRECT_ALIGNMENT
- uint32 address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2);
+ uint32_t address = gpu_reg[15] + (gpu_convert_zero[IMM_1] << 2);
if ((RM >= 0xF03000) && (RM <= 0xF03FFF))
RN = GPUReadLong(address & 0xFFFFFFFC, GPU);
{
#ifdef GPU_DIS_MOVEI
if (doGPUDis)
- WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, (uint32)GPUReadWord(gpu_pc) | ((uint32)GPUReadWord(gpu_pc + 2) << 16), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
+ WriteLog("%06X: MOVEI #$%08X, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, (uint32_t)GPUReadWord(gpu_pc) | ((uint32_t)GPUReadWord(gpu_pc + 2) << 16), IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
// This instruction is followed by 32-bit value in LSW / MSW format...
- RN = (uint32)GPUReadWord(gpu_pc, GPU) | ((uint32)GPUReadWord(gpu_pc + 2, GPU) << 16);
+ RN = (uint32_t)GPUReadWord(gpu_pc, GPU) | ((uint32_t)GPUReadWord(gpu_pc + 2, GPU) << 16);
gpu_pc += 4;
#ifdef GPU_DIS_MOVEI
if (doGPUDis)
if (doGPUDis)
WriteLog("%06X: IMULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- RN = (int16)RN * (int16)RM;
+ RN = (int16_t)RN * (int16_t)RM;
SET_ZN(RN);
#ifdef GPU_DIS_IMULT
if (doGPUDis)
if (doGPUDis)
WriteLog("%06X: MULT R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- RN = (uint16)RM * (uint16)RN;
+ RN = (uint16_t)RM * (uint16_t)RN;
SET_ZN(RN);
#ifdef GPU_DIS_MULT
if (doGPUDis)
if (doGPUDis)
WriteLog("%06X: BCLR #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 res = RN & ~(1 << IMM_1);
+ uint32_t res = RN & ~(1 << IMM_1);
RN = res;
SET_ZN(res);
#ifdef GPU_DIS_BCLR
if (doGPUDis)
WriteLog("%06X: BSET #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 res = RN | (1 << IMM_1);
+ uint32_t res = RN | (1 << IMM_1);
RN = res;
SET_ZN(res);
#ifdef GPU_DIS_BSET
static void gpu_opcode_imacn(void)
{
- uint32 res = (int16)RM * (int16)(RN);
+ uint32_t res = (int16_t)RM * (int16_t)(RN);
gpu_acc += res;
}
static void gpu_opcode_mtoi(void)
{
- uint32 _RM = RM;
- uint32 res = RN = (((int32)_RM >> 8) & 0xFF800000) | (_RM & 0x007FFFFF);
+ uint32_t _RM = RM;
+ uint32_t res = RN = (((int32_t)_RM >> 8) & 0xFF800000) | (_RM & 0x007FFFFF);
SET_ZN(res);
}
static void gpu_opcode_normi(void)
{
- uint32 _RM = RM;
- uint32 res = 0;
+ uint32_t _RM = RM;
+ uint32_t res = 0;
if (_RM)
{
static void gpu_opcode_mmult(void)
{
int count = gpu_matrix_control & 0x0F; // Matrix width
- uint32 addr = gpu_pointer_to_matrix; // In the GPU's RAM
- int64 accum = 0;
- uint32 res;
+ uint32_t addr = gpu_pointer_to_matrix; // In the GPU's RAM
+ int64_t accum = 0;
+ uint32_t res;
if (gpu_matrix_control & 0x10) // Column stepping
{
for(int i=0; i<count; i++)
{
- int16 a;
+ int16_t a;
if (i & 0x01)
- a = (int16)((gpu_alternate_reg[IMM_1 + (i >> 1)] >> 16) & 0xFFFF);
+ a = (int16_t)((gpu_alternate_reg[IMM_1 + (i >> 1)] >> 16) & 0xFFFF);
else
- a = (int16)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF);
+ a = (int16_t)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF);
- int16 b = ((int16)GPUReadWord(addr + 2, GPU));
+ int16_t b = ((int16_t)GPUReadWord(addr + 2, GPU));
accum += a * b;
addr += 4 * count;
}
{
for(int i=0; i<count; i++)
{
- int16 a;
+ int16_t a;
if (i & 0x01)
- a = (int16)((gpu_alternate_reg[IMM_1 + (i >> 1)] >> 16) & 0xFFFF);
+ a = (int16_t)((gpu_alternate_reg[IMM_1 + (i >> 1)] >> 16) & 0xFFFF);
else
- a = (int16)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF);
+ a = (int16_t)(gpu_alternate_reg[IMM_1 + (i >> 1)] & 0xFFFF);
- int16 b = ((int16)GPUReadWord(addr + 2, GPU));
+ int16_t b = ((int16_t)GPUReadWord(addr + 2, GPU));
accum += a * b;
addr += 4;
}
}
- RN = res = (int32)accum;
+ RN = res = (int32_t)accum;
// carry flag to do (out of the last add)
SET_ZN(res);
}
{
if (gpu_div_control & 0x01) // 16.16 division
{
- RN = ((uint64)RN << 16) / RM;
- gpu_remain = ((uint64)RN << 16) % RM;
+ RN = ((uint64_t)RN << 16) / RM;
+ gpu_remain = ((uint64_t)RN << 16) % RM;
}
else
{
else
RN = 0xFFFFFFFF;
-/* uint32 _RM=RM;
- uint32 _RN=RN;
+/* uint32_t _RM=RM;
+ uint32_t _RN=RN;
if (_RM)
{
if (gpu_div_control & 1)
{
- gpu_remain = (((uint64)_RN) << 16) % _RM;
+ gpu_remain = (((uint64_t)_RN) << 16) % _RM;
if (gpu_remain&0x80000000)
gpu_remain-=_RM;
- RN = (((uint64)_RN) << 16) / _RM;
+ RN = (((uint64_t)_RN) << 16) / _RM;
}
else
{
static void gpu_opcode_imultn(void)
{
- uint32 res = (int32)((int16)RN * (int16)RM);
- gpu_acc = (int32)res;
+ uint32_t res = (int32_t)((int16_t)RN * (int16_t)RM);
+ gpu_acc = (int32_t)res;
SET_FLAG_Z(res);
SET_FLAG_N(res);
}
if (doGPUDis)
WriteLog("%06X: NEG R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 res = -RN;
+ uint32_t res = -RN;
SET_ZNC_SUB(0, RN, res);
RN = res;
#ifdef GPU_DIS_NEG
#endif
// Was a bug here...
// (Look at Aaron's code: If r1 = 32, then 32 - 32 = 0 which is wrong!)
- int32 r1 = 32 - IMM_1;
- uint32 res = RN << r1;
+ int32_t r1 = 32 - IMM_1;
+ uint32_t res = RN << r1;
SET_ZN(res); gpu_flag_c = (RN >> 31) & 1;
RN = res;
#ifdef GPU_DIS_SHLQ
if (doGPUDis)
WriteLog("%06X: SHRQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- int32 r1 = gpu_convert_zero[IMM_1];
- uint32 res = RN >> r1;
+ int32_t r1 = gpu_convert_zero[IMM_1];
+ uint32_t res = RN >> r1;
SET_ZN(res); gpu_flag_c = RN & 1;
RN = res;
#ifdef GPU_DIS_SHRQ
if (doGPUDis)
WriteLog("%06X: ROR R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- uint32 r1 = RM & 0x1F;
- uint32 res = (RN >> r1) | (RN << (32 - r1));
+ uint32_t r1 = RM & 0x1F;
+ uint32_t res = (RN >> r1) | (RN << (32 - r1));
SET_ZN(res); gpu_flag_c = (RN >> 31) & 1;
RN = res;
#ifdef GPU_DIS_ROR
if (doGPUDis)
WriteLog("%06X: RORQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 r1 = gpu_convert_zero[IMM_1 & 0x1F];
- uint32 r2 = RN;
- uint32 res = (r2 >> r1) | (r2 << (32 - r1));
+ uint32_t r1 = gpu_convert_zero[IMM_1 & 0x1F];
+ uint32_t r2 = RN;
+ uint32_t res = (r2 >> r1) | (r2 << (32 - r1));
RN = res;
SET_ZN(res); gpu_flag_c = (r2 >> 31) & 0x01;
#ifdef GPU_DIS_RORQ
static void gpu_opcode_sha(void)
{
/* int dreg = jaguar.op & 31;
- int32 r1 = (int32)jaguar.r[(jaguar.op >> 5) & 31];
- uint32 r2 = jaguar.r[dreg];
- uint32 res;
+ int32_t r1 = (int32_t)jaguar.r[(jaguar.op >> 5) & 31];
+ uint32_t r2 = jaguar.r[dreg];
+ uint32_t res;
CLR_ZNC;
if (r1 < 0)
}
else
{
- res = (r1 >= 32) ? ((int32)r2 >> 31) : ((int32)r2 >> r1);
+ res = (r1 >= 32) ? ((int32_t)r2 >> 31) : ((int32_t)r2 >> r1);
jaguar.FLAGS |= (r2 << 1) & 2;
}
jaguar.r[dreg] = res;
if (doGPUDis)
WriteLog("%06X: SHA R%02u, R%02u [NCZ:%u%u%u, R%02u=%08X, R%02u=%08X] -> ", gpu_pc-2, IMM_1, IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
- uint32 res;
+ uint32_t res;
- if ((int32)RM < 0)
+ if ((int32_t)RM < 0)
{
- res = ((int32)RM <= -32) ? 0 : (RN << -(int32)RM);
+ res = ((int32_t)RM <= -32) ? 0 : (RN << -(int32_t)RM);
gpu_flag_c = RN >> 31;
}
else
{
- res = ((int32)RM >= 32) ? ((int32)RN >> 31) : ((int32)RN >> (int32)RM);
+ res = ((int32_t)RM >= 32) ? ((int32_t)RN >> 31) : ((int32_t)RN >> (int32_t)RM);
gpu_flag_c = RN & 0x01;
}
RN = res;
WriteLog("[NCZ:%u%u%u, R%02u=%08X, R%02u=%08X]\n", gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_1, RM, IMM_2, RN);
#endif
-/* int32 sRM=(int32)RM;
- uint32 _RN=RN;
+/* int32_t sRM=(int32_t)RM;
+ uint32_t _RN=RN;
if (sRM<0)
{
- uint32 shift=-sRM;
+ uint32_t shift=-sRM;
if (shift>=32) shift=32;
gpu_flag_c=(_RN&0x80000000)>>31;
while (shift)
}
else
{
- uint32 shift=sRM;
+ uint32_t shift=sRM;
if (shift>=32) shift=32;
gpu_flag_c=_RN&0x1;
while (shift)
{
- _RN=((int32)_RN)>>1;
+ _RN=((int32_t)_RN)>>1;
shift--;
}
}
if (doGPUDis)
WriteLog("%06X: SHARQ #%u, R%02u [NCZ:%u%u%u, R%02u=%08X] -> ", gpu_pc-2, gpu_convert_zero[IMM_1], IMM_2, gpu_flag_n, gpu_flag_c, gpu_flag_z, IMM_2, RN);
#endif
- uint32 res = (int32)RN >> gpu_convert_zero[IMM_1];
+ uint32_t res = (int32_t)RN >> gpu_convert_zero[IMM_1];
SET_ZN(res); gpu_flag_c = RN & 0x01;
RN = res;
#ifdef GPU_DIS_SHARQ
if (RM & 0x80000000) // Shift left
{
gpu_flag_c = RN >> 31;
- RN = ((int32)RM <= -32 ? 0 : RN << -(int32)RM);
+ RN = ((int32_t)RM <= -32 ? 0 : RN << -(int32_t)RM);
}
else // Shift right
{
projects / virtualjaguar / blobdiff