From 0c6f353827a94eb52c21e677658000f98452b247 Mon Sep 17 00:00:00 2001 From: Shamus Hammons Date: Thu, 1 Oct 2009 20:44:14 +0000 Subject: [PATCH] Virtual 6809 is close to being 100% at this point; at least StarGem works at this point. Minor formatting tweaks to 6809 disassembler. --- src/dis6809.cpp | 13 +- src/stargem2.cpp | 1 + src/v6809.cpp | 2406 ++-------------------------------------------- 3 files changed, 65 insertions(+), 2355 deletions(-) diff --git a/src/dis6809.cpp b/src/dis6809.cpp index 7205dc0..dbeeeda 100755 --- a/src/dis6809.cpp +++ b/src/dis6809.cpp @@ -193,20 +193,21 @@ iregs[4][2] = {"X", "Y", "U", "S" }; // static void DisplayBytes(uint16 src, uint32 dst) { + char buf[20], buf2[20]; + + buf[0] = 0; WriteLog("%04X: ", src); - uint8 cnt = 0; // Init counter... if (src > dst) dst += 0x10000; // That should fix the FFFF bug... for(uint32 i=src; i // @@ -11,10 +11,7 @@ // JLH 06/15/2006 Added changelog ;-) // JLH 06/15/2006 Scrubbed all BYTE, WORD & DWORD references from the code // JLH 11/11/2006 Removed all SignedX() references -// - -// Mebbe someday I'll get around to fixing the core to be more like V65C02... -// We have a start... ;-) +// JLH 09/29/2009 Converted V6809 to macro implementation! // #define __DEBUG__ @@ -41,21 +38,18 @@ bool disasm = false;//so we can extern this shit #define SET_N16(r) (flagN = ((r) & 0x8000) >> 15) #define SET_V(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x80) >> 7) #define SET_V16(a,b,r) (flagV = (((b) ^ (a) ^ (r) ^ ((r) >> 1)) & 0x8000) >> 15) +#define SET_H(a,b,r) (flagH = (((a) ^ (b) ^ (r)) & 0x10) >> 4) //Not sure that this code is computing the carry correctly... Investigate! [Seems to be] -#define SET_C_ADD(a,b) (flagC = ((uint8)(b) > (uint8)(~(a)) ? 1 : 0)) +//#define SET_C_ADD(a,b) (flagC = ((uint8)(b) > (uint8)(~(a)) ? 1 : 0)) //#define SET_C_SUB(a,b) (regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C)) -#define SET_C_CMP(a,b) (flagC = ((uint8)(b) >= (uint8)(a) ? 1 : 0)) +//#define SET_C_CMP(a,b) (flagC = ((uint8)(b) >= (uint8)(a) ? 1 : 0)) #define SET_ZN(r) SET_N(r); SET_Z(r) #define SET_ZN16(r) SET_N16(r); SET_Z(r) -#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) +//#define SET_ZNC_ADD(a,b,r) SET_N(r); SET_Z(r); SET_C_ADD(a,b) //#define SET_ZNC_SUB(a,b,r) SET_N(r); SET_Z(r); SET_C_SUB(a,b) -#define SET_ZNC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b) +//#define SET_ZNC_CMP(a,b,r) SET_N(r); SET_Z(r); SET_C_CMP(a,b) -//Small problem with the EA_ macros: ABS macros don't increment the PC!!! !!! FIX !!! -//Hmm, why not do like we did for READ_ABS*??? -//Because the EA_* macros are usually used as an argument to a function call, that's why. -//Now, we CAN fix it using FetchMemW()!!! [DONE] #define EA_IMM regs.pc++ #define EA_DP (regs.dp << 8) | regs.RdMem(regs.pc++) #define EA_IDX DecodeIDX(regs.RdMem(regs.pc++)) @@ -228,6 +222,7 @@ uint16 ReadEXG(uint8 code) retval = regs.b; break; case 10: + PACK_FLAGS; retval = regs.cc; break; case 11: @@ -264,7 +259,7 @@ void WriteEXG(uint8 code, uint16 data) case 9: regs.b = data & 0xFF; break; case 10: - regs.cc = data & 0xFF; break; + regs.cc = data & 0xFF; UNPACK_FLAGS; break; case 11: regs.dp = data & 0xFF; break; } @@ -423,8 +418,6 @@ uint16 DecodeIDX(uint8 code) return addr; } -#if 1 - // // 6809 OPCODE IMPLEMENTATION // @@ -454,7 +447,7 @@ uint16 DecodeIDX(uint8 code) #define OP_ADC_HANDLER(m, acc) \ uint16 sum = (uint16)acc + (m) + (uint16)flagC; \ flagC = (sum >> 8) & 0x01; \ - flagH = (sum >> 4) & 0x01; \ + SET_H(m, acc, sum); \ SET_V(m, acc, sum); \ acc = sum & 0xFF; \ SET_ZN(acc) @@ -542,7 +535,7 @@ static void OpF9(void) // ADCB ABS #define OP_ADD_HANDLER(m, acc) \ uint16 sum = (uint16)(acc) + (m); \ flagC = (sum >> 8) & 0x01; \ - flagH = (sum >> 4) & 0x01; \ + SET_H(m, acc, sum); \ SET_V(m, acc, sum); \ (acc) = sum & 0xFF; \ SET_ZN(acc) @@ -1784,14 +1777,22 @@ static void Op12() // NOP { } +/* +D3F8: A6 47 LDA (7),U CC=--H----- A=30 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FA +D3FA: 8B 01 ADDA #$01 CC=--H----- A=31 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FC +D3FC: 19 DAA CC=--H----- A=37 B=00 DP=9C X=3C72 Y=CE5C S=BFFF U=BAF0 PC=D3FD +*/ + static void Op19() // DAA { uint16 result = (uint16)regs.a; - if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H)) +// if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H)) + if ((regs.a & 0x0F) > 0x09 || flagH) result += 0x06; - if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09)) +// if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09)) + if ((regs.a & 0xF0) > 0x90 || flagC || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09)) result += 0x60; regs.a = (uint8)result; @@ -2100,17 +2101,31 @@ static void OpBD(void) // JSR ABS static void Op1E(void) // EXG { + // If bit 3 & 7 are not equal, $FF is the result (undocumented)... + uint8 m = READ_IMM; uint8 reg1 = m >> 4, reg2 = m & 0x0F; - uint16 acc = ReadEXG(reg1); - WriteEXG(reg1, ReadEXG(reg2)); - WriteEXG(reg2, acc); + uint16 acc1 = ReadEXG(reg1); + uint16 acc2 = ReadEXG(reg2); + + // If bit 3 & 7 are not equal, $FF is the result (undocumented)... + if (((m >> 4) ^ m) & 0x08) + acc1 = acc2 = 0xFF; + + WriteEXG(reg1, acc2); + WriteEXG(reg2, acc1); } static void Op1F(void) // TFR { uint8 m = READ_IMM; - WriteEXG(m & 0x0F, ReadEXG(m >> 4)); + uint16 acc = ReadEXG(m >> 4); + + // If bit 3 & 7 are not equal, $FF is the result (undocumented)... + if (((m >> 4) ^ m) & 0x08) + acc = 0xFF; + + WriteEXG(m & 0x0F, acc); } /* @@ -2607,6 +2622,10 @@ static void Op34(void) // PSHS regs.cc = PACK_FLAGS; PUSHS(regs.cc); } + + // Count bits in each nybble to come up with correct cycle counts... + uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; + regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]); } static void Op35(void) // PULS @@ -2632,6 +2651,10 @@ static void Op35(void) // PULS PULLS16(regs.u); if (m & 0x80) PULLS16(regs.pc); + + // Count bits in each nybble to come up with correct cycle counts... + uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; + regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]); } static void Op36(void) // PHSU @@ -2657,6 +2680,10 @@ static void Op36(void) // PHSU regs.cc = PACK_FLAGS; PUSHU(regs.cc); } + + // Count bits in each nybble to come up with correct cycle counts... + uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; + regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]); } static void Op37(void) // PULU @@ -2682,6 +2709,10 @@ static void Op37(void) // PULU PULLU16(regs.s); if (m & 0x80) PULLU16(regs.pc); + + // Count bits in each nybble to come up with correct cycle counts... + uint8 bitCount[16] = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; + regs.clock += (1 * bitCount[m & 0x0F]) + (2 * bitCount[m >> 4]); } /* @@ -3203,2329 +3234,6 @@ static void Op01(void) Op00(); // NEG DP } -#else - -// -// Page zero instructions... -// - -static void Op00(void) // NEG DP -{ - addr = (regs.dp << 8) | regs.RdMem(regs.pc++); - tmp = 256 - regs.RdMem(addr); - regs.WrMem(addr, tmp); - - (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp & 0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (tmp > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry - - regs.clock += 6; -} - -static void Op01(void) // NEG DP (Undocumented) -{ - Op00(); -} - -static void Op03(void) // COM DP -{ - addr = (regs.dp << 8) | regs.RdMem(regs.pc++); - tmp = 0xFF ^ regs.RdMem(addr); - regs.WrMem(addr, tmp); - - regs.cc &= 0xFD; regs.cc |= 0x01; // CLV SEC - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - - regs.clock += 6; -} - -static void Op04(void) // LSR DP -{ - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); - tmp = regs.RdMem(addr); - (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry - tmp >>= 1; regs.WrMem(addr, tmp); - regs.cc &= 0xF7; // CLN - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - regs.clock += 6; -} -static void Op06(void) // ROR DP -{ - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr); - tmp = (tmp2>>1) + (regs.cc&0x01)*128; - regs.WrMem(addr, tmp); - (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op07(void) // ASR DP -{ - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); tmp = regs.RdMem(addr); - (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - tmp >>= 1; - if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set - regs.WrMem(addr, tmp); - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op08(void) // LSL DP -{ - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); // NEEDS OVERFLOW ADJUSTMENT - tmp = regs.RdMem(addr); - (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - tmp <<= 1; - regs.WrMem(addr, tmp); - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op09(void) // ROL DP -{ - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); uint8 tmp2 = regs.RdMem(addr); - tmp = (tmp2<<1) + (regs.cc&0x01); - regs.WrMem(addr, tmp); - (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - ((tmp2&0x80)^((tmp2<<1)&0x80) ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op0A(void) // DEC DP -{ - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); - tmp = regs.RdMem(addr) - 1; - regs.WrMem(addr, tmp); - (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op0C(void) // INC DP -{ - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); - tmp = regs.RdMem(addr) + 1; - regs.WrMem(addr, tmp); - (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op0D(void) // TST DP -{ - tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // CLV - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op0E(void) // JMP DP -{ - regs.pc = (regs.dp<<8) | regs.RdMem(regs.pc++); - regs.clock += 3; -} -static void Op0F(void) // CLR DP -{ - regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), 0); - regs.cc &= 0xF0; regs.cc |= 0x04; // CLN, SEZ, CLV, CLC - regs.clock += 6; -} - -static void Op12(void) // NOP -{ - regs.clock += 2; -} - -static void Op13(void) // SYNC -{ - // Fix this so it does the right thing (software interrupt!) - regs.clock += 2; -} - -static void Op16(void) // LBRA -{ -// regs.pc += SignedW(FetchW()); - regs.pc += FetchW(); // No need to make signed, both are 16 bit quantities - - regs.clock += 5; -} - -static void Op17(void) // LBSR -{ - uint16 word = FetchW(); - regs.WrMem(--regs.s, regs.pc & 0xFF); - regs.WrMem(--regs.s, regs.pc >> 8); -// regs.pc += SignedW(addr); - regs.pc += word; // No need to make signed, both are 16 bit - - regs.clock += 9; -} - -static void Op19(void) // DAA -{ -#if 0 - uint8 result = regs.a; - - if ((regs.cc&0x20) || ((regs.a&0x0F) > 0x09)) // H set or lo nyb too big? - { -// regs.a += 0x06; - result += 0x06; - regs.cc |= 0x20; // Then adjust & set half carry - } - - if ((regs.cc&0x01) || (regs.a > 0x9F)) // C set or hi nyb too big? - { -// regs.a += 0x60; - result += 0x60; - regs.cc |= 0x01; // Then adjust & set carry - } - - regs.a = result; - - regs.cc &= 0xF1; // CL NZV - if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag -#else - uint16 result = (uint16)regs.a; - - if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H)) - result += 0x06; - - if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09)) - result += 0x60; - - regs.a = (uint8)result; -// SET_ZN(result); -// CLR_V; // Not sure this is correct... - regs.cc &= 0xF1; // CL NZV - if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag -// flagC |= (result & 0x100) >> 8; // Overwrite carry if it was 0, otherwise, ignore - regs.cc |= (result & 0x100) > 8; -#endif - regs.clock += 2; -} - -static void Op1A(void) // ORCC # -{ - regs.cc |= regs.RdMem(regs.pc++); - - regs.clock += 3; -} - -static void Op1C(void) // ANDCC # -{ - regs.cc &= regs.RdMem(regs.pc++); - - regs.clock += 3; -} - -static void Op1D(void) // SEX -{ - (regs.b & 0x80 ? regs.a = 0xFF : regs.a = 0x00); - - ((regs.a | regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a & 0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - - regs.clock += 2; -} - -static void Op1E(void) // EXG -{ - tmp = regs.RdMem(regs.pc++); - addr = ReadEXG(tmp >> 4); - WriteEXG(tmp >> 4, ReadEXG(tmp & 0xF)); - WriteEXG(tmp & 0xF, addr); - - regs.clock += 8; -} - -static void Op1F(void) // TFR -{ - tmp = regs.RdMem(regs.pc++); - WriteEXG(tmp&0xF, ReadEXG(tmp>>4)); - regs.clock += 7; -} - -static void Op20(void) // BRA -{ -// regs.pc += SignedB(regs.RdMem(regs.pc++)); // Branch always - regs.pc += (int16)(int8)regs.RdMem(regs.pc) + 1; // Branch always - - regs.clock += 3; -} - -static void Op21(void) // BRN -{ - regs.RdMem(regs.pc++); - - regs.clock += 3; -} - -static void Op22(void) // BHI -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (!(regs.cc & 0x05)) - regs.pc += word; - - regs.clock += 3; -} - -static void Op23(void) // BLS -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (regs.cc & 0x05) - regs.pc += word; - - regs.clock += 3; -} - -static void Op24(void) // BCC (BHS) -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (!(regs.cc & 0x01)) - regs.pc += word; - - regs.clock += 3; -} - -static void Op25(void) // BCS (BLO) -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (regs.cc & 0x01) - regs.pc += word; - - regs.clock += 3; -} - -static void Op26(void) // BNE -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (!(regs.cc & 0x04)) - regs.pc += word; - - regs.clock += 3; -} - -static void Op27(void) // BEQ -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (regs.cc & 0x04) - regs.pc += word; - - regs.clock += 3; -} - -static void Op28(void) // BVC -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (!(regs.cc & 0x02)) - regs.pc += word; - - regs.clock += 3; -} - -static void Op29(void) // BVS -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (regs.cc & 0x02) - regs.pc += word; - - regs.clock += 3; -} - -static void Op2A(void) // BPL -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (!(regs.cc & 0x08)) - regs.pc += word; - - regs.clock += 3; -} - -static void Op2B(void) // BMI -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (regs.cc & 0x08) - regs.pc += word; - - regs.clock += 3; -} - -static void Op2C(void) // BGE -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))) - regs.pc += word; - - regs.clock += 3; -} - -static void Op2D(void) // BLT -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)) - regs.pc += word; - - regs.clock += 3; -} - -static void Op2E(void) // BGT -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))) - regs.pc += word; - - regs.clock += 3; -} - -static void Op2F(void) // BLE -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - - if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))) - regs.pc += word; - - regs.clock += 3; -} - -static void Op30(void) // LEAX -{ - regs.x = DecodeIDX(regs.RdMem(regs.pc++)); - (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - regs.clock += 4; -} -static void Op31(void) // LEAY -{ - regs.y = DecodeIDX(regs.RdMem(regs.pc++)); - (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - regs.clock += 4; -} -static void Op32(void) // LEAS -{ - regs.s = DecodeIDX(regs.RdMem(regs.pc++)); - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - regs.clock += 4; -} -static void Op33(void) // LEAU -{ - regs.u = DecodeIDX(regs.RdMem(regs.pc++)); - (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - regs.clock += 4; -} -static void Op34(void) // PSHS -{ - tmp = regs.RdMem(regs.pc++); - if (tmp&0x80) { regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8); } - if (tmp&0x40) { regs.WrMem(--regs.s, regs.u&0xFF); regs.WrMem(--regs.s, regs.u>>8); } - if (tmp&0x20) { regs.WrMem(--regs.s, regs.y&0xFF); regs.WrMem(--regs.s, regs.y>>8); } - if (tmp&0x10) { regs.WrMem(--regs.s, regs.x&0xFF); regs.WrMem(--regs.s, regs.x>>8); } - if (tmp&0x08) regs.WrMem(--regs.s, regs.dp); - if (tmp&0x04) regs.WrMem(--regs.s, regs.b); - if (tmp&0x02) regs.WrMem(--regs.s, regs.a); - if (tmp&0x01) regs.WrMem(--regs.s, regs.cc); - regs.clock += 5; -} -static void Op35(void) // PULS -{ - tmp = regs.RdMem(regs.pc++); - if (tmp&0x01) regs.cc = regs.RdMem(regs.s++); - if (tmp&0x02) regs.a = regs.RdMem(regs.s++); - if (tmp&0x04) regs.b = regs.RdMem(regs.s++); - if (tmp&0x08) regs.dp = regs.RdMem(regs.s++); - if (tmp&0x10) regs.x = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - if (tmp&0x20) regs.y = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - if (tmp&0x40) regs.u = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - if (tmp&0x80) regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - regs.clock += 5; -} - -static void Op36(void) // PSHU -{ - tmp = regs.RdMem(regs.pc++); - - if (tmp & 0x80) { regs.WrMem(--regs.u, regs.pc & 0xFF); regs.WrMem(--regs.u, regs.pc >> 8); } - if (tmp & 0x40) { regs.WrMem(--regs.u, regs.s & 0xFF); regs.WrMem(--regs.u, regs.s >> 8); } - if (tmp & 0x20) { regs.WrMem(--regs.u, regs.y & 0xFF); regs.WrMem(--regs.u, regs.y >> 8); } - if (tmp & 0x10) { regs.WrMem(--regs.u, regs.x & 0xFF); regs.WrMem(--regs.u, regs.x >> 8); } - if (tmp & 0x08) regs.WrMem(--regs.u, regs.dp); - if (tmp & 0x04) regs.WrMem(--regs.u, regs.b); - if (tmp & 0x02) regs.WrMem(--regs.u, regs.a); - if (tmp & 0x01) regs.WrMem(--regs.u, regs.cc); - - regs.clock += 5; -} - -static void Op37(void) // PULU -{ - tmp = regs.RdMem(regs.pc++); - if (tmp&0x01) regs.cc = regs.RdMem(regs.u++); - if (tmp&0x02) regs.a = regs.RdMem(regs.u++); - if (tmp&0x04) regs.b = regs.RdMem(regs.u++); - if (tmp&0x08) regs.dp = regs.RdMem(regs.u++); - if (tmp&0x10) regs.x = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++); - if (tmp&0x20) regs.y = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++); - if (tmp&0x40) regs.s = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++); - if (tmp&0x80) regs.pc = (regs.RdMem(regs.u++)<<8) | regs.RdMem(regs.u++); - regs.clock += 5; -} -static void Op39(void) // RTS -{ - regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - regs.clock += 5; -} -static void Op3B(void) // RTI -{ - regs.cc = regs.RdMem(regs.s++); - if (regs.cc&0x80) // If E flag set, pull all regs - { - regs.a = regs.RdMem(regs.s++); regs.b = regs.RdMem(regs.s++); regs.dp = regs.RdMem(regs.s++); - regs.x = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - regs.y = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - regs.u = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); - regs.clock += 15; - } - else - { - regs.clock += 6; - } - regs.pc = (regs.RdMem(regs.s++)<<8) | regs.RdMem(regs.s++); -} -static void Op3C(void) // CWAI -{ - regs.cc &= regs.RdMem(regs.pc++); regs.cc |= 0x80; - regs.clock += 1000000; // Force interrupt -} -static void Op3D(void) // MUL -{ - addr = regs.a * regs.b; regs.a = addr>>8; regs.b = addr&0xFF; - (addr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero - (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry - regs.clock += 11; -} -static void Op3E(void) // RESET -{ -} -static void Op3F(void) // SWI -{ -} -static void Op40(void) // NEGA -{ - regs.a = 256 - regs.a; - (regs.a > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry - (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op43(void) // COMA -{ - regs.a ^= 0xFF; - regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op44(void) // LSRA -{ - (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry - regs.a >>= 1; - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op46(void) // RORA -{ - tmp = regs.a; regs.a = (tmp>>1) + (regs.cc&0x01)*128; - (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op47(void) // ASRA -{ - (regs.a&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - regs.a >>= 1; // Do the shift - if (regs.a&0x40) regs.a |= 0x80; // Set neg if it was set - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op48(void) // LSLA [Keep checking from here...] -{ - (regs.a&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - regs.a <<= 1; - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op49(void) // ROLA -{ - tmp = regs.a; regs.a = (tmp<<1) + (regs.cc&0x01); - (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op4A(void) // DECA -{ - regs.a--; - (regs.a == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op4C(void) // INCA - { - regs.a++; - (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op4D(void) // TSTA - { - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op4F(void) // CLRA -{ - regs.a = 0; - regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC - regs.clock += 2; -} -static void Op50(void) // NEGB - { - regs.b = 256 - regs.b; -// ((regs.b^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry - (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.b > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry - regs.clock += 2; - } -static void Op53(void) // COMB - { - regs.b ^= 0xFF; - regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op54(void) // LSRB - { - (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry - regs.b >>= 1; - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op56(void) // RORB - { - tmp = regs.b; regs.b = (regs.b >> 1) + (regs.cc&0x01)*128; - (tmp&0x01 ? regs.cc |=0x01 : regs.cc &= 0xFE); // Shift bit into carry - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op57(void) // ASRB - { - (regs.b&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - regs.b >>= 1; // Do the shift - if (regs.b&0x40) regs.b |= 0x80; // Set neg if it was set - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op58(void) // LSLB - { - (regs.b&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - regs.b <<= 1; - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op59(void) // ROLB -{ - tmp = regs.b; - regs.b = (tmp<<1) + (regs.cc&0x01); - (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op5A(void) // DECB - { - regs.b--; - (regs.b == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op5C(void) // INCB - { - regs.b++; - (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op5D(void) // TSTB - { - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op5F(void) // CLRB - { - regs.b = 0; - regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC - regs.clock += 2; - } -static void Op60(void) // NEG IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr); uint8 res = 256 - tmp; - regs.WrMem(addr, res); -// ((res^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry - (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry - regs.clock += 6; - } -static void Op63(void) // COM IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr) ^ 0xFF; - regs.WrMem(addr, tmp); - regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op64(void) // LSR IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr); - (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry - tmp >>= 1; regs.WrMem(addr, tmp); - regs.cc &= 0xF7; // CLN - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - regs.clock += 6; - } -static void Op66(void) // ROR IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr); uint8 tmp2 = tmp; - tmp = (tmp >> 1) + (regs.cc&0x01)*128; - regs.WrMem(addr, tmp); - (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op67(void) // ASR IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr); - (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - tmp >>= 1; - if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set - regs.WrMem(addr, tmp); - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op68(void) // LSL IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr); - (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - tmp <<= 1; - regs.WrMem(addr, tmp); - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op69(void) // ROL IDX -{ - uint8 tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - tmp = (tmp2<<1) + (regs.cc&0x01); - regs.WrMem(addr, tmp); - (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; -} -static void Op6A(void) // DEC IDX - { - uint8 tmp; uint16 addr; - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr) - 1; - regs.WrMem(addr, tmp); - (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op6C(void) // INC IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - tmp = regs.RdMem(addr) + 1; - regs.WrMem(addr, tmp); - (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op6D(void) // TST IDX - { - tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op6E(void) // JMP IDX -{ - regs.pc = DecodeIDX(regs.RdMem(regs.pc++)); - regs.clock += 3; -} -static void Op6F(void) // CLR IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.WrMem(addr, 0); - regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC - regs.clock += 6; -} -static void Op70(void) // NEG ABS - { - addr = FetchW(); - tmp = regs.RdMem(addr); uint8 res = 256 - tmp; - regs.WrMem(addr, res); - (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (res&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (res > 0x7F ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry - regs.clock += 7; - } -static void Op73(void) // COM ABS - { - addr = FetchW(); - tmp = regs.RdMem(addr) ^ 0xFF; - regs.WrMem(addr, tmp); - regs.cc &= 0xFD; regs.cc |= 0x01; // CLV, SEC - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op74(void) // LSR ABS - { - addr = FetchW(); - tmp = regs.RdMem(addr); - (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift low bit into carry - tmp >>= 1; regs.WrMem(addr, tmp); - regs.cc &= 0xF7; // CLN - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - regs.clock += 7; - } -static void Op76(void) // ROR ABS - { - uint8 tmp; uint16 addr; - addr = FetchW(); - tmp = regs.RdMem(addr); uint8 tmp2 = tmp; - tmp = (tmp >> 1) + (regs.cc&0x01)*128; - regs.WrMem(addr, tmp); - (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op77(void) // ASR ABS - { - uint8 tmp; uint16 addr; - addr = FetchW(); - tmp = regs.RdMem(addr); - (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry - tmp >>= 1; - if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set - regs.WrMem(addr, tmp); - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op78(void) // LSL ABS - { - uint8 tmp; uint16 addr; - addr = FetchW(); - tmp = regs.RdMem(addr); - (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - tmp <<= 1; - regs.WrMem(addr, tmp); - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op79(void) // ROL ABS -{ - uint8 tmp2 = regs.RdMem(FetchW()); - tmp = (tmp2<<1) + (regs.cc&0x01); - regs.WrMem(addr, tmp); - (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; -} -static void Op7A(void) // DEC ABS - { - uint8 tmp; uint16 addr; - addr = FetchW(); - tmp = regs.RdMem(addr) - 1; - regs.WrMem(addr, tmp); - (tmp == 0x7F ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op7C(void) // INC ABS - { - uint8 tmp; uint16 addr; - addr = FetchW(); - tmp = regs.RdMem(addr) + 1; - regs.WrMem(addr, tmp); - (tmp == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } - -static void Op7D(void) // TST ABS -{ - uint8 tmp = regs.RdMem(FetchW()); - - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - - regs.clock += 7; -} - -static void Op7E(void) // JMP ABS -{ - regs.pc = FetchW(); - regs.clock += 3; -} -static void Op7F(void) // CLR ABS - { - regs.WrMem(FetchW(), 0); - regs.cc &= 0xF0; regs.cc |= 0x04; // Set NZVC - regs.clock += 7; - } -static void Op80(void) // SUBA # -{ - uint8 tmp = regs.RdMem(regs.pc++); uint8 as = regs.a; - regs.a -= tmp; - (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op81(void) // CMPA # -{ - tmp = regs.RdMem(regs.pc++); - uint8 db = regs.a - tmp; - (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op82(void) // SBCA # -{ - tmp = regs.RdMem(regs.pc++); uint8 as = regs.a; - regs.a = regs.a - tmp - (regs.cc&0x01); - (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void Op83(void) // SUBD # -{ - addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr; - dr -= addr; - (ds < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.a = dr>>8; regs.b = dr&0xFF; - regs.clock += 4; -} -static void Op85(void) // BITA # - { - tmp = regs.a & regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op86(void) // LDA # - { - regs.a = regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op88(void) // EORA # - { - regs.a ^= regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op8A(void) // ORA # - { - regs.a |= regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op8C(void) // CMPX # -{ - addr = FetchW(); - uint16 dw = regs.x - addr; - (regs.x < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.x^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; -} - -static void Op8D(void) // Bregs.s -{ - uint16 word = (int16)(int8)regs.RdMem(regs.pc++); - regs.WrMem(--regs.s, regs.pc & 0xFF); - regs.WrMem(--regs.s, regs.pc >> 8); - regs.pc += word; - - regs.clock += 7; -} - -static void Op8E(void) // LDX # - { - regs.x = FetchW(); - regs.cc &= 0xFD; // CLV - (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 3; - } -static void Op90(void) // SUBA DP - { - tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a; - regs.a -= tmp; - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; - } -static void Op91(void) // CMPA DP - { - tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - uint8 db = regs.a - tmp; - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; - } -static void Op92(void) // SBCA DP -{ - tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 as = regs.a; - regs.a = regs.a - tmp - (regs.cc&0x01); - (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; -} -static void Op93(void) // SUBD DP -{ - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); uint16 dr = (regs.a<<8)|regs.b, ds = dr; - uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - dr -= adr2; - (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.a = dr>>8; regs.b = dr&0xFF; - regs.clock += 6; -} -static void Op84(void) // ANDA # - { - regs.a &= regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void Op94(void) // ANDA DP -{ - regs.a &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.a == 0) regs.cc |= 0x04; // Adjust Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag - regs.clock += 4; -} -static void Op95(void) // BITA DP - { - tmp = regs.a & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void Op96(void) // LDA DP -{ - regs.a = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xF1; // CLN CLZ CLV - if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag - regs.clock += 4; -} -static void Op97(void) // STA DP - { - regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.a); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void Op98(void) // EORA DP - { - regs.a ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void Op9A(void) // ORA DP - { - regs.a |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void Op9C(void) // CMPX DP - { - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - uint16 dw = regs.x - adr2; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.x < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.x^adr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 6; - } -static void Op9D(void) // JSR DP - { - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); - regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8); - regs.pc = addr; // JSR to DP location... - regs.clock += 7; - } -static void Op9E(void) // LDX DP - { - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); - regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void Op9F(void) // STX DP - { - addr = (regs.dp<<8) | regs.RdMem(regs.pc++); - regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF); - regs.cc &= 0xFD; // CLV - (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void OpA0(void) // SUBA IDX - { - tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a; - regs.a -= tmp; - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; - } -static void OpA1(void) // CMPA IDX - { - tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - uint8 db = regs.a - tmp; - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; - } -static void OpA2(void) // SBCA IDX -{ - tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 as = regs.a; - regs.a = regs.a - tmp - (regs.cc&0x01); - (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; -} -static void OpA3(void) // SUBD IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); uint16 dr = (regs.a<<8)|regs.b, ds = dr; - uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - dr -= adr2; - (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.a = dr>>8; regs.b = dr&0xFF; - regs.clock += 6; -} -static void OpA4(void) // ANDA IDX - { - regs.a &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpA5(void) // BITA IDX - { - tmp = regs.a & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpA6(void) // LDA IDX -{ - regs.a = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag - regs.clock += 4; -} -static void OpA7(void) // STA IDX -{ - regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.a); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.a == 0) regs.cc |= 0x04; // Set Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Set Negative flag - regs.clock += 4; -} -static void OpA8(void) // EORA IDX - { - regs.a ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpAA(void) // ORA IDX -{ - regs.a |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; -} -static void OpAC(void) // CMPX IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - uint16 dw = regs.x - addr2; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 6; -} -static void OpAD(void) // JSR IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8); - regs.pc = addr; // Jregs.s directly to IDX ptr - regs.clock += 7; -} -static void OpAE(void) // LDX IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpAF(void) // STX IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.x == 0) regs.cc |= 0x04; // Set Zero flag - if (regs.x&0x8000) regs.cc |= 0x08; // Set Negative flag - regs.clock += 5; -} -static void OpB0(void) // SUBA ABS - { - tmp = regs.RdMem(FetchW()); uint8 as = regs.a; - regs.a -= tmp; - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 5; - } -static void OpB1(void) // CMPA ABS - { - tmp = regs.RdMem(FetchW()); - uint8 db = regs.a - tmp; - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 5; - } -static void OpB2(void) // SBCA ABS -{ - tmp = regs.RdMem(FetchW()); uint8 as = regs.a; - regs.a = regs.a - tmp - (regs.cc&0x01); - (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpB3(void) // SUBD ABS -{ - addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b, ds = dr; - uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - dr -= adr2; - (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - (dr == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.a = dr>>8; regs.b = dr&0xFF; - regs.clock += 7; -} -static void OpB4(void) // ANDA ABS -{ - regs.a &= regs.RdMem(FetchW()); - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpB5(void) // BITA ABS -{ - tmp = regs.a & regs.RdMem(FetchW()); - regs.cc &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpB6(void) // LDA ABS -{ - regs.a = regs.RdMem(FetchW()); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpB7(void) // STA ABS -{ - regs.WrMem(FetchW(), regs.a); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpB8(void) // EORA ABS -{ - regs.a ^= regs.RdMem(FetchW()); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpBA(void) // ORA ABS -{ - regs.a |= regs.RdMem(FetchW()); - regs.cc &= 0xFD; // CLV - (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpBC(void) // CMPX ABS -{ - addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - uint16 dw = regs.x - addr2; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.x^addr2^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 7; -} -static void OpBD(void) // JSR ABS -{ - addr = FetchW(); - regs.WrMem(--regs.s, regs.pc&0xFF); regs.WrMem(--regs.s, regs.pc>>8); - regs.pc = addr; // Go to absolute address (Not indir) - regs.clock += 8; -} - -static void OpBE(void) // LDX ABS -{ -// addr = FetchW(); -// regs.x = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1); - regs.x = RdMemW(FetchW()); - - regs.cc &= 0xFD; // CLV - (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - - regs.clock += 6; -} - -static void OpBF(void) // STX ABS -{ -// addr = FetchW(); -// regs.WrMem(addr, regs.x>>8); regs.WrMem(addr+1, regs.x&0xFF); - WrMemW(FetchW(), regs.x); - - regs.cc &= 0xFD; // CLV - (regs.x == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.x&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - - regs.clock += 6; -} - -static void OpC0(void) // SUBB # - { - tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b; - regs.b -= tmp; - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 2; - } -static void OpC1(void) // CMPB # - { - tmp = regs.RdMem(regs.pc++); - uint8 db = regs.b - tmp; - (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void OpC2(void) // SBCB # -{ - tmp = regs.RdMem(regs.pc++); uint8 bs = regs.b; - regs.b = regs.b - tmp - (regs.cc&0x01); - (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; -} -static void OpC4(void) // ANDB # - { - regs.b &= regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void OpC5(void) // BITB # -{ - tmp = regs.b & regs.RdMem(regs.pc++); - regs.cc &= 0xF1; // CLV CLZ CLN - if (tmp == 0) regs.cc |= 0x04; // Set Zero flag - if (tmp&0x80) regs.cc |= 0x08; // Set Negative flag - regs.clock += 2; -} -static void OpC6(void) // LDB # -{ - regs.b = regs.RdMem(regs.pc++); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.b == 0) regs.cc |= 0x04; // Set Zero flag - if (regs.b&0x80) regs.cc |= 0x08; // Set Negative flag - regs.clock += 2; -} -static void OpC8(void) // EORB # - { - regs.b ^= regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void OpCA(void) // ORB # - { - regs.b |= regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 2; - } -static void OpCC(void) // LDD # -{ - regs.a = regs.RdMem(regs.pc++); regs.b = regs.RdMem(regs.pc++); - regs.cc &= 0xFD; // CLV - ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 3; -} -static void OpCE(void) // LDU # -{ - regs.u = FetchW(); - regs.cc &= 0xFD; // CLV - (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 3; -} -static void OpD0(void) // SUBB DP -{ - tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b; - regs.b -= tmp; - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; -} -static void OpD1(void) // CMPB DP -{ - tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - uint8 db = regs.b - tmp; - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; -} -static void OpD2(void) // SBCB DP -{ - tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); uint8 bs = regs.b; - regs.b = regs.b - tmp - (regs.cc&0x01); - (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; -} -static void OpD4(void) // ANDB DP - { - regs.b &= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpD5(void) // BITB DP - { - tmp = regs.b & regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpD6(void) // LDB DP -{ - regs.b = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; -} -static void OpD7(void) // STB DP - { - regs.WrMem((regs.dp<<8)|regs.RdMem(regs.pc++), regs.b); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpD8(void) // EORB DP - { - regs.b ^= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpDA(void) // ORB DP - { - regs.b |= regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++)); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpDC(void) // LDD DP -{ - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpDD(void) // STD DP -{ - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b); - regs.cc &= 0xFD; // CLV - ((regs.a|regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpDE(void) // LDU DP -{ - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpDF(void) // STU DP -{ - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF); - regs.cc &= 0xFD; // CLV - (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; -} -static void OpE0(void) // SUBB IDX -{ - tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b; - regs.b -= tmp; - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; -} -static void OpE1(void) // CMPB IDX -{ - tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - uint8 db = regs.b - tmp; - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 4; -} -static void OpE2(void) // SBCB IDX -{ - tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); uint8 bs = regs.b; - regs.b = regs.b - tmp - (regs.cc&0x01); - (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; -} -static void OpE4(void) // ANDB IDX - { - regs.b &= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpE5(void) // BITB IDX - { - tmp = regs.b & regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpE6(void) // LDB IDX - { - regs.b = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpE7(void) // STB IDX -{ - regs.WrMem(DecodeIDX(regs.RdMem(regs.pc++)), regs.b); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.b == 0) regs.cc |= 0x04; // Adjust Zero flag - if (regs.b&0x80) regs.cc |= 0x08; // Adjust Negative flag - regs.clock += 4; -} -static void OpE8(void) // EORB IDX - { - regs.b ^= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpEA(void) // ORB IDX - { - regs.b |= regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++))); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void OpEC(void) // LDD IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1); - regs.cc &= 0xF1; // CLV CLZ CLN - if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag - regs.clock += 5; -} -static void OpED(void) // STD IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b); - regs.cc &= 0xF1; // CLV CLZ CLZ - if (!(regs.a|regs.b)) regs.cc |= 0x04; // Adjust Zero flag - if (regs.a&0x80) regs.cc |= 0x08; // Adjust Negative flag - regs.clock += 5; -} -static void OpEE(void) // LDU IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag - if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag - regs.clock += 5; -} -static void OpEF(void) // STU IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.u == 0) regs.cc |= 0x04; // Set Zero flag - if (regs.u&0x8000) regs.cc |= 0x08; // Set Negative flag - regs.clock += 5; -} -static void OpF0(void) // SUBB ABS - { - tmp = regs.RdMem(FetchW()); uint8 bs = regs.b; - regs.b -= tmp; - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - } -static void OpF1(void) // CMPB ABS - { - tmp = regs.RdMem(FetchW()); - uint8 db = regs.b - tmp; - (db == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (db&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 5; - } -static void OpF2(void) // SBCB ABS -{ - tmp = regs.RdMem(FetchW()); uint8 bs = regs.b; - regs.b = regs.b - tmp - (regs.cc&0x01); - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (bs < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow - regs.clock += 5; -} -static void OpF4(void) // ANDB ABS - { - regs.b &= regs.RdMem(FetchW()); - regs.cc &= 0xFD; // Clear oVerflow flag - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void OpF5(void) // BITB ABS - { - tmp = regs.b & regs.RdMem(FetchW()); - regs.cc &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void OpF6(void) // LDB ABS - { - regs.b = regs.RdMem(FetchW()); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void OpF7(void) // STB ABS - { - regs.WrMem(FetchW(), regs.b); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void OpF8(void) // EORB ABS - { - regs.b ^= regs.RdMem(FetchW()); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void OpFA(void) // ORB ABS - { - regs.b |= regs.RdMem(FetchW()); - regs.cc &= 0xFD; // CLV - (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 5; - } -static void OpFC(void) // LDD ABS - { - addr = FetchW(); - regs.a = regs.RdMem(addr); regs.b = regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void OpFD(void) // STD ABS - { - addr = FetchW(); - regs.WrMem(addr, regs.a); regs.WrMem(addr+1, regs.b); - regs.cc &= 0xFD; // CLV - ((regs.a+regs.b) == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void OpFE(void) // LDU ABS - { - addr = FetchW(); - regs.u = (regs.RdMem(addr) << 8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void OpFF(void) // STU ABS - { - addr = FetchW(); - regs.WrMem(addr, regs.u>>8); regs.WrMem(addr+1, regs.u&0xFF); - regs.cc &= 0xFD; // CLV - (regs.u == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.u&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } - -// -// Page one opcodes' execute code -// - -static void Op1021(void) // LBRN -{ - addr = FetchW(); - - regs.clock += 5; -} - -static void Op1022(void) // LBHI -{ - uint16 word = FetchW(); - - if (!((regs.cc & 0x01) | (regs.cc & 0x04))) - regs.pc += word; - - regs.clock += 5; -} - -static void Op1023(void) // LBLS -{ - uint16 word = FetchW(); - - if ((regs.cc & 0x01) | (regs.cc & 0x04)) - regs.pc += word; - - regs.clock += 5; -} - -static void Op1024(void) // LBCC (LBHS) -{ - uint16 word = FetchW(); - - if (!(regs.cc & 0x01)) - regs.pc += word; - - regs.clock += 5; -} - -static void Op1025(void) // LBCS (LBLO) -{ - uint16 word = FetchW(); - - if (regs.cc & 0x01) - regs.pc += word; - - regs.clock += 5; -} - -static void Op1026(void) // LBNE -{ - uint16 word = FetchW(); - - if (!(regs.cc & 0x04)) - regs.pc += word; - - regs.clock += 5; -} - -static void Op1027(void) // LBEQ -{ - uint16 word = FetchW(); - - if (regs.cc & 0x04) - regs.pc += word; - - regs.clock += 5; -} - -static void Op1028(void) // LBVC -{ - uint16 word = FetchW(); - - if (!(regs.cc & 0x02)) - regs.pc += word; - - regs.clock += 5; -} - -static void Op1029(void) // LBVS -{ - uint16 word = FetchW(); - - if (regs.cc & 0x02) - regs.pc += word; - - regs.clock += 5; -} - -static void Op102A(void) // LBPL -{ - uint16 word = FetchW(); - - if (!(regs.cc & 0x08)) - regs.pc += word; - - regs.clock += 5; -} - -static void Op102B(void) // LBMI -{ - uint16 word = FetchW(); - - if (regs.cc & 0x08) - regs.pc += word; - - regs.clock += 5; -} - -static void Op102C(void) // LBGE -{ - uint16 word = FetchW(); - - if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))) - regs.pc += word; - - regs.clock += 5; -} - -static void Op102D(void) // LBLT -{ - uint16 word = FetchW(); - - if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)) - regs.pc += word; - - regs.clock += 5; -} - -static void Op102E(void) // LBGT -{ - uint16 word = FetchW(); - - if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))) - regs.pc += word; - - regs.clock += 5; -} - -static void Op102F(void) // LBLE -{ - uint16 word = FetchW(); - - if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))) - regs.pc += word; - - regs.clock += 5; -} - -static void Op103F(void) // SWI2 (Not yet implemented) -{ - regs.clock += 20; -} -static void Op1083(void) // CMPD # - { - addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b; - uint16 dw = dr - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((dr^addr^dw^((uint16)regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 5; - } -static void Op108C(void) // CMPY # - { - addr = FetchW(); - uint16 dw = regs.y - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.y^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 5; - } -static void Op108E(void) // LDY # - { - regs.y = FetchW(); - regs.cc &= 0xFD; // CLV - (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void Op1093(void) // CMPD DP - { - uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++), dr = (regs.a<<8)|regs.b; - addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1); - uint16 dw = dr - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((dr^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 7; - } -static void Op109C(void) // CMPY DP - { - uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++); - addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1); - uint16 dw = regs.y - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - ((regs.y^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 7; - } - -static void Op109E(void) // LDY DP - { - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } - -static void Op109F(void) // STY DP - { - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF); - regs.cc &= 0xFD; // CLV - (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op10A3(void) // CMPD IDX -{ - uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++)), dr = (regs.a<<8)|regs.b; - addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1); - uint16 dw = dr - addr; - regs.cc &= 0xF0; // CLC CLV CLZ CLN - if (dr < addr) regs.cc |= 0x01; // Set Carry flag - if ((dr^addr^dw^(regs.cc<<15))&0x8000) regs.cc |= 0x02; // Set oVerflow - if (dw == 0) regs.cc |= 0x04; // Set Zero flag - if (dw&0x8000) regs.cc |= 0x08; // Set Negative flag - regs.clock += 7; -} -static void Op10AC(void) // CMPY IDX - { - uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++)); - addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1); - uint16 dw = regs.y - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.y^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 7; - } -static void Op10AE(void) // LDY IDX -{ - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - regs.cc &= 0xF1; // CLV CLZ CLN - if (regs.y == 0) regs.cc |= 0x04; // Adjust Zero flag - if (regs.y&0x8000) regs.cc |= 0x08; // Adjust Negative flag - regs.clock += 6; -} -static void Op10AF(void) // STY IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF); - regs.cc &= 0xFD; // CLV - (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op10B3(void) // CMPD ABS - { - addr = FetchW(); uint16 dr = (regs.a<<8)|regs.b; - uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - uint16 dw = dr - addr2; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (dr < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^dr^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 8; - } -static void Op10BC(void) // CMPY ABS - { - addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - uint16 dw = regs.y - addr2; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.y < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.y^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 8; - } -static void Op10BE(void) // LDY ABS - { - addr = FetchW(); - regs.y = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op10BF(void) // STY ABS - { - addr = FetchW(); - regs.WrMem(addr, regs.y>>8); regs.WrMem(addr+1, regs.y&0xFF); - regs.cc &= 0xFD; // CLV - (regs.y == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.y&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op10CE(void) // LDS # - { - regs.s = FetchW(); - regs.cc &= 0xFD; // CLV - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 4; - } -static void Op10DE(void) // LDS DP - { - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op10DF(void) // STS DP - { - addr = (regs.dp<<8)|regs.RdMem(regs.pc++); - regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF); - regs.cc &= 0xFD; // CLV - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op10EE(void) // LDS IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op10EF(void) // STS IDX - { - addr = DecodeIDX(regs.RdMem(regs.pc++)); - regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF); - regs.cc &= 0xFD; // CLV - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 6; - } -static void Op10FE(void) // LDS ABS - { - addr = FetchW(); - regs.s = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - regs.cc &= 0xFD; // CLV - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; - } -static void Op10FF(void) // STS ABS -{ - addr = FetchW(); - regs.WrMem(addr, regs.s>>8); regs.WrMem(addr+1, regs.s&0xFF); - regs.cc &= 0xFD; // CLV - (regs.s == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - regs.clock += 7; -} - -// -// Page two opcodes' execute code -// - -static void Op113F(void) // SWI3 - { - regs.clock += 20; - } -static void Op1183(void) // CMPU # - { - addr = FetchW(); - uint16 dw = regs.u - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 5; - } -static void Op118C(void) // CMPS # - { - addr = FetchW(); - uint16 dw = regs.s - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 5; - } -static void Op1193(void) // CMPU DP - { - uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++); - addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1); - uint16 dw = regs.u - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 7; - } -static void Op119C(void) // CMPS DP - { - uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++); - addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1); - uint16 dw = regs.s - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 7; - } -static void Op11A3(void) // CMPU IDX - { - uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++)); - addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1); - uint16 dw = regs.u - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.u^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 7; - } -static void Op11AC(void) // CMPS IDX - { - uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++)); - addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1); - uint16 dw = regs.s - addr; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.s^addr^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 7; - } -static void Op11B3(void) // CMPU ABS - { - addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - uint16 dw = regs.u - addr2; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.u < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.u^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 8; - } - -static void Op11BC(void) // CMPS ABS -{ - addr = FetchW(); uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1); - uint16 dw = regs.s - addr2; - (dw == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7); // Adjust Negative flag - (regs.s < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust Carry flag - (((regs.cc<<15)^regs.s^addr2^dw)&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl - regs.clock += 8; -} -#endif - //temp, for testing... #ifdef __DEBUG__ @@ -5828,7 +3536,7 @@ if (disasm) WriteLog(" IRQ taken...\n"); } } #ifdef __DEBUG__ -if (disasm) WriteLog("\tCC=%s%s%s%s%s%s%s%s A=%02X B=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n", +if (disasm) WriteLog("CC=%s%s%s%s%s%s%s%s A=%02X B=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n", (flagE ? "E" : "-"), (flagF ? "F" : "-"), (flagH ? "H" : "-"), (flagI ? "I" : "-"), (flagN ? "N" : "-"), (flagZ ? "Z" : "-"), (flagV ? "V" : "-"), (flagC ? "C" : "-"), regs.a, regs.b, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/ -- 2.37.2