Finally fixed problems with demo mode.

[stargem2] / src / v6808.cpp

diff --git a/src/v6808.cpp b/src/v6808.cpp
old mode 100755 (executable)
new mode 100644 (file)
index ac1352c..3e9b5e2
--- a/src/v6808.cpp
+++ b/src/v6808.cpp
@@ -1,10 +1,10 @@
 //
 // Virtual 6808 Emulator v2.1
 //
-// by James L. Hammons
+// by James Hammons
 // (C) 2006 Underground Software
 //
-// JLH = James L. Hammons <jlhamm@acm.org>
+// JLH = James Hammons <jlhamm@acm.org>
 //
 // WHO  WHEN        WHAT
 // ---  ----------  ------------------------------------------------------------
@@ -19,15 +19,6 @@
 
 // NOTE: V6808_STATE_WAI is not handled in the main loop correctly. !!! FIX !!!
 
-// Some random thoughts: Could there be a performance gain by breaking
-// out the flags in regs.cc into separate uint8_t variables (or bools)?
-// You'd have to convert on entering and exiting the emulation loop, but I
-// think the perfomance hit would be negligible compared to the gain in not
-// having to mask and shift flags all the time. Investigate after the
-// conversion to macro style opcodes is completed. :-)
-// [DONE--remain to be seen if there is any performance increase]
-
-//#define __DEBUG__
 #define TEST_DONT_BRANCH_OPTIMIZATION
 
 #include "v6808.h"
@@ -151,11 +142,11 @@ static inline uint16_t FetchMemW(uint16_t address)
 //
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Add                     |ADDA |8B 2 2|9B 3 2|AB 5 2|BB 4 3|      |A=A+M     |T TTTT|
-                        |ADDB |CB 2 2|DB 3 2|EB 5 2|FB 4 3|      |B=B+M     |T TTTT|
-Add Accumulators        |ABA  |      |      |      |      |1B 2 1|A=A+B     |T TTTT|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Add                 |ADDA |8B 2 2|9B 3 2|AB 5 2|BB 4 3|      |A=A+M     |T TTTT|
+                    |ADDB |CB 2 2|DB 3 2|EB 5 2|FB 4 3|      |B=B+M     |T TTTT|
+Add Accumulators    |ABA  |      |      |      |      |1B 2 1|A=A+B     |T TTTT|
 */
 
 // ADD opcodes
@@ -222,10 +213,10 @@ static void Op1B(void)                                                    // ABA
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Add with Carry          |ADCA |89 2 2|99 3 2|A9 5 2|B9 4 3|      |A=A+M+C   |T TTTT|
-                        |ADCB |C9 2 2|D9 3 2|E9 5 2|F9 4 3|      |B=B+M+C   |T TTTT|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Add with Carry      |ADCA |89 2 2|99 3 2|A9 5 2|B9 4 3|      |A=A+M+C   |T TTTT|
+                    |ADCB |C9 2 2|D9 3 2|E9 5 2|F9 4 3|      |B=B+M+C   |T TTTT|
 */
 
 // ADC opcodes
@@ -287,10 +278,10 @@ static void OpF9(void)                                                    // ADCB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-And                     |ANDA |84 2 2|94 3 2|A4 5 2|B4 4 3|      |A=A+M     |  TTR |
-                        |ANDB |C4 2 2|D4 3 2|E4 5 2|F4 4 3|      |B=B+M     |  TTR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+And                 |ANDA |84 2 2|94 3 2|A4 5 2|B4 4 3|      |A=A+M     |  TTR |
+                    |ANDB |C4 2 2|D4 3 2|E4 5 2|F4 4 3|      |B=B+M     |  TTR |
 */
 
 // AND opcodes
@@ -349,10 +340,10 @@ static void OpF4(void)                                                    // ANDB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Bit Test                |BITA |85 2 2|95 3 2|A5 5 2|B5 4 3|      |A+M       |  TTR |
-                        |BITB |C5 2 2|D5 3 2|E5 5 2|F5 4 3|      |B+M       |  TTR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Bit Test            |BITA |85 2 2|95 3 2|A5 5 2|B5 4 3|      |A+M       |  TTR |
+                    |BITB |C5 2 2|D5 3 2|E5 5 2|F5 4 3|      |B+M       |  TTR |
 */
 
 // BIT opcodes
@@ -410,11 +401,11 @@ static void OpF5(void)                                                    // BITB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Clear                   |CLR  |      |      |6F 7 2|7F 6 3|      |M=00      |  RSRR|
-                        |CLRA |      |      |      |      |4F 2 1|A=00      |  RSRR|
-                        |CLRB |      |      |      |      |5F 2 1|B=00      |  RSRR|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Clear               |CLR  |      |      |6F 7 2|7F 6 3|      |M=00      |  RSRR|
+                    |CLRA |      |      |      |      |4F 2 1|A=00      |  RSRR|
+                    |CLRB |      |      |      |      |5F 2 1|B=00      |  RSRR|
 */
 
 // CLR opcodes
@@ -448,11 +439,11 @@ static void Op5F(void)                                                    // CLRB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Compare                 |CMPA |81 2 2|91 3 2|A1 5 2|B1 4 3|      |A-M       |  TTTT|
-                        |CMPB |C1 2 2|D1 3 2|E1 5 2|F1 4 3|      |B-M       |  TTTT|
-Compare Accumulators    |CBA  |      |      |      |      |11 2 1|A-B       |  TTTT|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Compare             |CMPA |81 2 2|91 3 2|A1 5 2|B1 4 3|      |A-M       |  TTTT|
+                    |CMPB |C1 2 2|D1 3 2|E1 5 2|F1 4 3|      |B-M       |  TTTT|
+Compare Accumulators|CBA  |      |      |      |      |11 2 1|A-B       |  TTTT|
 */
 
 // CMP opcodes
@@ -519,11 +510,11 @@ static void Op11(void)                                                    // CBA
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Complement 1's          |COM  |      |      |63 7 2|73 6 3|      |M=-M      |  TTRS|
-                        |COMA |      |      |      |      |43 2 1|A=-A      |  TTRS|
-                        |COMB |      |      |      |      |53 2 1|B=-B      |  TTRS|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Complement 1's      |COM  |      |      |63 7 2|73 6 3|      |M=-M      |  TTRS|
+                    |COMA |      |      |      |      |43 2 1|A=-A      |  TTRS|
+                    |COMB |      |      |      |      |53 2 1|B=-B      |  TTRS|
 */
 
 // COM opcodes
@@ -561,11 +552,11 @@ static void Op53(void)                                                    // COMB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Complement 2's          |NEG  |      |      |60 7 2|70 6 3|      |M=00-M    |  TT12|
-                        |NEGA |      |      |      |      |40 2 1|A=00-A    |  TT12|
-                        |NEGB |      |      |      |      |50 2 1|B=00-B    |  TT12|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Complement 2's      |NEG  |      |      |60 7 2|70 6 3|      |M=00-M    |  TT12|
+                    |NEGA |      |      |      |      |40 2 1|A=00-A    |  TT12|
+                    |NEGB |      |      |      |      |50 2 1|B=00-B    |  TT12|
 */
 
 // NEG opcodes
@@ -603,9 +594,9 @@ static void Op50(void)                                                      // NEGB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Decimal Adjust          |DAA  |      |      |      |      |19 2 1|*         |  TTT3|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Decimal Adjust      |DAA  |      |      |      |      |19 2 1|*         |  TTT3|
 */
 
 static void Op19(void)                                                 // DAA
@@ -625,11 +616,11 @@ static void Op19(void)                                                    // DAA
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Decrement               |DEC  |      |      |6A 7 2|7A 6 3|      |M=M-1     |  TT4 |
-                        |DECA |      |      |      |      |4A 2 1|A=A-1     |  TT4 |
-                        |DECB |      |      |      |      |5A 2 1|B=B-1     |  TT4 |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Decrement           |DEC  |      |      |6A 7 2|7A 6 3|      |M=M-1     |  TT4 |
+                    |DECA |      |      |      |      |4A 2 1|A=A-1     |  TT4 |
+                    |DECB |      |      |      |      |5A 2 1|B=B-1     |  TT4 |
 */
 
 // DEC opcodes
@@ -666,10 +657,10 @@ static void Op5A(void)                                                    // DECB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Exclusive OR            |EORA |88 2 2|98 3 2|A8 5 2|B8 4 3|      |A=A(+)M   |  TTR |
-                        |EORB |C8 2 2|D8 3 2|E8 5 2|F8 4 3|      |B=B(+)M   |  TTR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Exclusive OR        |EORA |88 2 2|98 3 2|A8 5 2|B8 4 3|      |A=A(+)M   |  TTR |
+                    |EORB |C8 2 2|D8 3 2|E8 5 2|F8 4 3|      |B=B(+)M   |  TTR |
 */
 
 // EOR opcodes
@@ -728,11 +719,11 @@ static void OpF8(void)                                                    // EORB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Increment               |INC  |      |      |6C 7 2|7C 6 3|      |M=M+1     |  TT5 |
-                        |INCA |      |      |      |      |4C 2 1|A=A+1     |  TT5 |
-                        |INCB |      |      |      |      |5C 2 1|B=B+1     |  TT5 |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Increment           |INC  |      |      |6C 7 2|7C 6 3|      |M=M+1     |  TT5 |
+                    |INCA |      |      |      |      |4C 2 1|A=A+1     |  TT5 |
+                    |INCB |      |      |      |      |5C 2 1|B=B+1     |  TT5 |
 */
 
 // INC opcodes
@@ -769,10 +760,10 @@ static void Op5C(void)                                                    // INCB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Load Accumulator        |LDAA |86 2 2|96 3 2|A6 5 2|B6 4 3|      |A=M       |  TTR |
-                        |LDAB |C6 2 2|D6 3 2|E6 5 2|F6 4 3|      |B=M       |  TTR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Load Accumulator    |LDAA |86 2 2|96 3 2|A6 5 2|B6 4 3|      |A=M       |  TTR |
+                    |LDAB |C6 2 2|D6 3 2|E6 5 2|F6 4 3|      |B=M       |  TTR |
 */
 
 // LDA opcodes
@@ -831,10 +822,10 @@ static void OpF6(void)                                                    // LDAB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-OR, Inclusive           |ORAA |8A 2 2|9A 3 2|AA 5 2|BA 4 3|      |A=A+M     |  TTR |
-                        |ORAB |CA 2 2|DA 3 2|EA 5 2|FA 4 3|      |B=B+M     |  TTR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+OR, Inclusive       |ORAA |8A 2 2|9A 3 2|AA 5 2|BA 4 3|      |A=A+M     |  TTR |
+                    |ORAB |CA 2 2|DA 3 2|EA 5 2|FA 4 3|      |B=B+M     |  TTR |
 */
 
 // ORA opcodes
@@ -893,12 +884,12 @@ static void OpFA(void)                                                    // ORAB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Push Data               |PSHA |      |      |      |      |36 4 1|Msp=A, *- |      |
-                        |PSHB |      |      |      |      |37 4 1|Msp=B, *- |      |
-Pull Data               |PULA |      |      |      |      |32 4 1|A=Msp, *+ |      |
-                        |PULB |      |      |      |      |33 4 1|B=Msp, *+ |      |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Push Data           |PSHA |      |      |      |      |36 4 1|Msp=A, *- |      |
+                    |PSHB |      |      |      |      |37 4 1|Msp=B, *- |      |
+Pull Data           |PULA |      |      |      |      |32 4 1|A=Msp, *+ |      |
+                    |PULB |      |      |      |      |33 4 1|B=Msp, *+ |      |
 */
 
 static void Op36(void)                                                 // PSHA
@@ -922,11 +913,11 @@ static void Op33(void)                                                    // PULB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Rotate Left             |ROL  |      |      |69 7 2|79 6 3|      |Memory  *1|  TT6T|
-                        |ROLA |      |      |      |      |49 2 1|Accum A *1|  TT6T|
-                        |ROLB |      |      |      |      |59 2 1|Accum B *1|  TT6T|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Rotate Left         |ROL  |      |      |69 7 2|79 6 3|      |Memory  *1|  TT6T|
+                    |ROLA |      |      |      |      |49 2 1|Accum A *1|  TT6T|
+                    |ROLB |      |      |      |      |59 2 1|Accum B *1|  TT6T|
 */
 
 // ROL opcodes
@@ -965,11 +956,11 @@ static void Op59(void)                                                    // ROLB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Rotate Right            |ROR  |      |      |66 7 2|76 6 3|      |Memory  *2|  TT6T|
-                        |RORA |      |      |      |      |46 2 1|Accum A *2|  TT6T|
-                        |RORB |      |      |      |      |56 2 1|Accum B *2|  TT6T|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Rotate Right        |ROR  |      |      |66 7 2|76 6 3|      |Memory  *2|  TT6T|
+                    |RORA |      |      |      |      |46 2 1|Accum A *2|  TT6T|
+                    |RORB |      |      |      |      |56 2 1|Accum B *2|  TT6T|
 */
 
 // ROR opcodes
@@ -1008,11 +999,11 @@ static void Op56(void)                                                   // RORB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Arithmetic Shift Left   |ASL  |      |      |68 7 2|78 6 3|      |Memory  *3|  TT6T|
-                        |ASLA |      |      |      |      |48 2 1|Accum A *3|  TT6T|
-                        |ASLB |      |      |      |      |58 2 1|Accum B *3|  TT6T|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Arithmetic Shft Left|ASL  |      |      |68 7 2|78 6 3|      |Memory  *3|  TT6T|
+                    |ASLA |      |      |      |      |48 2 1|Accum A *3|  TT6T|
+                    |ASLB |      |      |      |      |58 2 1|Accum B *3|  TT6T|
 */
 
 // ASL opcodes
@@ -1051,11 +1042,11 @@ static void Op58(void)                                                  // ASLB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Arithmetic Shift Right  |ASR  |      |      |67 7 2|77 6 3|      |Memory  *4|  TT6T|
-                        |ASRA |      |      |      |      |47 2 1|Accum A *4|  TT6T|
-                        |ASRB |      |      |      |      |57 2 1|Accum B *4|  TT6T|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Arithmetic Shft Rght|ASR  |      |      |67 7 2|77 6 3|      |Memory  *4|  TT6T|
+                    |ASRA |      |      |      |      |47 2 1|Accum A *4|  TT6T|
+                    |ASRB |      |      |      |      |57 2 1|Accum B *4|  TT6T|
 */
 
 // ASR opcodes
@@ -1094,11 +1085,11 @@ static void Op57(void)                                                  // ASRB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Logic Shift Right       |LSR  |      |      |64 7 2|74 6 3|      |Memory  *5|  TT6T|
-                        |LSRA |      |      |      |      |44 2 1|Accum A *5|  TT6T|
-                        |LSRB |      |      |      |      |54 2 1|Accum B *5|  TT6T|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Logic Shift Right   |LSR  |      |      |64 7 2|74 6 3|      |Memory  *5|  TT6T|
+                    |LSRA |      |      |      |      |44 2 1|Accum A *5|  TT6T|
+                    |LSRB |      |      |      |      |54 2 1|Accum B *5|  TT6T|
 */
 
 // LSR opcodes
@@ -1137,10 +1128,10 @@ static void Op54(void)                                                  // LSRB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Store Accumulator       |STAA |      |97 4 2|A7 6 2|B7 5 3|      |M=A       |  TTR |
-                        |STAB |      |D7 4 2|E7 6 2|F7 5 3|      |M=B       |  TTR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Store Accumulator   |STAA |      |97 4 2|A7 6 2|B7 5 3|      |M=A       |  TTR |
+                    |STAB |      |D7 4 2|E7 6 2|F7 5 3|      |M=B       |  TTR |
 */
 
 static void Op97(void)                                                 // STAA ZP
@@ -1174,11 +1165,11 @@ static void OpF7(void)                                                  // STAB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Subtract                |SUBA |80 2 2|90 3 2|A0 5 2|B0 4 3|      |A=A-M     |  TTTT|
-                        |SUBB |C0 2 2|D0 3 2|E0 5 2|F0 4 3|      |B=B-M     |  TTTT|
-Subtract Accumulators   |SBA  |      |      |      |      |10 2 1|A=A-B     |  TTTT|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Subtract            |SUBA |80 2 2|90 3 2|A0 5 2|B0 4 3|      |A=A-M     |  TTTT|
+                    |SUBB |C0 2 2|D0 3 2|E0 5 2|F0 4 3|      |B=B-M     |  TTTT|
+Subtract Accumulatrs|SBA  |      |      |      |      |10 2 1|A=A-B     |  TTTT|
 */
 
 // SUB opcodes
@@ -1244,10 +1235,10 @@ static void Op10(void)                                                  // SBA
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Subtract with Carry     |SBCA |82 2 2|92 3 2|A2 5 2|B2 4 3|      |A=A-M-C   |  TTTT|
-                        |SBCB |C2 2 2|D2 3 2|E2 5 2|F2 4 3|      |B=B-M-C   |  TTTT|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Subtract with Carry |SBCA |82 2 2|92 3 2|A2 5 2|B2 4 3|      |A=A-M-C   |  TTTT|
+                    |SBCB |C2 2 2|D2 3 2|E2 5 2|F2 4 3|      |B=B-M-C   |  TTTT|
 */
 
 // SBC opcodes
@@ -1308,10 +1299,10 @@ static void OpF2(void)                                                  // SBCB ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Transfer Accumulators   |TAB  |      |      |      |      |16 2 1|B=A       |  TTR |
-                        |TBA  |      |      |      |      |17 2 1|A=B       |  TTR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Transfer Accumulatrs|TAB  |      |      |      |      |16 2 1|B=A       |  TTR |
+                    |TBA  |      |      |      |      |17 2 1|A=B       |  TTR |
 */
 
 static void Op16(void)                                                 // TAB
@@ -1329,11 +1320,11 @@ static void Op17(void)                                                  // TBA
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Test, Zero/Minus        |TST  |      |      |6D 7 2|7D 6 3|      |M-00      |  TTRR|
-                        |TSTA |      |      |      |      |4D 2 1|A-00      |  TTRR|
-                        |TSTB |      |      |      |      |5D 2 1|B-00      |  TTRR|
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Test, Zero/Minus    |TST  |      |      |6D 7 2|7D 6 3|      |M-00      |  TTRR|
+                    |TSTA |      |      |      |      |4D 2 1|A-00      |  TTRR|
+                    |TSTB |      |      |      |      |5D 2 1|B-00      |  TTRR|
 */
 
 // TST opcodes
@@ -1369,9 +1360,9 @@ static void Op5D(void)                                                    // TSTB
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Compare Index Register  |CPX  |8C 3 3|9C 4 2|AC 6 2|BC 5 3|      |Formula 1 |  7T8 |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Compare Index Regstr|CPX  |8C 3 3|9C 4 2|AC 6 2|BC 5 3|      |Formula 1 |  7T8 |
 */
 
 // CPX opcodes
@@ -1409,12 +1400,12 @@ static void OpBC(void)                                                  // CPX ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Decrement Index Register|DEX  |      |      |      |      |09 4 1|X=X-1     |   T  |
-Dec Stack Pointer       |DES  |      |      |      |      |34 4 1|SP=SP-1   |      |
-Inc Index Regster       |INX  |      |      |      |      |08 4 1|X=X+1     |   T  |
-Inc Stack Pointer       |INS  |      |      |      |      |31 4 1|SP=SP+1   |      |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Decrement Index Regr|DEX  |      |      |      |      |09 4 1|X=X-1     |   T  |
+Dec Stack Pointer   |DES  |      |      |      |      |34 4 1|SP=SP-1   |      |
+Inc Index Regster   |INX  |      |      |      |      |08 4 1|X=X+1     |   T  |
+Inc Stack Pointer   |INS  |      |      |      |      |31 4 1|SP=SP+1   |      |
 */
 
 static void Op09(void)                                                 // DEX
@@ -1440,10 +1431,10 @@ static void Op31(void)                                                  // INS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Load Index Register     |LDX  |CE 3 3|DE 4 2|EE 6 2|FE 5 3|      |Formula 2 |  9TR |
-Load Stack Pointer      |LDS  |8E 3 3|9E 4 2|AE 6 2|BE 5 3|      |Formula 3 |  9TR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Load Index Register |LDX  |CE 3 3|DE 4 2|EE 6 2|FE 5 3|      |Formula 2 |  9TR |
+Load Stack Pointer  |LDS  |8E 3 3|9E 4 2|AE 6 2|BE 5 3|      |Formula 3 |  9TR |
 */
 
 // LD* opcode handler
@@ -1502,10 +1493,10 @@ static void OpBE(void)                                                  // LDS ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Store Index Register    |STX  |      |DF 5 2|EF 7 2|FF 6 3|      |Formula 4 |  9TR |
-Store Stack Pointer     |STS  |      |9F 5 2|AF 7 2|BF 6 3|      |Formula 5 |  9TR |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Store Index Register|STX  |      |DF 5 2|EF 7 2|FF 6 3|      |Formula 4 |  9TR |
+Store Stack Pointer |STS  |      |9F 5 2|AF 7 2|BF 6 3|      |Formula 5 |  9TR |
 */
 
 // ST* opcode handler
@@ -1554,10 +1545,10 @@ static void OpBF(void)                                                  // STS ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Index Reg > Stack Pnter |TXS  |      |      |      |      |35 4 1|SP=X-1    |      |
-Stack Ptr > Index Regtr |TSX  |      |      |      |      |30 4 1|X=SP+1    |      |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Indx Reg > Stack Ptr|TXS  |      |      |      |      |35 4 1|SP=X-1    |      |
+Stack Ptr > Indx Reg|TSX  |      |      |      |      |30 4 1|X=SP+1    |      |
 */
 
 static void Op35(void)                                                 // TXS
@@ -1571,23 +1562,23 @@ static void Op30(void)                                                  // TSX
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Always                  |BRA  |      |20 4 2|      |      |      |none      |      |
-Carry is Clear          |BCC  |      |24 4 2|      |      |      |C=0       |      |
-Carry is Set            |BCS  |      |25 4 2|      |      |      |C=1       |      |
-Equals Zero             |BEQ  |      |27 4 2|      |      |      |Z=1       |      |
-Greater or Equal to Zero|BGE  |      |2C 4 2|      |      |      |N(+)V=0   |      |
-Greater than Zero       |BGT  |      |2E 4 2|      |      |      |Z+N(+)V=0 |      |
-Higher                  |BHI  |      |22 4 2|      |      |      |C+Z=0     |      |
-Less or Equal than Zero |BLE  |      |2F 4 2|      |      |      |Z+N(+)V=1 |      |
-Lower or Same           |BLS  |      |23 4 2|      |      |      |C+Z=1     |      |
-Less Than Zero          |BLT  |      |2D 4 2|      |      |      |N(+)V=1   |      |
-Minus                   |BMI  |      |2B 4 2|      |      |      |N=1       |      |
-Not Zero                |BNE  |      |26 4 2|      |      |      |Z=0       |      |
-Overflow Clear          |BVC  |      |28 4 2|      |      |      |V=0       |      |
-Overflow Set            |BVS  |      |29 4 2|      |      |      |V=1       |      |
-Plus                    |BPL  |      |2A 4 2|      |      |      |N=0       |      |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Always              |BRA  |      |20 4 2|      |      |      |none      |      |
+Carry is Clear      |BCC  |      |24 4 2|      |      |      |C=0       |      |
+Carry is Set        |BCS  |      |25 4 2|      |      |      |C=1       |      |
+Equals Zero         |BEQ  |      |27 4 2|      |      |      |Z=1       |      |
+Greater / Equal to 0|BGE  |      |2C 4 2|      |      |      |N(+)V=0   |      |
+Greater than Zero   |BGT  |      |2E 4 2|      |      |      |Z+N(+)V=0 |      |
+Higher              |BHI  |      |22 4 2|      |      |      |C+Z=0     |      |
+Less / Equal than 0 |BLE  |      |2F 4 2|      |      |      |Z+N(+)V=1 |      |
+Lower or Same       |BLS  |      |23 4 2|      |      |      |C+Z=1     |      |
+Less Than Zero      |BLT  |      |2D 4 2|      |      |      |N(+)V=1   |      |
+Minus               |BMI  |      |2B 4 2|      |      |      |N=1       |      |
+Not Zero            |BNE  |      |26 4 2|      |      |      |Z=0       |      |
+Overflow Clear      |BVC  |      |28 4 2|      |      |      |V=0       |      |
+Overflow Set        |BVS  |      |29 4 2|      |      |      |V=1       |      |
+Plus                |BPL  |      |2A 4 2|      |      |      |N=0       |      |
 */
 
 static void Op20(void)                                                 // BRA
@@ -1769,11 +1760,11 @@ static void Op2A(void)                                                  // BPL
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Branch to Subroutine    |BSR  |      |8D 8 2|      |      |      |          |      |
-Jump                    |JMP  |      |      |6E 4 2|7E 3 3|      |          |      |
-Jump to Subroutine      |JSR  |      |      |AD 8 2|BD 9 3|      |          |      |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Branch to Subroutine|BSR  |      |8D 8 2|      |      |      |          |      |
+Jump                |JMP  |      |      |6E 4 2|7E 3 3|      |          |      |
+Jump to Subroutine  |JSR  |      |      |AD 8 2|BD 9 3|      |          |      |
 */
 
 static void Op8D(void)                                                 // BSR
@@ -1785,7 +1776,8 @@ static void Op8D(void)                                                    // BSR
 
 static void Op6E(void)                                                 // JMP ZP, X
 {
-       regs.pc = EA_ZP_X;
+       uint16_t m = EA_ZP_X;
+       regs.pc = m;
 }
 
 static void Op7E(void)                                                 // JMP ABS
@@ -1808,13 +1800,13 @@ static void OpBD(void)                                                  // JSR ABS
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-No Operation            |NOP  |      |      |      |      |01 2 1|          |      |
-Return from Interrupt   |RTI  |      |      |      |      |3B A 1|          |AAAAAA|
-Return from Subroutine  |RTS  |      |      |      |      |39 5 1|          |      |
-Software Interrupt      |SWI  |      |      |      |      |3F C 1|          | S    |
-Wait For Interrupt      |WAI  |      |      |      |      |3E 9 1|          | B    |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+No Operation        |NOP  |      |      |      |      |01 2 1|          |      |
+Return from Interrpt|RTI  |      |      |      |      |3B A 1|          |AAAAAA|
+Return from Subrtine|RTS  |      |      |      |      |39 5 1|          |      |
+Software Interrupt  |SWI  |      |      |      |      |3F C 1|          | S    |
+Wait For Interrupt  |WAI  |      |      |      |      |3E 9 1|          | B    |
 */
 
 static void Op01(void)                                                 // NOP
@@ -1864,16 +1856,16 @@ WriteLog("*** WAI STATE ASSERTED ***\n");
 }
 
 /*
-Operation               |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
-                        |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
-Clear Carry             |CLC  |      |      |      |      |0C 2 1|C=0       |     R|
-Clear Interrupt         |CLI  |      |      |      |      |0E 2 1|I=0       | R    |
-Clear Overflow          |CLV  |      |      |      |      |0A 2 1|V=0       |    R |
-Set Carry               |SEC  |      |      |      |      |0D 2 1|C=1       |     S|
-Set Interrupt           |SEI  |      |      |      |      |0F 2 1|I=1       | S    |
-Set Overflow            |SEV  |      |      |      |      |0B 2 1|V=1       |    S |
-CCR=Accumulator A       |TAP  |      |      |      |      |06 2 1|CCR=A     |CCCCCC|
-Accumlator A=CCR        |TPA  |      |      |      |      |07 2 1|A=CCR     |      |
+Operation           |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg|
+                    |     |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #|          |HINZVC|
+Clear Carry         |CLC  |      |      |      |      |0C 2 1|C=0       |     R|
+Clear Interrupt     |CLI  |      |      |      |      |0E 2 1|I=0       | R    |
+Clear Overflow      |CLV  |      |      |      |      |0A 2 1|V=0       |    R |
+Set Carry           |SEC  |      |      |      |      |0D 2 1|C=1       |     S|
+Set Interrupt       |SEI  |      |      |      |      |0F 2 1|I=1       | S    |
+Set Overflow        |SEV  |      |      |      |      |0B 2 1|V=1       |    S |
+CCR=Accumulator A   |TAP  |      |      |      |      |06 2 1|CCR=A     |CCCCCC|
+Accumlator A=CCR    |TPA  |      |      |      |      |07 2 1|A=CCR     |      |
 */
 
 static void Op0C(void)                                                 // CLC
@@ -1978,7 +1970,6 @@ static void Op__(void)
        regs.cpuFlags |= V6808_STATE_ILLEGAL_INST;
 }
 
-
 //
 // Ok, the exec_op[] array is globally defined here basically to save
 // a LOT of unnecessary typing.  Sure it's ugly, but hey, it works!
@@ -2002,7 +1993,6 @@ void (* exec_op[256])() = {
        OpF0, OpF1, OpF2, Op__, OpF4, OpF5, OpF6, OpF7, OpF8, OpF9, OpFA, OpFB, Op__, Op__, OpFE, OpFF
 };
 
-
 //
 // Internal "memcpy" (so we don't have to link with any external libraries!)
 //
@@ -2014,10 +2004,6 @@ static void myMemcpy(void * dst, void * src, uint32_t size)
                d[i] = s[i];
 }
 
-#ifdef __DEBUG__
-//int instCount[256];
-static bool logGo = false;
-#endif
 //
 // Function to execute 6808 for "cycles" cycles
 //
@@ -2025,91 +2011,61 @@ void Execute6808(V6808REGS * context, uint32_t cycles)
 {
 #warning "V6808_STATE_WAI is not properly handled yet! !!! FIX !!!"
 #warning "Need to convert from destructive clock to non-destructive. !!! FIX !!!"
-
        myMemcpy(&regs, context, sizeof(V6808REGS));
-       UNPACK_FLAGS;                                                           // Explode flags register into individual uint8_ts
+       UNPACK_FLAGS;                                           // Explode flags register into individual uint8_ts
 
        // Execute here...
        while (regs.clock < cycles)
        {
-#ifdef __DEBUG__
-if (logGo)
-       Decode6808(regs.pc);
-#endif
                uint8_t opcode = regs.RdMem(regs.pc++);
-
-#ifdef __DEBUG__
-//if (!(regs.cpuFlags & V6808_STATE_ILLEGAL_INST))
-//instCount[opcode]++;
-#endif
-
-               exec_op[opcode]();                                              // Execute that opcode...
+               exec_op[opcode]();                              // Execute that opcode...
                regs.clock += CPUCycles[opcode];
-#ifdef __DEBUG__
-if (logGo)
-//     WriteLog(" [PC=%04X, S=%04X, X=%04X, A=%02X, B=%02X, CC=%s%s%s%s%s%s%s%s]\n", regs.pc, regs.s, regs.x, regs.a, regs.b, (regs.cc & FLAG_E ? "E" : " "), (regs.cc & FLAG_F ? "F" : " "), (regs.cc & FLAG_H ? "H" : " "), (regs.cc & FLAG_I ? "I" : " "), (regs.cc & FLAG_N ? "N" : " "), (regs.cc & FLAG_Z ? "Z" : " "), (regs.cc & FLAG_V ? "V" : " "), (regs.cc & FLAG_C ? "C" : " "));
-       WriteLog(" [PC=%04X, S=%04X, X=%04X, A=%02X, B=%02X, CC=%s%s%s%s%s%s%s%s]\n", regs.pc, regs.s, regs.x, regs.a, regs.b, (regs.cc & FLAG_E ? "E" : " "), (regs.cc & FLAG_F ? "F" : " "), (flagH ? "H" : " "), (flagI ? "I" : " "), (flagN ? "N" : " "), (flagZ ? "Z" : " "), (flagV ? "V" : " "), (flagC ? "C" : " "));
-#endif
 
-               if (regs.cpuFlags & V6808_ASSERT_LINE_RESET)
+               if (regs.cpuFlags & V6808_LINE_RESET)
                {
-#ifdef __DEBUG__
-WriteLog("*** RESET LINE ASSERTED ***\n");
-#endif
-                       flagI = 1;                                                      // Set I
-                       regs.pc = RdMemW(0xFFFE);                       // And load PC with the RESET vector
+                       flagI = 1;                                      // Set I
+                       regs.pc = RdMemW(0xFFFE);       // And load PC with the RESET vector
 
-                       context->cpuFlags &= ~V6808_ASSERT_LINE_RESET;
-                       regs.cpuFlags &= ~V6808_ASSERT_LINE_RESET;
+                       context->cpuFlags &= ~V6808_LINE_RESET;
+                       regs.cpuFlags &= ~V6808_LINE_RESET;
                }
-               else if (regs.cpuFlags & V6808_ASSERT_LINE_NMI)
+               else if (regs.cpuFlags & V6808_LINE_NMI)
                {
-#ifdef __DEBUG__
-WriteLog("*** NMI LINE ASSERTED ***\n");
-#endif
-                       regs.cc = PACK_FLAGS;                           // Mash flags back into the CC register
-                       PUSH16(regs.pc);                                        // Save all regs...
+                       regs.cc = PACK_FLAGS;           // Mash flags back into the CC register
+                       PUSH16(regs.pc);                        // Save all regs...
                        PUSH16(regs.x);
                        PUSH(regs.b);
                        PUSH(regs.a);
                        PUSH(regs.cc);
-                       regs.pc = RdMemW(0xFFFC);                       // And do it!
+                       regs.pc = RdMemW(0xFFFC);       // And do it!
 
 #warning "# of clock cycles for NMI unknown. !!! FIX !!!"
                        regs.clock += 0;                                                        // How many???
-                       context->cpuFlags &= ~V6808_ASSERT_LINE_NMI;// Reset the asserted line (NMI)...
-                       regs.cpuFlags &= ~V6808_ASSERT_LINE_NMI;        // Reset the asserted line (NMI)...
+                       context->cpuFlags &= ~V6808_LINE_NMI;// Reset the asserted line (NMI)...
+                       regs.cpuFlags &= ~V6808_LINE_NMI;       // Reset the asserted line (NMI)...
                }
-               else if (regs.cpuFlags & V6808_ASSERT_LINE_IRQ)
+               else if (regs.cpuFlags & V6808_LINE_IRQ)
                {
-#ifdef __DEBUG__
-WriteLog("*** IRQ LINE ASSERTED ***\n");
-#endif
-//                     if (!(regs.cc & FLAG_I))                        // Process an interrupt (I=0)?
-                       if (!flagI)                                                     // Process an interrupt (I=0)?
+                       if (!flagI)                                     // Process an interrupt (I=0)?
                        {
-#ifdef __DEBUG__
-WriteLog("    IRQ TAKEN!\n");
-logGo = true;
-#endif
-                               regs.cc = PACK_FLAGS;                   // Mash flags back into the CC register
-                               PUSH16(regs.pc);                                // Save all regs...
+                               regs.cc = PACK_FLAGS;   // Mash flags back into the CC register
+                               PUSH16(regs.pc);                // Save all regs...
                                PUSH16(regs.x);
                                PUSH(regs.b);
                                PUSH(regs.a);
                                PUSH(regs.cc);
-                               regs.pc = RdMemW(0xFFF8);               // And do it!
+                               regs.pc = RdMemW(0xFFF8);// And do it!
 
 #warning "# of clock cycles for IRQ unknown. !!! FIX !!!"
                                regs.clock += 0;                                // How many???
 #warning "IRQ/NMI lines should not be cleared here... !!! FIX !!!"
-                               context->cpuFlags &= ~V6808_ASSERT_LINE_IRQ;    // Reset the asserted line (IRQ)...
-                               regs.cpuFlags &= ~V6808_ASSERT_LINE_IRQ;        // Reset the asserted line (IRQ)...
+                               context->cpuFlags &= ~V6808_LINE_IRQ;   // Reset the asserted line (IRQ)...
+                               regs.cpuFlags &= ~V6808_LINE_IRQ;       // Reset the asserted line (IRQ)...
                        }
                }
        }
 
-       regs.cc = PACK_FLAGS;                                           // Mash flags back into the CC register
+       regs.cc = PACK_FLAGS;                           // Mash flags back into the CC register
        myMemcpy(context, &regs, sizeof(V6808REGS));
 }