From 4ca28ba07da9f3848c2e3db0e2e9cbcaa787dd29 Mon Sep 17 00:00:00 2001 From: Shamus Hammons Date: Wed, 29 Nov 2017 18:52:47 -0600 Subject: [PATCH] Small cleanups + version bump for last commit. Version now at 1.10.2. --- 68ktab | 46 +++++++++---------- expr.c | 5 ++ mach.c | 135 +++++++++++++++++++++++++----------------------------- rmac.c | 24 +++++----- rmac.h | 3 +- token.c | 3 +- version.h | 2 +- 7 files changed, 108 insertions(+), 110 deletions(-) diff --git a/68ktab b/68ktab index a572a3f..a8eca59 100644 --- a/68ktab +++ b/68ktab @@ -280,11 +280,11 @@ facos NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_facos + - NX M_FREG M_FREG %1111001000eeeeee m_facos + - NX M_FREG M_AM_NONE %1111001000eeeeee m_facos fadd NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fadd + -- NX M_FREG M_FREG %1111001000eeeeee m_fadd +- NX M_FREG M_FREG %1111001000eeeeee m_fadd fsadd NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsadd + -- NX M_FREG M_FREG %1111001000eeeeee m_fsadd +- NX M_FREG M_FREG %1111001000eeeeee m_fsadd fdadd NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdadd + -- NX M_FREG M_FREG %1111001000eeeeee m_fdadd +- NX M_FREG M_FREG %1111001000eeeeee m_fdadd fasin NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fasin + - NX M_FREG M_FREG %1111001000eeeeee m_fasin + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fasin @@ -333,12 +333,12 @@ fbseq NWL C_LABEL M_AM_NONE %111100101s010001 m_cpbr fbsne NWL C_LABEL M_AM_NONE %111100101s011110 m_cpbr fcmp NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fcmp + -- NX M_FREG M_FREG %1111001000eeeeee m_fcmp +- NX M_FREG M_FREG %1111001000eeeeee m_fcmp fcos NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fcos + - NX M_FREG M_FREG %1111001000eeeeee m_fcos + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fcos fcosh NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fcosh + -- NX M_FREG M_FREG %1111001000eeeeee m_fcosh + +- NX M_FREG M_FREG %1111001000eeeeee m_fcosh + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fcosh fdbeq N M_DREG C_LABEL %1111001001000001 m_fdbcc @@ -430,11 +430,11 @@ fdmove NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdmove fmovecr NX M_IMMED M_FREG %1111001000000000 m_fmovecr fmovem ! M_AM_NONE M_AM_NONE %1111001000eeeeee m_fmovem fmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fmul +- NX M_FREG M_FREG %1111001000eeeeee m_fmul fsmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fsmul +- NX M_FREG M_FREG %1111001000eeeeee m_fsmul fdmul NX C_ALL030 M_FREG %1111001000eeeeee m_fdmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fdmul +- NX M_FREG M_FREG %1111001000eeeeee m_fdmul fneg NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fneg + - NX M_FREG M_FREG %1111001000eeeeee m_fneg + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fneg @@ -448,11 +448,11 @@ fnop N M_AM_NONE M_AM_NONE %1111001010000000 m_fnop frem NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_frem + - NX M_FREG M_FREG %1111001000eeeeee m_frem fscale NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fscale + -- NX M_FREG M_FREG %1111001000eeeeee m_fscale +- NX M_FREG M_FREG %1111001000eeeeee m_fscale fseq NB C_ALL030 M_AM_NONE %1111001001e00001 m_fscc fsze -fsz +fsz fsne NB C_ALL030 M_AM_NONE %1111001001e01110 m_fscc fsgt NB C_ALL030 M_AM_NONE %1111001001e10010 m_fscc fsngt NB C_ALL030 M_AM_NONE %1111001001e11101 m_fscc @@ -486,14 +486,14 @@ fsseq NB C_ALL030 M_AM_NONE %1111001001e10001 m_fscc fssne NB C_ALL030 M_AM_NONE %1111001001e11110 m_fscc fsgldiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsgldiv + -- NX M_FREG M_FREG %1111001000eeeeee m_fsgldiv +- NX M_FREG M_FREG %1111001000eeeeee m_fsgldiv fsglmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsglmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fsglmul +- NX M_FREG M_FREG %1111001000eeeeee m_fsglmul fsin NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsin + - NX M_FREG M_FREG %1111001000eeeeee m_fsin + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fsin fsincos NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsincos + -- NX M_FREG M_FREG %1111001000eeeeee m_fsincos +- NX M_FREG M_FREG %1111001000eeeeee m_fsincos fsinh NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsinh + - NX M_FREG M_FREG %1111001000eeeeee m_fsinh + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fsinh @@ -507,11 +507,11 @@ fdsqrt NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdfsqrt + - NX M_FREG M_FREG %1111001000eeeeee m_fdfsqrt + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fdfsqrt fsub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsub + -- NX M_FREG M_FREG %1111001000eeeeee m_fsub +- NX M_FREG M_FREG %1111001000eeeeee m_fsub fssub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsub + -- NX M_FREG M_FREG %1111001000eeeeee m_fsub +- NX M_FREG M_FREG %1111001000eeeeee m_fsub fdsub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdsub + -- NX M_FREG M_FREG %1111001000eeeeee m_fdsub +- NX M_FREG M_FREG %1111001000eeeeee m_fdsub ftan NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftan + - NX M_FREG M_FREG %1111001000eeeeee m_ftan + - NX M_FREG M_AM_NONE %1111001000eeeeee m_ftan @@ -605,10 +605,10 @@ movec NL M_DREG+M_AREG C_CREG %0100111001111011 m_movec + - NL C_CREG M_DREG+M_AREG %0100111001111010 m_movec moves NBWL M_DREG+M_AREG C_MOVES %00001110sseeeeee m_moves + -- NBWL C_MOVES M_DREG+M_AREG %00001110sseeeeee m_moves +- NBWL C_MOVES M_DREG+M_AREG %00001110sseeeeee m_moves move16 N APOSTINC APOSTINC %1111011000100rrr m_move16a + -- N AIND+APOSTINC+ABSL AIND+APOSTINC+ABSL %11110110000ooorrr m_move16b +- N AIND+APOSTINC+ABSL AIND+APOSTINC+ABSL %11110110000ooorrr m_move16b movem ! M_AM_NONE M_AM_NONE %01001d001seeeeee m_movem @@ -618,7 +618,7 @@ movep NWL M_DREG M_AIND|M_ADISP %0000rrr11s001aaa m_movep + moveq NL M_IMMED M_DREG %0111rrr0dddddddd m_moveq muls NW C_DATA M_DREG %1100rrr111eR1000 m_ea + -- L C_DATA030 M_DREG %0100110000eeeeee m_muls +- L C_DATA030 M_DREG %0100110000eeeeee m_muls mulu NW C_DATA M_DREG %1100rrr011eR1000 m_ea + - L C_DATA030 M_DREG %0100110000eeeeee m_mulu @@ -677,7 +677,7 @@ pflusha N M_AM_NONE M_AM_NONE %1111000000000000 m_pflusha pflushr N C_ALL030 M_AM_NONE %1111000000eeeeee m_pflushr ploadr N M_FC C_PMOVE %1111000000eeeeee m_ploadr -ploadw N M_FC C_PMOVE %1111000000eeeeee m_ploadw +ploadw N M_FC C_PMOVE %1111000000eeeeee m_ploadw pmove NWLD M_MRN C_PMOVE %1111000000eeeeee m_pmove + - NWLD C_PMOVE M_MRN %1111000000eeeeee m_pmove @@ -796,10 +796,10 @@ trapcc NWL M_IMMED M_AM_NONE %0101010011111ooo m_trapcc + - NWL M_AM_NONE M_AM_NONE %0101010011111100 m_self trapcs NWL M_IMMED M_AM_NONE %0101010111111ooo m_trapcc + - NWL M_AM_NONE M_AM_NONE %0101010111111100 m_self -traplo +traplo trapeq NWL M_IMMED M_AM_NONE %0101011111111ooo m_trapcc + - NWL M_AM_NONE M_AM_NONE %0101011111111100 m_self -trapze +trapze trapf NWL M_IMMED M_AM_NONE %0101000111111ooo m_trapcc + - NWL M_AM_NONE M_AM_NONE %0101000111111100 m_self trapge NWL M_IMMED M_AM_NONE %0101110011111ooo m_trapcc + @@ -818,7 +818,7 @@ trapmi NWL M_IMMED M_AM_NONE %0101101111111ooo m_trapcc + - NWL M_AM_NONE M_AM_NONE %0101101111111100 m_self trapne NWL M_IMMED M_AM_NONE %0101011011111ooo m_trapcc + - NWL M_AM_NONE M_AM_NONE %0101011011111100 m_self -trapnz +trapnz trappl NWL M_IMMED M_AM_NONE %0101101011111ooo m_trapcc + - NWL M_AM_NONE M_AM_NONE %0101101011111100 m_self trapt NWL M_IMMED M_AM_NONE %0101000011111ooo m_trapcc + diff --git a/expr.c b/expr.c index 20f43cf..5474af8 100644 --- a/expr.c +++ b/expr.c @@ -230,6 +230,11 @@ int expr2(void) switch (*tok++) { case CONST: + ptk.u32 = tok; + *evalTokenBuffer.u32++ = CONST; + *evalTokenBuffer.u64++ = *ptk.u64++; + tok = ptk.u32; + break; case FCONST: ptk.u32 = tok; *evalTokenBuffer.u32++ = CONST; diff --git a/mach.c b/mach.c index 2db0db3..15f818f 100644 --- a/mach.c +++ b/mach.c @@ -168,9 +168,9 @@ char unsupport[] = "unsupported for selected CPU"; // Include code tables MNTAB machtab[] = { - { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 - #include "68ktab.h" - { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry + { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 +#include "68ktab.h" + { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry }; // Register number << 9 @@ -208,10 +208,10 @@ WORD lwsiz_8[] = { // Byte/Word/long size (0=.w, 1=.l) in bit 9 WORD lwsiz_9[] = { (WORD)-1, - 0, // Byte - 1<<9, (WORD)-1, // Word - 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long - 1<<9 // Word (SIZN) + 0, // Byte + 1<<9, (WORD)-1, // Word + 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long + 1<<9 // Word (SIZN) }; // Addressing mode in bits 6..11 (register/mode fields are reversed) @@ -739,6 +739,7 @@ int m_move(WORD inst, WORD size) return OK; } + // // Handle MOVE // MOVE @@ -1093,18 +1094,13 @@ int m_clra(WORD inst, WORD siz) int m_clrd(WORD inst, WORD siz) { if (!CHECK_OPTS(OPT_CLR_DX)) - { inst |= a0reg; - D_word(inst); - - return OK; - } else - { inst = (a0reg << 9) | B16(01110000, 00000000); - D_word(inst); - return OK; - } + + D_word(inst); + + return OK; } @@ -1892,6 +1888,7 @@ int m_divsl(WORD inst, WORD siz) return OK; } + // // divul.l // @@ -2489,6 +2486,7 @@ int m_pflush(WORD inst, WORD siz) return OK; } + // // pflushr (68851) // @@ -2547,12 +2545,11 @@ int m_pflushr(WORD inst, WORD siz) int m_pload(WORD inst, WORD siz, WORD extension) { // TODO: 68851 support is not added yet. - // None of the ST series of computers had a 68020 + 68551 socket and since + // None of the ST series of computers had a 68020 + 68851 socket and since // this is an Atari targetted assembler... CHECKNO30; inst |= am1; - D_word(inst); switch (am0) @@ -2585,16 +2582,19 @@ int m_pload(WORD inst, WORD siz, WORD extension) return OK; } + int m_ploadr(WORD inst, WORD siz) { return m_pload(inst, siz, 1 << 9); } + int m_ploadw(WORD inst, WORD siz) { return m_pload(inst, siz, 0 << 9); } + // // pmove (68030/68851) // @@ -2602,15 +2602,13 @@ int m_pmove(WORD inst, WORD siz) { int inst2,reg; - // TODO: 68851 support is not added yet. - // None of the ST series of computers had - // a 68020 + 68851 socket and since this is - // an Atari targetted assembler.... - // (same for 68EC030) + // TODO: 68851 support is not added yet. None of the ST series of + // computers had a 68020 + 68851 socket and since this is an Atari + // targetted assembler.... (same for 68EC030) CHECKNO30; - inst2 = inst & (1 << 8); //Copy the flush bit over to inst2 in case we're called from m_pmovefd - inst &= ~(1 << 8); //And mask it out + inst2 = inst & (1 << 8); // Copy the flush bit over to inst2 in case we're called from m_pmovefd + inst &= ~(1 << 8); // And mask it out if (am0 == CREG) { @@ -2642,7 +2640,6 @@ int m_pmove(WORD inst, WORD siz) if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN))) return error(siz_error); - if (am0 == CREG) { inst |= am1 | a1reg; @@ -2698,17 +2695,15 @@ int m_pmovefd(WORD inst, WORD siz) return m_pmove(inst | (1 << 8), siz); } + // // ptrapcc (68851) // int m_ptrapcc(WORD inst, WORD siz) { CHECKNO20; - // We stash the 5 condition bits - // inside the opcode in 68ktab - // (bits 0-4), so we need to extract - // them first and fill in - // the clobbered bits. + // We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4), + // so we need to extract them first and fill in the clobbered bits. WORD opcode = inst & 0x1F; inst = (inst & 0xFFE0) | (0x18); @@ -2732,6 +2727,7 @@ int m_ptrapcc(WORD inst, WORD siz) D_word(inst); D_word(opcode); } + return OK; } @@ -2831,8 +2827,8 @@ int m_fsabs(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01011000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2840,8 +2836,8 @@ int m_fdabs(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01011100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2867,8 +2863,8 @@ int m_fsadd(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100010), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2876,8 +2872,8 @@ int m_fdadd(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100110), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2985,8 +2981,8 @@ int m_fsdiv(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2994,8 +2990,8 @@ int m_fddiv(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3111,7 +3107,6 @@ int m_fmod(WORD inst, WORD siz) // int m_fmove(WORD inst, WORD siz) { - // EA to register if ((am0 == FREG) && (am1 < AM_USP)) { @@ -3136,7 +3131,6 @@ int m_fmove(WORD inst, WORD siz) case SIZP: inst |= (3 << 10); // In P size we have 2 cases: {#k} where k is immediate // and {Dn} where Dn=Data register - if (bfparam1) { // Dn @@ -3158,7 +3152,6 @@ int m_fmove(WORD inst, WORD siz) break; } - // Destination specifier inst |= (a0reg << 7); @@ -3261,8 +3254,8 @@ int m_fmovescr(WORD inst, WORD siz) ea0gen(siz); return OK; } - else - return error("m_fmovescr says: wut?"); + + return error("m_fmovescr says: wut?"); } // @@ -3320,7 +3313,7 @@ int m_fmovem(WORD inst, WORD siz) WORD regmask; WORD datareg; - if (siz == SIZX || siz==SIZN) + if (siz == SIZX || siz == SIZN) { if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) { @@ -3553,8 +3546,8 @@ int m_fdneg(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01011110), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3592,11 +3585,8 @@ int m_fscale(WORD inst, WORD siz) // int m_fscc(WORD inst, WORD siz) { - // We stash the 5 condition bits - // inside the opcode in 68ktab - // (bits 4-0), so we need to extract - // them first and fill in - // the clobbered bits. + // We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0), + // so we need to extract them first and fill in the clobbered bits. WORD opcode = inst & 0x1F; inst &= 0xFFE0; inst |= am0 | a0reg; @@ -3606,19 +3596,17 @@ int m_fscc(WORD inst, WORD siz) return OK; } + // // FTRAPcc (6888X, 68040) // - int m_ftrapcc(WORD inst, WORD siz) { - // We stash the 5 condition bits - // inside the opcode in 68ktab - // (bits 3-7), so we need to extract - // them first and fill in - // the clobbered bits. + // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7), + // so we need to extract them first and fill in the clobbered bits. WORD opcode = (inst >> 3) & 0x1F; inst = (inst & 0xFF07) | (0xF << 3); + if (siz == SIZW) { inst |= 2; @@ -3640,9 +3628,11 @@ int m_ftrapcc(WORD inst, WORD siz) D_word(opcode); return OK; } + return OK; } + // // fsgldiv (6888X, 68040) // @@ -3675,19 +3665,20 @@ int m_fsin(WORD inst, WORD siz) // int m_fsincos(WORD inst, WORD siz) { - // Swap a1reg, a2reg as a2reg should be stored - // in the bitfield gen_fpu generates + // Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu + // generates int temp; temp = a2reg; a2reg = a1reg; a1reg = temp; + if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK) { chptr[-1] |= a2reg; return OK; } - else - return ERROR; + + return ERROR; } @@ -3722,8 +3713,8 @@ int m_fdfsqrt(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01000101), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3740,8 +3731,8 @@ int m_fsfsub(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01101000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3749,8 +3740,8 @@ int m_fdsub(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01101100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } diff --git a/rmac.c b/rmac.c index 2e6baf3..a4b6b42 100644 --- a/rmac.c +++ b/rmac.c @@ -378,31 +378,31 @@ int Process(int argc, char ** argv) break; case 'm': case 'M': - if ((*(argv[argno] + 2) == '6') && (*(argv[argno] + 3) == '8') && (*(argv[argno] + 4) == '0') && (*(argv[argno] + 5) == '0') && (*(argv[argno] + 6) == '0')) + if (strcmp(argv[argno] + 2, "68000") == 0) d_68000(); - else if ((*(argv[argno] + 2) == '6')&&(*(argv[argno] + 3) == '8')&&(*(argv[argno] + 4) == '0')&&(*(argv[argno] + 5) == '2')&&(*(argv[argno] + 6) == '0')) + else if (strcmp(argv[argno] + 2, "68020") == 0) d_68020(); - else if ((*(argv[argno] + 2) == '6')&&(*(argv[argno] + 3) == '8')&&(*(argv[argno] + 4) == '0')&&(*(argv[argno] + 5) == '3')&&(*(argv[argno] + 6) == '0')) + else if (strcmp(argv[argno] + 2, "68030") == 0) d_68030(); - else if ((*(argv[argno] + 2) == '6')&&(*(argv[argno] + 3) == '8')&&(*(argv[argno] + 4) == '0')&&(*(argv[argno] + 5) == '4')&&(*(argv[argno] + 6) == '0')) + else if (strcmp(argv[argno] + 2, "68040") == 0) d_68040(); - else if ((*(argv[argno] + 2) == '6')&&(*(argv[argno] + 3) == '8')&&(*(argv[argno] + 4) == '0')&&(*(argv[argno] + 5) == '6')&&(*(argv[argno] + 6) == '0')) + else if (strcmp(argv[argno] + 2, "68060") == 0) d_68060(); - else if ((*(argv[argno] + 2) == '6')&&(*(argv[argno] + 3) == '8')&&(*(argv[argno] + 4) == '8')&&(*(argv[argno] + 5) == '8')&&(*(argv[argno] + 6) == '1')) + else if (strcmp(argv[argno] + 2, "68881") == 0) d_68881(); - else if ((*(argv[argno] + 2) == '6')&&(*(argv[argno] + 3) == '8')&&(*(argv[argno] + 4) == '8')&&(*(argv[argno] + 5) == '8')&&(*(argv[argno] + 6) == '2')) + else if (strcmp(argv[argno] + 2, "68882") == 0) d_68882(); - else if ((*(argv[argno] + 2) == '5')&&(*(argv[argno] + 3) == '6')&&(*(argv[argno] + 4) == '0')&&(*(argv[argno] + 5) == '0')&&(*(argv[argno] + 6) == '1')) + else if (strcmp(argv[argno] + 2, "56001") == 0) d_56001(); - else if ((*(argv[argno] + 2) == '6')&&(*(argv[argno] + 3) == '5')&&(*(argv[argno] + 4) == '0')&&(*(argv[argno] + 5) == '2')) + else if (strcmp(argv[argno] + 2, "6502") == 0) d_6502(); - else if ((*(argv[argno] + 2) == 't')&&(*(argv[argno] + 3) == 'o')&&(*(argv[argno] + 4) == 'm')) + else if (strcmp(argv[argno] + 2, "tom") == 0) d_gpu(); - else if ((*(argv[argno] + 2) == 'j')&&(*(argv[argno] + 3) == 'e')&&(*(argv[argno] + 4) == 'r')&&(*(argv[argno] + 5) == 'r')&&(*(argv[argno] + 6) == 'y')) + else if (strcmp(argv[argno] + 2, "jerry") == 0) d_dsp(); else { - printf("Unrecognised CPU"); + printf("Unrecognized CPU '%s'\n", argv[argno] + 2); errcnt++; return errcnt; } diff --git a/rmac.h b/rmac.h index 8e4e295..61c7618 100644 --- a/rmac.h +++ b/rmac.h @@ -135,7 +135,7 @@ // Byteswap crap #define BYTESWAP16(x) ((((x) & 0x00FF) << 8) | (((x) & 0xFF00) >> 8)) #define BYTESWAP32(x) ((((x) & 0x000000FF) << 24) | (((x) & 0x0000FF00) << 8) | (((x) & 0x00FF0000) >> 8) | (((x) & 0xFF000000) >> 24)) -#define BYTESWAP64(x) ((BYTESWAP32(x >> 32) | (BYTESWAP32(x & 0xFFFFFFFF) << 32))) +#define BYTESWAP64(x) (BYTESWAP32(x >> 32) | (BYTESWAP32(x & 0xFFFFFFFF) << 32)) #define WORDSWAP32(x) ((((x) & 0x0000FFFF) << 16) | (((x) & 0xFFFF0000) >> 16)) // @@ -189,6 +189,7 @@ PTR uint32_t lw; // LONG (for some reason) SYM ** sy; // SYM pointer TOKEN * tk; // TOKEN pointer + double * dp; // Double pointer (temporary!) }; // Symbol spaces diff --git a/token.c b/token.c index 9754f4e..34c4a52 100644 --- a/token.c +++ b/token.c @@ -1624,7 +1624,8 @@ dostring: *tk.u32++ = FCONST; // Shamus: Well, this is all kinds of icky--not the least of which is that unlike uintNN_t types, we have no guarantees of any kind when it comes to the size of floating point numbers in C (as far as I know of). If there is, we need to use those kinds here, or else figure out at runtime what sizes we're dealing with and act accordingly. To be fair, this is OK as long as the double type is less than 64 bits wide, but again, there's no guarantee that it isn't. :-/ - *tk.u64++ = f; + *tk.dp = f; + tk.u64++; continue; } } diff --git a/version.h b/version.h index 067302f..edc8d0c 100644 --- a/version.h +++ b/version.h @@ -15,7 +15,7 @@ #define MAJOR 1 // Major version number #define MINOR 10 // Minor version number -#define PATCH 1 // Patch release number +#define PATCH 2 // Patch release number #endif // __VERSION_H__ -- 2.37.2