From 0c583009c5819e1774b24ef3cb59dde468fd3f60 Mon Sep 17 00:00:00 2001 From: ggn Date: Tue, 23 Jan 2018 13:01:23 +0200 Subject: [PATCH] FPU instructions debugged and stricter checks enforced --- 68ktab | 170 ++++++++++---------- amode.h | 1 + mach.c | 492 +++++++++++++++++++++++++++++++++++++++----------------- sect.h | 3 +- 4 files changed, 429 insertions(+), 237 deletions(-) diff --git a/68ktab b/68ktab index 017d044..1c03cff 100644 --- a/68ktab +++ b/68ktab @@ -376,17 +376,17 @@ fdbst N M_DREG C_LABEL %1111001001011111 m_fdbcc fdbseq N M_DREG C_LABEL %1111001001010001 m_fdbcc fdbsne N M_DREG C_LABEL %1111001001011110 m_fdbcc -fdiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdiv + -- NX M_FREG M_FREG %1111001000eeeeee m_fdiv + +fdiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdiv + +- NX M_FREG M_FREG %1111001000eeeeee m_fdiv + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fdiv -fsdiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsdiv + -- NX M_FREG M_FREG %1111001000eeeeee m_fsdiv + +fsdiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsdiv + +- NX M_FREG M_FREG %1111001000eeeeee m_fsdiv + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fsdiv -fddiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fddiv + -- NX M_FREG M_FREG %1111001000eeeeee m_fddiv + +fddiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fddiv + +- NX M_FREG M_FREG %1111001000eeeeee m_fddiv + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fddiv -fetox NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fetox + -- NX M_FREG M_FREG %1111001000eeeeee m_fetox + +fetox NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fetox + +- NX M_FREG M_FREG %1111001000eeeeee m_fetox + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fetox fetoxm1 NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fetoxm1 + - NX M_FREG M_FREG %1111001000eeeeee m_fetoxm1 + @@ -397,56 +397,56 @@ fgetexp NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fgetexp + fgetman NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fgetman + - NX M_FREG M_FREG %1111001000eeeeee m_fgetman + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fgetman -fint NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fint + -- NX M_FREG M_FREG %1111001000eeeeee m_fint + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_fint -fintrz NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fintrz + -- NX M_FREG M_FREG %1111001000eeeeee m_fintrz + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_fintrz -flog10 NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flog10 + -- NX M_FREG M_FREG %1111001000eeeeee m_flog10 + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_flog10 -flog2 NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flog2 + -- NX M_FREG M_FREG %1111001000eeeeee m_flog2 + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_flog2 -flogn NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flogn + -- NX M_FREG M_FREG %1111001000eeeeee m_flogn + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_flogn -flognp1 NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flognp1 + -- NX M_FREG M_FREG %1111001000eeeeee m_flognp1 + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_flognp1 -fmod NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fmod + -- NX M_FREG M_FREG %1111001000eeeeee m_fmod + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_fmod -fmove NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fmove + -- NBWLSDXP M_FREG C_ALL030 %1111001000eeeeee m_fmove + -- NX M_FREG M_FREG %1111001000eeeeee m_fmove + -- NL M_FPSCR C_ALL030 %1111001000eeeeee m_fmovescr + -- NL C_ALL030 M_FPSCR %1111001000eeeeee m_fmovescr + -fsmove NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsmove -fdmove NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdmove -fmovecr NX M_IMMED M_FREG %1111001000000000 m_fmovecr -fmovem ! M_AM_NONE M_AM_NONE %1111001000eeeeee m_fmovem -fmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fmul -fsmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fsmul -fdmul NX C_ALL030 M_FREG %1111001000eeeeee m_fdmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fdmul -fneg NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fneg + -- NX M_FREG M_FREG %1111001000eeeeee m_fneg + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_fneg -fsneg NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsneg + -- NX M_FREG M_FREG %1111001000eeeeee m_fsneg + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_fsneg -fdneg NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdneg + -- NX M_FREG M_FREG %1111001000eeeeee m_fdneg + -- NX M_FREG M_AM_NONE %1111001000eeeeee m_fdneg -fnop N M_AM_NONE M_AM_NONE %1111001010000000 m_fnop -frem NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_frem + -- NX M_FREG M_FREG %1111001000eeeeee m_frem -fscale NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fscale + -- NX M_FREG M_FREG %1111001000eeeeee m_fscale +fint NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fint + +- NX M_FREG M_FREG %1111001000eeeeee m_fint + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_fint +fintrz NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fintrz + +- NX M_FREG M_FREG %1111001000eeeeee m_fintrz + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_fintrz +flog10 NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flog10 + +- NX M_FREG M_FREG %1111001000eeeeee m_flog10 + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_flog10 +flog2 NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flog2 + +- NX M_FREG M_FREG %1111001000eeeeee m_flog2 + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_flog2 +flogn NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flogn + +- NX M_FREG M_FREG %1111001000eeeeee m_flogn + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_flogn +flognp1 NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_flognp1 + +- NX M_FREG M_FREG %1111001000eeeeee m_flognp1 + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_flognp1 +fmod NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fmod + +- NX M_FREG M_FREG %1111001000eeeeee m_fmod + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_fmod +fmove NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fmove + +- NBWLSDXP M_FREG C_ALL030 %1111001000eeeeee m_fmove + +- NX M_FREG M_FREG %1111001000eeeeee m_fmove + +- NL M_FPSCR C_ALL030 %1111001000eeeeee m_fmovescr + +- NL C_ALL030 M_FPSCR %1111001000eeeeee m_fmovescr + +fsmove NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsmove +fdmove NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdmove +fmovecr NX M_IMMED M_FREG %1111001000000000 m_fmovecr +fmovem ! M_AM_NONE M_AM_NONE %1111001000eeeeee m_fmovem +fmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fmul + +- NX M_FREG M_FREG %1111001000eeeeee m_fmul +fsmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsmul + +- NX M_FREG M_FREG %1111001000eeeeee m_fsmul +fdmul NX C_ALL030 M_FREG %1111001000eeeeee m_fdmul + +- NX M_FREG M_FREG %1111001000eeeeee m_fdmul +fneg NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fneg + +- NX M_FREG M_FREG %1111001000eeeeee m_fneg + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_fneg +fsneg NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsneg + +- NX M_FREG M_FREG %1111001000eeeeee m_fsneg + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_fsneg +fdneg NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdneg + +- NX M_FREG M_FREG %1111001000eeeeee m_fdneg + +- NX M_FREG M_AM_NONE %1111001000eeeeee m_fdneg +fnop N M_AM_NONE M_AM_NONE %1111001010000000 m_fnop +frem NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_frem + +- NX M_FREG M_FREG %1111001000eeeeee m_frem +fscale NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fscale + +- NX M_FREG M_FREG %1111001000eeeeee m_fscale fseq NB C_ALL030 M_AM_NONE %1111001001e00001 m_fscc fsze @@ -483,46 +483,46 @@ fsst NB C_ALL030 M_AM_NONE %1111001001e11111 m_fscc fsseq NB C_ALL030 M_AM_NONE %1111001001e10001 m_fscc fssne NB C_ALL030 M_AM_NONE %1111001001e11110 m_fscc -fsgldiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsgldiv + -- NX M_FREG M_FREG %1111001000eeeeee m_fsgldiv -fsglmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsglmul + -- NX M_FREG M_FREG %1111001000eeeeee m_fsglmul -fsin NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsin + -- NX M_FREG M_FREG %1111001000eeeeee m_fsin + +fsgldiv NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsgldiv + +- NX M_FREG M_FREG %1111001000eeeeee m_fsgldiv +fsglmul NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsglmul + +- NX M_FREG M_FREG %1111001000eeeeee m_fsglmul +fsin NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsin + +- NX M_FREG M_FREG %1111001000eeeeee m_fsin + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fsin -fsincos NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsincos + +fsincos NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsincos + - NX M_FREG M_FREG %1111001000eeeeee m_fsincos -fsinh NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsinh + -- NX M_FREG M_FREG %1111001000eeeeee m_fsinh + +fsinh NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsinh + +- NX M_FREG M_FREG %1111001000eeeeee m_fsinh + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fsinh fsqrt NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsqrt + - NX M_FREG M_FREG %1111001000eeeeee m_fsqrt + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fsqrt -fssqrt NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsfsqrt + -- NX M_FREG M_FREG %1111001000eeeeee m_fsfsqrt + +fssqrt NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsfsqrt + +- NX M_FREG M_FREG %1111001000eeeeee m_fsfsqrt + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fsfsqrt -fdsqrt NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdfsqrt + -- NX M_FREG M_FREG %1111001000eeeeee m_fdfsqrt + +fdsqrt NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdfsqrt + +- NX M_FREG M_FREG %1111001000eeeeee m_fdfsqrt + - NX M_FREG M_AM_NONE %1111001000eeeeee m_fdfsqrt -fsub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsub + +fsub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsub + - NX M_FREG M_FREG %1111001000eeeeee m_fsub -fssub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsub + +fssub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fsub + - NX M_FREG M_FREG %1111001000eeeeee m_fsub -fdsub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdsub + +fdsub NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_fdsub + - NX M_FREG M_FREG %1111001000eeeeee m_fdsub -ftan NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftan + -- NX M_FREG M_FREG %1111001000eeeeee m_ftan + +ftan NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftan + +- NX M_FREG M_FREG %1111001000eeeeee m_ftan + - NX M_FREG M_AM_NONE %1111001000eeeeee m_ftan -ftanh NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftanh + -- NX M_FREG M_FREG %1111001000eeeeee m_ftanh + +ftanh NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftanh + +- NX M_FREG M_FREG %1111001000eeeeee m_ftanh + - NX M_FREG M_AM_NONE %1111001000eeeeee m_ftanh -ftentox NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftentox + -- NX M_FREG M_FREG %1111001000eeeeee m_ftentox + +ftentox NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftentox + +- NX M_FREG M_FREG %1111001000eeeeee m_ftentox + - NX M_FREG M_AM_NONE %1111001000eeeeee m_ftentox -ftst NBWLSDXP C_ALL030 M_AM_NONE %1111001000eeeeee m_ftst + +ftst NBWLSDXP C_ALL030 M_AM_NONE %1111001000eeeeee m_ftst + - NX M_FREG M_AM_NONE %1111001000eeeeee m_ftst -ftwotox NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftwotox + -- NX M_FREG M_FREG %1111001000eeeeee m_ftwotox + +ftwotox NBWLSDXP C_ALL030 M_FREG %1111001000eeeeee m_ftwotox + +- NX M_FREG M_FREG %1111001000eeeeee m_ftwotox + - NX M_FREG M_AM_NONE %1111001000eeeeee m_ftwotox ftrapeq WLN M_IMMED|M_AM_NONE M_AM_NONE %1111001000001mmm m_ftrapcc @@ -561,8 +561,8 @@ ftrapseq WLN M_IMMED|M_AM_NONE M_AM_NONE %1111001010001mmm m_ftrapcc ftrapsne WLN M_IMMED|M_AM_NONE M_AM_NONE %1111001011110mmm m_ftrapcc -frestore N C_DATA030 M_AM_NONE %1111001101eeeeee m_cprest -fsave N C_DATA030 M_AM_NONE %1111001100eeeeee m_cprest +frestore N C_DATA030 M_AM_NONE %1111001101eeeeee m_frestore +fsave N C_DATA030 M_AM_NONE %1111001100eeeeee m_frestore illegal N M_AM_NONE M_AM_NONE %0100101011111100 m_self diff --git a/amode.h b/amode.h index 3da2321..2272b9c 100644 --- a/amode.h +++ b/amode.h @@ -77,6 +77,7 @@ #define C_CTRL 0x000007E4L #define C_ALT 0x000001FFL #define C_ALL030 0x0003FFFFL +#define C_FPU030 0x0003FFECL /* (An), #, (An)+, (d16,An), (d16,PC), (d8, An, Xn), (d8, PC, Xn), (bd, An, Xn), An(bd, PC, Xn), ([bd, An, Xn], od), An([bd, PC, Xn], od), ([bd, An], Xn, od), An([bd, PC], Xn, od) */ #define C_CTRL030 0x0003F7E4L #define C_DATA030 0x0003FFFDL #define C_MOVES (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPRE | M_MEMPOST) diff --git a/mach.c b/mach.c index b49fcb7..162757f 100644 --- a/mach.c +++ b/mach.c @@ -87,7 +87,7 @@ int m_ptrapcc(WORD inst, WORD siz); int m_ploadr(WORD inst, WORD siz); int m_ploadw(WORD inst, WORD siz); -//FPU +// FPU int m_fabs(WORD inst, WORD siz); int m_facos(WORD inst, WORD siz); int m_fadd(WORD inst, WORD siz); @@ -126,6 +126,7 @@ int m_fmul(WORD inst, WORD siz); int m_fneg(WORD inst, WORD siz); int m_fnop(WORD inst, WORD siz); int m_frem(WORD inst, WORD siz); +int m_frestore(WORD inst, WORD siz); int m_fsabs(WORD inst, WORD siz); int m_fsadd(WORD inst, WORD siz); int m_fscc(WORD inst, WORD siz); @@ -1945,19 +1946,39 @@ int m_cinv(WORD inst, WORD siz) } +int m_fpusavrest(WORD inst, WORD siz) +{ + inst |= am0 | a0reg; + D_word(inst); + ea0gen(siz); + + return OK; +} + + // -// cpRESTORE (68020, 68030) +// cpSAVE/cpRESTORE (68020, 68030) // int m_cprest(WORD inst, WORD siz) { if (activecpu & !(CPU_68020 | CPU_68030)) return error(unsupport); - inst |= am0 | a0reg; - D_word(inst); - ea0gen(siz); + return m_fpusavrest(inst, siz); - return OK; +} + + +// +// FSAVE/FRESTORE (68040, 68060) +// +int m_frestore(WORD inst, WORD siz) +{ + if ((!(activecpu & (CPU_68040 | CPU_68060))) || + (activefpu&(FPU_68881 | FPU_68882))) + return error(unsupport); + + return m_fpusavrest(inst, siz); } @@ -2493,11 +2514,18 @@ int m_ptest(WORD inst, WORD siz) return ERROR; } +////////////////////////////////////////////////////////////////////////////// +// +// 68020/30/40/60 instructions +// Note: the map of which instructions are allowed on which CPUs came from the +// 68060 manual, section D-1 (page 392 of the PDF). The current implementation +// is missing checks for the EC models which have a simplified FPU. +// +////////////////////////////////////////////////////////////////////////////// + #define FPU_NOWARN 0 -#define FPU_P_EMUL 1 -#define FPU_P2_EMU 2 -#define FPU_FPSP 4 +#define FPU_FPSP 1 // @@ -2510,8 +2538,8 @@ static inline int gen_fpu(WORD inst, WORD siz, WORD opmode, WORD emul) inst |= (1 << 9); // Bolt on FPU id inst |= am0; - if (am0 == DREG) - inst |= a0reg; + //if (am0 == DREG || am0 == AREG) + inst |= a0reg; D_word(inst); inst = 1 << 14; // R/M field (we have ea so have to set this to 1) @@ -2553,135 +2581,158 @@ static inline int gen_fpu(WORD inst, WORD siz, WORD opmode, WORD emul) D_word(inst); } - if ((emul & FPU_FPSP) && (activefpu == FPU_68040)) - warn("Instruction is emulated in 68040"); + if ((emul & FPU_FPSP) && (activefpu == (FPU_68040 | FPU_68060))) + warn("Instruction is emulated in 68040/060"); return OK; } // -// fabs, fsabs, fdabs (6888X, 68040) +// fabs (6888X, 68040FPSP, 68060FPSP) // int m_fabs(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00011000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00011000), FPU_NOWARN); } +// +// fsabs (68040, 68060) +// int m_fsabs(WORD inst, WORD siz) { + CHECKNO40; if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011000), FPU_P_EMUL); + return gen_fpu(inst, siz, B8(01011000), FPU_NOWARN); return error("Unsupported in current FPU"); } +// +// fdabs (68040, 68060) +// int m_fdabs(WORD inst, WORD siz) { if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011100), FPU_P_EMUL); + return gen_fpu(inst, siz, B8(01011100), FPU_NOWARN); return error("Unsupported in current FPU"); } // -// facos (6888X, 68040FPSP) +// facos (6888X, 68040FPSP, 68060FPSP) // int m_facos(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00011100), FPU_FPSP); } // -// fadd (6888X, 68040FPSP) +// fadd (6888X, 68040, 68060) // int m_fadd(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100010), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100010), FPU_NOWARN); } +// +// fsadd (68040, 68060) +// int m_fsadd(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100010), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100010), FPU_NOWARN); return error("Unsupported in current FPU"); } +// +// fxadd (68040) +// int m_fdadd(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100110), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100110), FPU_NOWARN); return error("Unsupported in current FPU"); } // -// fasin (6888X, 68040FPSP)f +// fasin (6888X, 68040FPSP, 68060FPSP) // int m_fasin(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001100), FPU_FPSP); } // -// fatan (6888X, 68040FPSP) +// fatan (6888X, 68040FPSP, 68060FPSP) // int m_fatan(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001010), FPU_FPSP); } // -// fatanh (6888X, 68040FPSP) +// fatanh (6888X, 68040FPSP, 68060FPSP) // int m_fatanh(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001101), FPU_FPSP); } // -// fcmp (6888X, 68040) +// fcmp (6888X, 68040, 68060) // int m_fcmp(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00111000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00111000), FPU_FPSP); } // -// fcos (6888X, 68040FPSP) +// fcos (6888X, 68040FPSP, 68060FPSP) // int m_fcos(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00011101), FPU_FPSP); } // -// fcosh (6888X, 68040FPSP) +// fcosh (6888X, 68040FPSP, 68060FPSP) // int m_fcosh(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00011001), FPU_FPSP); } // -// fdbcc (6888X, 68040) +// fdbcc (6888X, 68040, 68060FPSP) // int m_fdbcc(WORD inst, WORD siz) { + CHECKNOFPU; WORD opcode = inst & 0x3F; // Grab conditional bitfield inst &= ~0x3F; @@ -2710,75 +2761,89 @@ int m_fdbcc(WORD inst, WORD siz) D_word(0); } + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + return OK; } // -// fdiv (6888X, 68040) +// fdiv (6888X, 68040, 68060) // int m_fdiv(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100000), FPU_NOWARN); } +// +// fsdiv (68040, 68060) +// int m_fsdiv(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100000), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100000), FPU_NOWARN); return error("Unsupported in current FPU"); } +// +// fddiv (68040, 68060) +// int m_fddiv(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100100), FPU_NOWARN); return error("Unsupported in current FPU"); } // -// fetox (6888X, 68040FPSP) +// fetox (6888X, 68040FPSP, 68060FPSP) // int m_fetox(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010000), FPU_FPSP); } // -// fetoxm1 (6888X, 68040FPSP) +// fetoxm1 (6888X, 68040FPSP, 68060FPSP) // int m_fetoxm1(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001000), FPU_FPSP); } // -// fgetexp (6888X, 68040FPSP) +// fgetexp (6888X, 68040FPSP, 68060FPSP) // int m_fgetexp(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00011110), FPU_FPSP); } // -// fgetman (6888X, 68040FPSP) +// fgetman (6888X, 68040FPSP, 68060FPSP) // int m_fgetman(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00011111), FPU_FPSP); } // -// fint (6888X, 68040FPSP) +// fint (6888X, 68040FPSP, 68060) // int m_fint(WORD inst, WORD siz) { @@ -2786,12 +2851,15 @@ int m_fint(WORD inst, WORD siz) // special case - fint fpx = fint fpx,fpx a1reg = a0reg; - return gen_fpu(inst, siz, B8(00000001), FPU_FPSP); + if (activefpu == FPU_68040) + warn("Instruction is emulated in 68040"); + + return gen_fpu(inst, siz, B8(00000001), FPU_NOWARN); } // -// fintrz (6888X, 68040FPSP) +// fintrz (6888X, 68040FPSP, 68060) // int m_fintrz(WORD inst, WORD siz) { @@ -2799,64 +2867,76 @@ int m_fintrz(WORD inst, WORD siz) // special case - fintrz fpx = fintrz fpx,fpx a1reg = a0reg; - return gen_fpu(inst, siz, B8(00000011), FPU_FPSP); + if (activefpu == FPU_68040) + warn("Instruction is emulated in 68040"); + + return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN); } // -// flog10 (6888X, 68040FPSP) +// flog10 (6888X, 68040FPSP, 68060FPSP) // int m_flog10(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010101), FPU_FPSP); } // -// flog2 (6888X, 68040FPSP) +// flog2 (6888X, 68040FPSP, 68060FPSP) // int m_flog2(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010110), FPU_FPSP); } // -// flogn (6888X, 68040FPSP) +// flogn (6888X, 68040FPSP, 68060FPSP) // int m_flogn(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010100), FPU_FPSP); } // -// flognp1 (6888X, 68040FPSP) +// flognp1 (68040FPSP, 68060FPSP) // int m_flognp1(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00000110), FPU_FPSP); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(00000110), FPU_FPSP); + + return error("Unsupported in current FPU"); } // -// fmod (6888X, 68040FPSP) +// fmod (6888X, 68040FPSP, 68060FPSP) // int m_fmod(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00100001), FPU_FPSP); } // -// fmove (6888X, 68040) +// fmove (6888X, 68040, 68060) // int m_fmove(WORD inst, WORD siz) { + CHECKNOFPU; + // EA to register if ((am0 == FREG) && (am1 < AM_USP)) { - //fpx->ea + // fpx->ea // EA inst |= am1 | a1reg; D_word(inst); @@ -2955,13 +3035,13 @@ int m_fmove(WORD inst, WORD siz) inst = 0 << 14; // Source specifier - if (siz != SIZX) + if (siz != SIZX && siz != SIZN) return error("Invalid size"); // Source register inst |= (a0reg << 10); - // Destination register + // Destination register inst |= (a1reg << 7); D_word(inst); @@ -2972,10 +3052,12 @@ int m_fmove(WORD inst, WORD siz) // -// fmove (6888X, 68040) +// fmove (6888X, 68040, 68060) // int m_fmovescr(WORD inst, WORD siz) { + CHECKNOFPU; + // Move Floating-Point System Control Register (FPCR) // ea // dr @@ -3005,10 +3087,13 @@ int m_fmovescr(WORD inst, WORD siz) } // -// fsmove/fdmove (68040) +// fsmove/fdmove (68040, 68060) // int m_fsmove(WORD inst, WORD siz) { + if (!(activefpu & (FPU_68040 | FPU_68060))) + return error("Unsupported in current FPU"); + return error("Not implemented yet."); #if 0 @@ -3022,6 +3107,9 @@ int m_fsmove(WORD inst, WORD siz) int m_fdmove(WORD inst, WORD siz) { + if (!(activefpu & (FPU_68040 | FPU_68060))) + return error("Unsupported in current FPU"); + return error("Not implemented yet."); #if 0 @@ -3034,10 +3122,12 @@ int m_fdmove(WORD inst, WORD siz) // -// fmovecr (6888X, 68040FPSP) +// fmovecr (6888X, 68040FPSP, 68060FPSP) // int m_fmovecr(WORD inst, WORD siz) { + CHECKNOFPU; + D_word(inst); inst = 0x5c00; inst |= a1reg << 7; @@ -3045,17 +3135,19 @@ int m_fmovecr(WORD inst, WORD siz) D_word(inst); if (activefpu == FPU_68040) - warn("Instruction is emulated in 68040"); + warn("Instruction is emulated in 68040/060"); return OK; } // -// fmovem (6888X, 68040) +// fmovem (6888X, 68040, 68060FPSP) // int m_fmovem(WORD inst, WORD siz) { + CHECKNOFPU; + WORD regmask; WORD datareg; @@ -3063,7 +3155,7 @@ int m_fmovem(WORD inst, WORD siz) { if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) { - //fmovem.x ,ea + // fmovem.x ,ea if (fpu_reglist_left(®mask) < 0) return OK; @@ -3100,6 +3192,11 @@ int m_fmovem(WORD inst, WORD siz) if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC))) return error("invalid addressing mode"); + // Quote from the 060 manual: + // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list." + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + D_word(inst); inst = (1 << 15) | (1 << 14) | (1 << 13) | (1 << 11) | (datareg << 4); D_word(inst); @@ -3119,7 +3216,7 @@ int m_fmovem(WORD inst, WORD siz) if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) { - //fmovem.x ea, + // fmovem.x ea, if (fpu_reglist_right(®mask) < 0) return OK; @@ -3133,6 +3230,12 @@ int m_fmovem(WORD inst, WORD siz) { // fmovem.x ea,Dn datareg = (*tok++ & 7) << 10; + + // Quote from the 060 manual: + // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list." + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + D_word(inst); inst = (1 << 15) | (1 << 14) | (0 << 13) | (3 << 11) | (datareg << 4); D_word(inst); @@ -3145,13 +3248,16 @@ int m_fmovem(WORD inst, WORD siz) { if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR)) { - //fmovem.l ,ea + // fmovem.l ,ea regmask = (1 << 15) | (1 << 13); + int no_control_regs = 0; + fmovem_loop_1: if (*tok == KW_FPCR) { regmask |= (1 << 12); tok++; + no_control_regs++; goto fmovem_loop_1; } @@ -3159,6 +3265,7 @@ fmovem_loop_1: { regmask |= (1 << 11); tok++; + no_control_regs++; goto fmovem_loop_1; } @@ -3166,6 +3273,7 @@ fmovem_loop_1: { regmask |= (1 << 10); tok++; + no_control_regs++; goto fmovem_loop_1; } @@ -3181,6 +3289,14 @@ fmovem_loop_1: if (amode(0) < 0) return OK; + // Quote from the 060 manual: + // "[..] when the processor attempts to execute an FMOVEM.L instruction with + // an immediate addressing mode to more than one floating - point + // control register (FPCR, FPSR, FPIAR)[..]" + if (activefpu == FPU_68060) + if (no_control_regs > 1 && am0 == IMMED) + warn("Instruction is emulated in 68060"); + inst |= am0 | a0reg; D_word(inst); D_word(regmask); @@ -3188,7 +3304,7 @@ fmovem_loop_1: } else { - //fmovem.l ea, + // fmovem.l ea, if (amode(0) < 0) return OK; @@ -3244,93 +3360,135 @@ fmovem_loop_2: // -// fmul (6888X, 68040) +// fmul (6888X, 68040, 68060) // int m_fmul(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100011), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100011), FPU_NOWARN); } +// +// fsmul (68040, 68060) +// int m_fsmul(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100011), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN); + + return error("Unsupported in current FPU"); } +// +// fdmul (68040) +// int m_fdmul(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100111), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100111), FPU_NOWARN); + + return error("Unsupported in current FPU"); } // -// fneg (6888X, 68040) +// fneg (6888X, 68040, 68060) // int m_fneg(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00011010), FPU_P_EMUL); + CHECKNOFPU; + + if (am1 == AM_NONE) + { + a1reg = a0reg; + return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN); + } + + return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN); } +// +// fsneg (68040, 68060) +// int m_fsneg(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011010), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + { + if (am1 == AM_NONE) + { + a1reg = a0reg; + return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN); + } + + return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN); + } + + return error("Unsupported in current FPU"); } +// +// fdneg (68040, 68060) +// int m_fdneg(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011110), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + { + if (am1 == AM_NONE) + { + a1reg = a0reg; + return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN); + } + + return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN); + } return error("Unsupported in current FPU"); } // -// fnop (6888X, 68040) +// fnop (6888X, 68040, 68060) // int m_fnop(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00000000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00000000), FPU_NOWARN); } // -// frem (6888X, 68040FPSP) +// frem (6888X, 68040FPSP, 68060FPSP) // int m_frem(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00100101), FPU_FPSP); } // -// fscale (6888X, 68040FPSP) +// fscale (6888X, 68040FPSP, 68060FPSP) // int m_fscale(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00100110), FPU_FPSP); } // -// FScc (6888X, 68040), cpScc (68851, 68030), PScc (68851) +// FScc (6888X, 68040, 68060), cpScc (68851, 68030), PScc (68851) // TODO: Add check for PScc to ensure 68020+68851 active // TODO: Add check for cpScc to ensure 68020+68851, 68030 // int m_fscc(WORD inst, WORD siz) { + CHECKNOFPU; + // We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0), // so we need to extract them first and fill in the clobbered bits. WORD opcode = inst & 0x1F; @@ -3339,78 +3497,49 @@ int m_fscc(WORD inst, WORD siz) D_word(inst); ea0gen(siz); D_word(opcode); + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); return OK; } // -// FTRAPcc (6888X, 68040) -// -int m_ftrapcc(WORD inst, WORD siz) -{ - // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7), - // so we need to extract them first and fill in the clobbered bits. - WORD opcode = (inst >> 3) & 0x1F; - inst = (inst & 0xFF07) | (0xF << 3); - - if (siz == SIZW) - { - inst |= 2; - D_word(inst); - D_word(opcode); - D_word(a0exval); - } - else if (siz == SIZL) - { - inst |= 3; - D_word(inst); - D_word(opcode); - D_long(a0exval); - } - else if (siz = SIZN) - { - inst |= 4; - D_word(inst); - D_word(opcode); - return OK; - } - - return OK; -} - - -// -// fsgldiv (6888X, 68040) +// fsgldiv (6888X, 68040FPSP, 68060FPSP) // int m_fsgldiv(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100100), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100100), FPU_FPSP); } // -// fsglmul (6888X, 68040) +// fsglmul (6888X, 68040, 68060FPSP) // int m_fsglmul(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100111), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100111), FPU_FPSP); } // -// fsin (6888X, 68040FPSP) +// fsin (6888X, 68040FPSP, 68060FPSP) // int m_fsin(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001110), FPU_FPSP); } // -// fsincos (6888X, 68040FPSP) +// fsincos (6888X, 68040FPSP, 68060FPSP) // int m_fsincos(WORD inst, WORD siz) { + CHECKNOFPU; + // Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu // generates int temp; @@ -3429,109 +3558,170 @@ int m_fsincos(WORD inst, WORD siz) // -// fsin (6888X, 68040FPSP) +// fsinh (6888X, 68040FPSP, 68060FPSP) // int m_fsinh(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00000010), FPU_FPSP); } // -// fsqrt (6888X, 68040) +// fsqrt (6888X, 68040, 68060) // int m_fsqrt(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00000100), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00000100), FPU_NOWARN); } +// +// fsfsqrt (68040, 68060) +// int m_fsfsqrt(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01000001), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN); + + return error("Unsupported in current FPU"); } +// +// fdfsqrt (68040, 68060) +// int m_fdfsqrt(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01000101), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01000101), FPU_NOWARN); return error("Unsupported in current FPU"); } // -// fsub (6888X, 68040) +// fsub (6888X, 68040, 68060) // int m_fsub(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00101000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00101000), FPU_NOWARN); } +// +// fsfsub (68040, 68060) +// int m_fsfsub(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01101000), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01101000), FPU_NOWARN); return error("Unsupported in current FPU"); } +// +// fdfsub (68040, 68060) +// int m_fdsub(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01101100), FPU_P_EMUL); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01101100), FPU_NOWARN); return error("Unsupported in current FPU"); } // -// ftan (6888X, 68040FPSP) +// ftan (6888X, 68040FPSP, 68060FPSP) // int m_ftan(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001111), FPU_FPSP); } // -// ftanh (6888X, 68040FPSP) +// ftanh (6888X, 68040FPSP, 68060FPSP) // int m_ftanh(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001001), FPU_FPSP); } // -// ftentox (6888X, 68040FPSP) +// ftentox (6888X, 68040FPSP, 68060FPSP) // int m_ftentox(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010010), FPU_FPSP); } // -// ftst (6888X, 68040) +// FTRAPcc (6888X, 68040, 68060FPSP) +// +int m_ftrapcc(WORD inst, WORD siz) +{ + CHECKNOFPU; + + // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7), + // so we need to extract them first and fill in the clobbered bits. + WORD opcode = (inst >> 3) & 0x1F; + inst = (inst & 0xFF07) | (0xF << 3); + + if (siz == SIZW) + { + inst |= 2; + D_word(inst); + D_word(opcode); + D_word(a0exval); + } + else if (siz == SIZL) + { + inst |= 3; + D_word(inst); + D_word(opcode); + D_long(a0exval); + } + else if (siz == SIZN) + { + inst |= 4; + D_word(inst); + D_word(opcode); + return OK; + } + + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + + return OK; +} + + +// +// ftst (6888X, 68040, 68060) // int m_ftst(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00111010), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00111010), FPU_NOWARN); } // -// ftwotox (6888X, 68040FPSP) +// ftwotox (6888X, 68040FPSP, 68060FPSP) // int m_ftwotox(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010001), FPU_FPSP); } diff --git a/sect.h b/sect.h index bae68eb..3f6f28e 100644 --- a/sect.h +++ b/sect.h @@ -139,6 +139,7 @@ SECT { #define FPU_68881 1 #define FPU_68882 2 #define FPU_68040 4 +#define FPU_68060 8 // Helper macros to test for active CPU #define CHECK00 if (activecpu == CPU_68000) return error(unsupport) @@ -151,7 +152,7 @@ SECT { #define CHECKNO30 if (activecpu != CPU_68030) return error(unsupport) #define CHECKNO40 if (activecpu != CPU_68040) return error(unsupport) #define CHECKNO60 if (activecpu != CPU_68060) return error(unsupport) - +#define CHECKNOFPU if (!activefpu) return error(unsupport) // Globals, external etc extern uint32_t sloc; -- 2.37.2