divu.l/divs.l/mulu.l/muls.l debugged and condensed into one function
authorggn <ggn.dbug@gmail.com>
Tue, 23 Jan 2018 09:33:24 +0000 (11:33 +0200)
committerShamus Hammons <jlhamm@acm.org>
Wed, 24 Jan 2018 01:45:24 +0000 (19:45 -0600)
68ktab
amode.c
mach.c

diff --git a/68ktab b/68ktab
index a8eca59a4fe7bf289511e69dd9d855015a161ddc..017d044f826eb64858469fe81de9279608a21eb1 100644 (file)
--- a/68ktab
+++ b/68ktab
@@ -245,16 +245,14 @@ dbvc  NW     M_DREG          C_LABEL         %0101100011001rrr   m_dbra
 dbvs  NW     M_DREG          C_LABEL         %0101100111001rrr   m_dbra
 
 divs  NW     C_DATA          M_DREG          %1000rrr111eR1000   m_ea     +
--     L      C_DATA030       M_DREG          %0100110001eeeeee   m_divs   +
--     L      C_DATA030       M_DREG          %0100110001eeeeee   m_divs
+-     L      C_DATA030       M_DREG          %0100111101eeeeee   m_muls
 
-divsl NL     C_DATA030       M_DREG          %0100110001eeeeee   m_divsl
+divsl NL     C_DATA030       M_DREG          %0100111001eeeeee   m_muls
 
 divu  NW     C_DATA          M_DREG          %1000rrr011eR1000   m_ea     +
--     L      C_DATA030       M_DREG          %0100110001eeeeee   m_divu   +
--     L      C_DATA030       M_DREG          %0100110001eeeeee   m_divu   +
+-     L      C_DATA030       M_DREG          %0100110101eeeeee   m_muls
 
-divul LN     C_DATA030       M_DREG          %0100110001eeeeee   m_divul
+divul LN     C_DATA030       M_DREG          %0100110001eeeeee   m_muls
 
 eor   NBWL   M_DREG          C_ALTDATA       %1011rrr1sseR0S01   m_ea      +
 eori  NBWL   M_IMMED         C_ALTDATA       %00001010sseeeS11   m_ea      +
@@ -618,9 +616,9 @@ movep NWL    M_DREG          M_AIND|M_ADISP  %0000rrr11s001aaa   m_movep   +
 moveq NL     M_IMMED         M_DREG          %0111rrr0dddddddd   m_moveq
 
 muls  NW     C_DATA          M_DREG          %1100rrr111eR1000   m_ea      +
--     L      C_DATA030       M_DREG          %0100110000eeeeee   m_muls
+-     L      C_DATA030       M_DREG          %0100111100eeeeee   m_muls    
 mulu  NW     C_DATA          M_DREG          %1100rrr011eR1000   m_ea      +
--     L      C_DATA030       M_DREG          %0100110000eeeeee   m_mulu
+-     L      C_DATA030       M_DREG          %0100110100eeeeee   m_muls
 
 nbcd  NB     C_ALTDATA       M_AM_NONE       %0100100000eee000   m_ea
 neg   NBWL   C_ALTDATA       M_AM_NONE       %01000100sseeeS00   m_ea
diff --git a/amode.c b/amode.c
index 7ba585349883a49b2fa1e897dd7060882f3a0e80..fb10055f1968bf45985cd193392c6f42bb57d071 100644 (file)
--- a/amode.c
+++ b/amode.c
@@ -61,7 +61,6 @@ WORD a1extension;                     // 020+ extension address word
 WORD am1_030;                          // ea bits for 020+ addressing modes
 
 int a2reg;                                     // Register for div.l (68020+)
-WORD mulmode;                          // to distinguish between 32 and 64 bit multiplications (68020+)
 
 int bfparam1;                          // bfxxx / fmove instruction parameter 1
 int bfparam2;                          // bfxxx / fmove instruction parameter 2
@@ -186,25 +185,20 @@ int amode(int acount)
 
                if ((*tok >= KW_D0) && (*tok <= KW_D7))
                {
-                       a2reg = (*tok - KW_D0);
-                       mulmode = 1 << 10;
+                       a2reg = (*tok++) & 7;
                }
                else if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
                {
-                       a2reg = (*tok - KW_FP0);
-                       mulmode = 1 << 10;
+                       a2reg = (*tok++) & 7;
                }
                else
                        return error("a data or FPU register must follow a :");
-
-               *tok++;
        }
        else
        {
                // If no ':' is present then maybe we have something like divs.l d0,d1
                // which sould translate to divs.l d0,d1:d1
                a2reg = a1reg;
-               mulmode = 0;
        }
 
        nmodes = 2;
diff --git a/mach.c b/mach.c
index ef4c8c6837c88cbf3c43675a96eebf4c6655ff64..b49fcb74445ddfa39a869643fb2614c03934dd8e 100644 (file)
--- a/mach.c
+++ b/mach.c
@@ -41,7 +41,6 @@ int m_dbra(WORD, WORD);
 int m_link(WORD, WORD);
 int m_adda(WORD, WORD);
 int m_addq(WORD, WORD);
-//int m_move(WORD, int);
 int m_move(WORD, WORD);
 int m_moveq(WORD, WORD);
 int m_usp(WORD, WORD);
@@ -63,12 +62,7 @@ int m_cmp2(WORD inst, WORD siz);
 int m_bkpt(WORD inst, WORD siz);
 int m_cpbr(WORD inst, WORD siz);
 int m_cpdbr(WORD inst, WORD siz);
-int m_divs(WORD inst, WORD siz);
 int m_muls(WORD inst, WORD siz);
-int m_divu(WORD inst, WORD siz);
-int m_mulu(WORD inst, WORD siz);
-int m_divsl(WORD inst, WORD siz);
-int m_divul(WORD inst, WORD siz);
 int m_move16a(WORD inst, WORD siz);
 int m_move16b(WORD inst, WORD siz);
 int m_pack(WORD inst, WORD siz);
@@ -1122,7 +1116,7 @@ int m_clrd(WORD inst, WORD siz)
 
 ////////////////////////////////////////
 //
-// 68020/30/40 instructions
+// 68020/30/40/60 instructions
 //
 ////////////////////////////////////////
 
@@ -1618,62 +1612,7 @@ int m_cpdbr(WORD inst, WORD siz)
 
 
 //
-// divs.l
-//
-int m_divs(WORD inst, WORD siz)
-{
-       if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
-               return error(unsupport);
-
-       WORD flg = inst;                                        // Save flag bits
-       inst &= ~0x3F;                                          // Clobber flag bits in instr
-
-       // Install "standard" instr size bits
-       if (flg & 4)
-               inst |= siz_6[siz];
-
-       if (flg & 16)
-       {
-               // OR-in register number
-               if (flg & 8)
-                       inst |= reg_9[a1reg];           // ea1reg in bits 9..11
-               else
-                       inst |= reg_9[a0reg];           // ea0reg in bits 9..11
-       }
-
-       if (flg & 1)
-       {
-               // Use am1
-               inst |= am1 | a1reg;                    // Get ea1 into instr
-               D_word(inst);                                   // Deposit instr
-
-               // Generate ea0 if requested
-               if (flg & 2)
-                       ea0gen(siz);
-
-               ea1gen(siz);                                    // Generate ea1
-       }
-       else
-       {
-               // Use am0
-               inst |= am0 | a0reg;                    // Get ea0 into instr
-               D_word(inst);                                   // Deposit instr
-               ea0gen(siz);                                    // Generate ea0
-
-               // Generate ea1 if requested
-               if (flg & 2)
-                       ea1gen(siz);
-       }
-
-       inst = a1reg + (a2reg << 12) + (1 << 11);
-       D_word(inst);
-
-       return OK;
-}
-
-
-//
-// muls.l
+// muls.l / divs.l / divu.l / mulu.l (68020+)
 //
 int m_muls(WORD inst, WORD siz)
 {
@@ -1681,7 +1620,7 @@ int m_muls(WORD inst, WORD siz)
                return error(unsupport);
 
        WORD flg = inst;                                        // Save flag bits
-       inst &= ~0x3F;                                          // Clobber flag bits in instr
+       inst &= ~0x33F;                                         // Clobber flag and extension bits in instr
 
        // Install "standard" instr size bits
        if (flg & 4)
@@ -1689,79 +1628,20 @@ int m_muls(WORD inst, WORD siz)
 
        if (flg & 16)
        {
-               // OR-in register number
+               // OR-in register number 
                if (flg & 8)
                        inst |= reg_9[a1reg];           // ea1reg in bits 9..11
                else
                        inst |= reg_9[a0reg];           // ea0reg in bits 9..11
        }
 
-       if (flg & 1)
-       {
-               // Use am1
-               inst |= am1 | a1reg;                    // Get ea1 into instr
-               D_word(inst);                                   // Deposit instr
-
-                                                                               // Extension word
-               inst = a1reg + (a2reg << 12) + (1 << 11);
-               inst |= mulmode;  // add size bit
-               D_word(inst);
-
-               // Generate ea0 if requested
-               if (flg & 2)
-                       ea0gen(siz);
-
-               ea1gen(siz);                                    // Generate ea1
-       }
-       else
-       {
-               // Use am0
-               inst |= am0 | a0reg;                    // Get ea0 into instr
-               D_word(inst);                                   // Deposit instr
-                                                                               // Extension word
-               inst = a1reg + (a2reg << 12) + (1 << 11);
-               inst |= mulmode;  // add size bit
-               D_word(inst);
-
-               ea0gen(siz);                                    // Generate ea0
-
-               // Generate ea1 if requested
-               if (flg & 2)
-                       ea1gen(siz);
-       }
-
-       //D_word(inst);
-       //ea0gen(siz);
-
-       return OK;
-}
-
-
-//
-// divu.l
-//
-int m_divu(WORD inst, WORD siz)
-{
-       if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
-               return error(unsupport);
-
-       //WARNING("divu.l d0,d1 is actually divul.l d0,d1:d1!!!")
-
-       WORD flg = inst;                                        // Save flag bits
-       inst &= ~0x3F;                                          // Clobber flag bits in instr
-
-       // Install "standard" instr size bits
-       if (flg & 4)
-               inst |= siz_6[siz];
-
-       if (flg & 16)
-       {
-               // OR-in register number
-               if (flg & 8)
-                       inst |= reg_9[a1reg];           // ea1reg in bits 9..11
-               else
-                       inst |= reg_9[a0reg];           // ea0reg in bits 9..11
-       }
+       // Regarding extension word: bit 11 is signed/unsigned selector
+       //                           bit 10 is 32/64 bit selector
+       // Both of these are packed in bits 9 and 8 of the instruction
+       // field in 68ktab. Extra compilcations arise from the fact we
+       // have to distinguish between divu/s.l Dn,Dm (which is encoded
+       // as divu/s.l Dn,Dm:Dm) and divu/s.l Dn,Dm:Dx - the first is
+       // 32 bit while the second 64 bit
 
        if (flg & 1)
        {
@@ -1769,194 +1649,44 @@ int m_divu(WORD inst, WORD siz)
                inst |= am1 | a1reg;                    // Get ea1 into instr
                D_word(inst);                                   // Deposit instr
 
-               // Generate ea0 if requested
-               if (flg & 2)
-                       ea0gen(siz);
-
-               ea1gen(siz);                                    // Generate ea1
-       }
-       else
-       {
-               // Use am0
-               inst |= am0 | a0reg;                    // Get ea0 into instr
-               D_word(inst);                                   // Deposit instr
-               ea0gen(siz);                                    // Generate ea0
-
-                                                                               // Generate ea1 if requested
-               if (flg & 2)
-                       ea1gen(siz);
-       }
-
-       inst = a1reg + (a2reg << 12);
-       D_word(inst);
-
-       return OK;
-}
-
-
-//
-// mulu.l
-//
-int m_mulu(WORD inst, WORD siz)
-{
-       if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
-               return error(unsupport);
-
-       WORD flg = inst;                                        // Save flag bits
-       inst &= ~0x3F;                                          // Clobber flag bits in instr
-
-       // Install "standard" instr size bits
-       if (flg & 4)
-               inst |= siz_6[siz];
-
-       if (flg & 16)
-       {
-               // OR-in register number
-               if (flg & 8)
-                       inst |= reg_9[a1reg];           // ea1reg in bits 9..11
+               // Extension word
+               if (a1reg == a2reg)
+                       inst = a1reg + (a2reg << 12) + ((flg & 0x200) << 2);
                else
-                       inst |= reg_9[a0reg];           // ea0reg in bits 9..11
-       }
+                       inst = a1reg + (a2reg << 12) + ((flg & 0x300) << 2);
 
-       if (flg & 1)
-       {
-               // Use am1
-               inst |= am1 | a1reg;                    // Get ea1 into instr
-               D_word(inst);                                   // Deposit instr
+                D_word(inst);
 
-               // Generate ea0 if requested
+               // Generate ea0 if requested 
                if (flg & 2)
                        ea0gen(siz);
 
                ea1gen(siz);                                    // Generate ea1
-       }
-       else
-       {
-               // Use am0
-               inst |= am0 | a0reg;                    // Get ea0 into instr
-               D_word(inst);                                   // Deposit instr
-               ea0gen(siz);                                    // Generate ea0
-
-               // Generate ea1 if requested
-               if (flg & 2)
-                       ea1gen(siz);
-       }
-
-       inst = a1reg + (a2reg << 12);
-    inst |= mulmode;  // add size bit
-       D_word(inst);
-
-       return OK;
-}
-
-
-//
-// divsl.l
-//
-int m_divsl(WORD inst, WORD siz)
-{
-       if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
-               return error(unsupport);
-
-       WORD flg = inst;                                        // Save flag bits
-       inst &= ~0x3F;                                          // Clobber flag bits in instr
-
-       // Install "standard" instr size bits
-       if (flg & 4)
-               inst |= siz_6[siz];
-
-       if (flg & 16)
-       {
-               // OR-in register number
-               if (flg & 8)
-                       inst |= reg_9[a1reg];           // ea1reg in bits 9..11
-               else
-                       inst |= reg_9[a0reg];           // ea0reg in bits 9..11
-       }
-
-       if (flg & 1)
-       {
-               // Use am1
-               inst |= am1 | a1reg;                    // Get ea1 into instr
-               D_word(inst);                                   // Deposit instr
-
-               // Generate ea0 if requested
-               if (flg & 2)
-                       ea0gen(siz);
 
-               ea1gen(siz);                                    // Generate ea1
+               return OK;
        }
        else
        {
                // Use am0
                inst |= am0 | a0reg;                    // Get ea0 into instr
                D_word(inst);                                   // Deposit instr
-               ea0gen(siz);                                    // Generate ea0
-
-               // Generate ea1 if requested
-               if (flg & 2)
-                       ea1gen(siz);
-       }
-
-       inst = a1reg + (a2reg << 12) + (1 << 11) + (1 << 10);
-       D_word(inst);
-
-       return OK;
-}
-
-
-//
-// divul.l
-//
-int m_divul(WORD inst, WORD siz)
-{
-       if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
-               return error(unsupport);
-
-       WORD flg = inst;                                        // Save flag bits
-       inst &= ~0x3F;                                          // Clobber flag bits in instr
-
-       // Install "standard" instr size bits
-       if (flg & 4)
-               inst |= siz_6[siz];
 
-       if (flg & 16)
-       {
-               // OR-in register number
-               if (flg & 8)
-                       inst |= reg_9[a1reg];           // ea1reg in bits 9..11
+               // Extension word
+               if (a1reg == a2reg)
+                       inst = a1reg + (a2reg << 12) + ((flg & 0x200) << 2);
                else
-                       inst |= reg_9[a0reg];           // ea0reg in bits 9..11
-       }
-
-       if (flg & 1)
-       {
-               // Use am1
-               inst |= am1 | a1reg;                    // Get ea1 into instr
-               D_word(inst);                                   // Deposit instr
+                       inst = a1reg + (a2reg << 12) + ((flg & 0x300) << 2);
 
-               // Generate ea0 if requested
-               if (flg & 2)
-                       ea0gen(siz);
+               D_word(inst);
 
-               ea1gen(siz);                                    // Generate ea1
-       }
-       else
-       {
-               // Use am0
-               inst |= am0 | a0reg;                    // Get ea0 into instr
-               D_word(inst);                                   // Deposit instr
                ea0gen(siz);                                    // Generate ea0
 
                // Generate ea1 if requested
                if (flg & 2)
                        ea1gen(siz);
-       }
-
-       inst = a1reg + (a2reg << 12) + (1 << 10);
-       D_word(inst);
 
-       return OK;
+               return OK;
+       }
 }