X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=riscasm.c;h=a76cb2e19a1438310e38939571546a29cc1569cb;hp=4925adce0c8cc2b46ac0750af4ed422ac5df9702;hb=f3c7d186a15b89c39e360b9cc89545a0d24bd6a4;hpb=61ba7cfa9ae30c0c8211e12b00924ce4efc2c847 diff --git a/riscasm.c b/riscasm.c index 4925adc..a76cb2e 100644 --- a/riscasm.c +++ b/riscasm.c @@ -1,49 +1,51 @@ // -// RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System +// RMAC - Reboot's Macro Assembler for all Atari computers // RISCA.C - GPU/DSP Assembler -// Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends +// Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986 -// Source Utilised with the Kind Permission of Landon Dyer +// Source utilised with the kind permission of Landon Dyer // #include "riscasm.h" +#include "amode.h" +#include "direct.h" #include "error.h" -#include "sect.h" -#include "token.h" #include "expr.h" -#include "direct.h" #include "mark.h" -#include "amode.h" +#include "procln.h" +#include "sect.h" +#include "token.h" -#define DEF_MR // Declar keyword values -#include "risckw.h" // Incl generated risc keywords +#define DEF_MR // Declare keyword values +#include "risckw.h" // Incl. generated risc keywords -#define DEF_KW // Declare keyword values -#include "kwtab.h" // Incl generated keyword tables & defs +#define DEF_KW // Declare keyword values +#include "kwtab.h" // Incl. generated keyword tables & defs unsigned altbankok = 0; // Ok to use alternate register bank -unsigned orgactive = 0; // RISC org directive active +unsigned orgactive = 0; // RISC/6502 org directive active unsigned orgaddr = 0; // Org'd address unsigned orgwarning = 0; // Has an ORG warning been issued int lastOpcode = -1; // Last RISC opcode assembled +uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen -char reg_err[] = "missing register R0...R31"; +const char reg_err[] = "missing register R0...R31"; -// Jaguar Jump Condition Names -char condname[MAXINTERNCC][5] = { +// Jaguar jump condition names +const char condname[MAXINTERNCC][5] = { "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ", - "N", "N_NZ", "N_Z ", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO", + "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO", "PL", "MI", "F" }; -// Jaguar Jump Condition Numbers -char condnumber[] = { +// Jaguar jump condition numbers +const char condnumber[] = { 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26, 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31 }; -struct opcoderecord roptbl[] = { +const struct opcoderecord roptbl[] = { { MR_ADD, RI_TWO, 0 }, { MR_ADDC, RI_TWO, 1 }, { MR_ADDQ, RI_NUM_32, 2 }, @@ -100,8 +102,8 @@ struct opcoderecord roptbl[] = { { MR_NORMI, RI_TWO, 56 }, { MR_NOP, RI_NONE, 57 }, { MR_SAT24, RI_ONE, 62 }, - { MR_UNPACK, RI_ONE, 63 + GPUONLY }, - { MR_PACK, RI_ONE, 63 + GPUONLY }, + { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) }, + { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) }, { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY }, { MR_MOVE, RI_MOVE, 0 }, { MR_LOAD, RI_LOAD, 0 }, @@ -110,7 +112,7 @@ struct opcoderecord roptbl[] = { // -// Convert a String to Uppercase +// Convert a string to uppercase // void strtoupper(char * s) { @@ -125,44 +127,60 @@ void strtoupper(char * s) // static inline int MalformedOpcode(int signal) { - char buf[16]; - sprintf(buf, "%02X", signal); - errors("Malformed opcode [internal $%s]", buf); - return ERROR; + return error("Malformed opcode [internal $%02X]", signal); } // -// Build RISC Instruction Word +// Function to return "Illegal Indexed Register" error +// Anyone trying to index something other than R14 or R15 +// +static inline int IllegalIndexedRegister(int reg) +{ + return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0); +} + + +// +// Function to return "Illegal Indexed Register" error for EQUR scenarios +// Trying to use register value within EQUR that isn't 14 or 15 +// +static inline int IllegalIndexedRegisterEqur(SYM * sy) +{ + return error("Attempted index reference with non-indexable register within EQUR (%s = r%d)", sy->sname, sy->svalue); +} + + +// +// Build RISC instruction word // void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2) { // Check for absolute address setting if (!orgwarning && !orgactive) { - warn("GPU/DSP code outside of absolute section"); + warn("RISC code generated with no origin defined"); orgwarning = 1; } int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F); D_word(value); +//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value); } // -// Get a RISC Register +// Get a RISC register // int GetRegister(WORD rattr) { - VALUE eval; // Expression value + uint64_t eval; // Expression value WORD eattr; // Expression attributes SYM * esym; // External symbol involved in expr. TOKEN r_expr[EXPRSIZE]; // Expression token list // Evaluate what's in the global "tok" buffer - if (expr(r_expr, &eval, &eattr, &esym) != OK) - // Hmm, the evaluator should report the error to us... -// return MalformedOpcode(0x00); + if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK) return ERROR; if ((challoc - ch_size) < 4) @@ -170,22 +188,21 @@ int GetRegister(WORD rattr) if (!(eattr & DEFINED)) { - fixup((WORD)(FU_WORD | rattr), sloc, r_expr); + AddFixup((WORD)(FU_WORD | rattr), sloc, (TOKENPTR)r_expr); return 0; } // If we got a register in range (0-31), return it if ((eval >= 0) && (eval <= 31)) - return eval; + return (int)eval; // Otherwise, it's out of range & we flag an error - error(reg_err); - return ERROR; + return error(reg_err); } // -// Do RISC Code Generation +// Do RISC code generation // int GenerateRISCCode(int state) { @@ -200,7 +217,7 @@ int GenerateRISCCode(int state) WORD attrflg; int indexed; // Indexed register flag - VALUE eval; // Expression value + uint64_t eval; // Expression value WORD eattr; // Expression attributes SYM * esym; // External symbol involved in expr. TOKEN r_expr[EXPRSIZE]; // Expression token list @@ -208,15 +225,13 @@ int GenerateRISCCode(int state) // Get opcode parameter and type unsigned short parm = (WORD)(roptbl[state - 3000].parm); unsigned type = roptbl[state - 3000].typ; + riscImmTokenSeen = 0; // Set to "token not seen yet" // Detect whether the opcode parmeter passed determines that the opcode is // specific to only one of the RISC processors and ensure it is legal in // the current code section. If not then show error and return. if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu)) - { - error("Opcode is not valid in this code section"); - return ERROR; - } + return error("Opcode is not valid in this code section"); // Process RISC opcode switch (type) @@ -228,22 +243,23 @@ int GenerateRISCCode(int state) break; // Single operand instructions (Rd) - // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK + // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, + // UNPACK case RI_ONE: reg2 = GetRegister(FU_REGTWO); at_eol(); BuildRISCIntructionWord(parm, parm >> 6, reg2); - break; + break; // Two operand instructions (Rs,Rd) - // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT, - // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR - case RI_TWO: + // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, + // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR + case RI_TWO: if (parm == 37) altbankok = 1; // MOVEFA reg1 = GetRegister(FU_REGONE); - CHECK_COMMA; + CHECK_COMMA; if (parm == 36) altbankok = 1; // MOVETA @@ -262,7 +278,8 @@ int GenerateRISCCode(int state) case RI_NUM_31: // Numeric operand (n,Rd) where n = 1..32 - // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ + // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, + // RORQ case RI_NUM_32: switch (type) { @@ -281,12 +298,13 @@ int GenerateRISCCode(int state) if (parm & SUB32) attrflg |= FU_SUB32; - if (*tok != '#') + if (*tok.u32 != '#') return MalformedOpcode(0x01); - tok++; + tok.u32++; + riscImmTokenSeen = 1; - if (expr(r_expr, &eval, &eattr, &esym) != OK) + if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x02); if ((challoc - ch_size) < 4) @@ -294,23 +312,20 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup((WORD)(FU_WORD | attrflg), sloc, r_expr); + AddFixup((WORD)(FU_WORD | attrflg), sloc, (TOKENPTR)r_expr); reg1 = 0; } else { if ((int)eval < reg1 || (int)eval > reg2) - { - error("constant out of range"); - return ERROR; - } + return error("constant out of range"); - if (parm & SUB32) - reg1 = 32 - eval; + if (parm & SUB32) + reg1 = 32 - (int)eval; else if (type == RI_NUM_32) - reg1 = (reg1 == 32 ? 0 : eval); + reg1 = (reg1 == 32 ? 0 : (int)eval); else - reg1 = eval; + reg1 = (int)eval; } CHECK_COMMA; @@ -321,12 +336,22 @@ int GenerateRISCCode(int state) // Move Immediate--n,Rn--n in Second Word case RI_MOVEI: - if (*tok != '#') + if (*tok.u32 != '#') return MalformedOpcode(0x03); - tok++; + tok.u32++; + riscImmTokenSeen = 1; + + // Check for equated register after # and return error if so + if (*tok.u32 == SYMBOL) + { + sy = lookup(string[tok.u32[1]], LABEL, 0); + + if (sy && (sy->sattre & EQUATEDREG)) + return error("equated register in 1st operand of MOVEI instruction"); + } - if (expr(r_expr, &eval, &eattr, &esym) != OK) + if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x04); if (lastOpcode == RI_JUMP || lastOpcode == RI_JR) @@ -338,7 +363,7 @@ int GenerateRISCCode(int state) warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE"); } else - warn("MOVEI following JUMP"); + warn("MOVEI immediately follows JUMP"); } if ((challoc - ch_size) < 4) @@ -346,19 +371,20 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr); + AddFixup(FU_LONG | FU_MOVEI, sloc + 2, (TOKENPTR)r_expr); eval = 0; } else { if (eattr & TDB) //{ -//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); - rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL); +//printf("RISCASM: Doing MarkRelocatable for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); + MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL); //} } - val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000); +// val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000); + val = WORDSWAP32(eval); CHECK_COMMA; reg2 = GetRegister(FU_REGTWO); at_eol(); @@ -368,11 +394,11 @@ int GenerateRISCCode(int state) // PC,Rd or Rs,Rd case RI_MOVE: - if (*tok == KW_PC) + if (*tok.u32 == KW_PC) { parm = 51; reg1 = 0; - tok++; + tok.u32++; } else { @@ -387,22 +413,28 @@ int GenerateRISCCode(int state) break; // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59 - case RI_LOAD: + case RI_LOAD: indexed = 0; parm = 41; - if (*tok != '(') + if (*tok.u32 != '(') return MalformedOpcode(0x05); - tok++; + tok.u32++; - if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) - indexed = (*tok - KW_R0); + if ((*(tok.u32 + 1) == '+') || (*(tok.u32 + 1) == '-')) { + // Trying to make indexed call + if ((*tok.u32 == KW_R14 || *tok.u32 == KW_R15)) { + indexed = (*tok.u32 - KW_R0); + } else { + return IllegalIndexedRegister(*tok.u32); + } + } - if (*tok == SYMBOL) + if (*tok.u32 == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); - sy = lookup(string[tok[1]], LABEL, 0); +// sy = lookup((char *)tok.u32[1], LABEL, 0); + sy = lookup(string[tok.u32[1]], LABEL, 0); if (!sy) { @@ -412,11 +444,13 @@ int GenerateRISCCode(int state) if (sy->sattre & EQUATEDREG) { - if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) - && (*(tok + 2) != ')')) - { - indexed = (sy->svalue & 0x1F); - tok++; + if ((*(tok.u32 + 2) == '+') || (*(tok.u32 + 2) == '-')) { + if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) { + indexed = (sy->svalue & 0x1F); + tok.u32++; + } else { + return IllegalIndexedRegisterEqur(sy); + } } } } @@ -429,20 +463,20 @@ int GenerateRISCCode(int state) { reg1 = indexed; indexed = 0; - tok++; + tok.u32++; - if (*tok == '+') + if (*tok.u32 == '+') { parm = (WORD)(reg1 - 14 + 58); - tok++; + tok.u32++; - if (*tok >= KW_R0 && *tok <= KW_R31) + if (*tok.u32 >= KW_R0 && *tok.u32 <= KW_R31) indexed = 1; - if (*tok == SYMBOL) + if (*tok.u32 == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); - sy = lookup(string[tok[1]], LABEL, 0); +// sy = lookup((char *)tok.u32[1], LABEL, 0); + sy = lookup(string[tok.u32[1]], LABEL, 0); if (!sy) { @@ -460,19 +494,16 @@ int GenerateRISCCode(int state) } else { - if (expr(r_expr, &eval, &eattr, &esym) != OK) + if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x06); if ((challoc - ch_size) < 4) chcheck(4L); if (!(eattr & DEFINED)) - { - error("constant expected after '+'"); - return ERROR; - } + return error("constant expected after '+'"); - reg1 = eval; + reg1 = (int)eval; if (reg1 == 0) { @@ -483,10 +514,7 @@ int GenerateRISCCode(int state) else { if (reg1 < 1 || reg1 > 32) - { - error("constant in LOAD out of range"); - return ERROR; - } + return error("constant in LOAD out of range"); if (reg1 == 32) reg1 = 0; @@ -501,10 +529,10 @@ int GenerateRISCCode(int state) } } - if (*tok != ')') + if (*tok.u32 != ')') return MalformedOpcode(0x07); - tok++; + tok.u32++; CHECK_COMMA; reg2 = GetRegister(FU_REGTWO); at_eol(); @@ -512,24 +540,23 @@ int GenerateRISCCode(int state) break; // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61 - case RI_STORE: + case RI_STORE: parm = 47; reg1 = GetRegister(FU_REGONE); CHECK_COMMA; - if (*tok != '(') + if (*tok.u32 != '(') return MalformedOpcode(0x08); - tok++; + tok.u32++; indexed = 0; - if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) - indexed = (*tok - KW_R0); + if ((*tok.u32 == KW_R14 || *tok.u32 == KW_R15) && (*(tok.u32 + 1) != ')')) + indexed = (*tok.u32 - KW_R0); - if (*tok == SYMBOL) + if (*tok.u32 == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); - sy = lookup(string[tok[1]], LABEL, 0); + sy = lookup(string[tok.u32[1]], LABEL, 0); if (!sy) { @@ -537,13 +564,13 @@ int GenerateRISCCode(int state) return ERROR; } - if (sy->sattre & EQUATEDREG) + if (sy->sattre & EQUATEDREG) { if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) - && (*(tok + 2) != ')')) + && (*(tok.u32 + 2) != ')')) { indexed = (sy->svalue & 0x1F); - tok++; + tok.u32++; } } } @@ -556,20 +583,19 @@ int GenerateRISCCode(int state) { reg2 = indexed; indexed = 0; - tok++; + tok.u32++; - if (*tok == '+') + if (*tok.u32 == '+') { parm = (WORD)(reg2 - 14 + 60); - tok++; + tok.u32++; - if (*tok >= KW_R0 && *tok <= KW_R31) + if (*tok.u32 >= KW_R0 && *tok.u32 <= KW_R31) indexed = 1; - if (*tok == SYMBOL) + if (*tok.u32 == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); - sy = lookup(string[tok[1]], LABEL, 0); + sy = lookup(string[tok.u32[1]], LABEL, 0); if (!sy) { @@ -587,7 +613,7 @@ int GenerateRISCCode(int state) } else { - if (expr(r_expr, &eval, &eattr, &esym) != OK) + if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x09); if ((challoc - ch_size) < 4) @@ -595,12 +621,12 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup(FU_WORD | FU_REGTWO, sloc, r_expr); + AddFixup(FU_WORD | FU_REGTWO, sloc, (TOKENPTR)r_expr); reg2 = 0; } else { - reg2 = eval; + reg2 = (int)eval; if (reg2 == 0) { @@ -611,10 +637,7 @@ int GenerateRISCCode(int state) else { if (reg2 < 1 || reg2 > 32) - { - error("constant in STORE out of range"); - return ERROR; - } + return error("constant in STORE out of range"); if (reg2 == 32) reg2 = 0; @@ -630,26 +653,26 @@ int GenerateRISCCode(int state) } } - if (*tok != ')') + if (*tok.u32 != ')') return MalformedOpcode(0x0A); - tok++; + tok.u32++; at_eol(); BuildRISCIntructionWord(parm, reg2, reg1); break; // LOADB/LOADP/LOADW (Rn),Rn - case RI_LOADN: - if (*tok != '(') + case RI_LOADN: + if (*tok.u32 != '(') return MalformedOpcode(0x0B); - tok++; + tok.u32++; reg1 = GetRegister(FU_REGONE); - if (*tok != ')') + if (*tok.u32 != ')') return MalformedOpcode(0x0C); - tok++; + tok.u32++; CHECK_COMMA; reg2 = GetRegister(FU_REGTWO); at_eol(); @@ -657,20 +680,20 @@ int GenerateRISCCode(int state) break; // STOREB/STOREP/STOREW Rn,(Rn) - case RI_STOREN: + case RI_STOREN: reg1 = GetRegister(FU_REGONE); CHECK_COMMA; - if (*tok != '(') + if (*tok.u32 != '(') return MalformedOpcode(0x0D); - tok++; + tok.u32++; reg2 = GetRegister(FU_REGTWO); - if (*tok != ')') + if (*tok.u32 != ')') return MalformedOpcode(0x0E); - tok++; + tok.u32++; at_eol(); BuildRISCIntructionWord(parm, reg2, reg1); break; @@ -684,7 +707,7 @@ int GenerateRISCCode(int state) // the JR or JUMP should default to 0, Jump Always commaFound = 0; - for(t=tok; *t!=EOL; t++) + for(t=tok.u32; *t!=EOL; t++) { if (*t == ',') { @@ -695,19 +718,20 @@ int GenerateRISCCode(int state) if (commaFound) { - if (*tok == CONST) + if (*tok.u32 == CONST) { // CC using a constant number - tok++; - val = *tok; - tok++; + tok.u32++; + uint64_t *tok64 = (uint64_t *)tok.u32; + val = (int)*tok64++; + tok.u32 = (uint32_t *)tok64; CHECK_COMMA; } - else if (*tok == SYMBOL) + else if (*tok.u32 == SYMBOL) { val = 99; -// strcpy(scratch, (char *)tok[1]); - strcpy(scratch, string[tok[1]]); +// strcpy(scratch, (char *)tok.u32[1]); + strcpy(scratch, string[tok.u32[1]]); strtoupper(scratch); for(i=0; isattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC)) - { val = ccsym->svalue; - } else - { - error("unknown condition code"); - return ERROR; - } + return error("unknown condition code"); } - tok += 2; + tok.u32 += 2; CHECK_COMMA; } - else if (*tok == '(') + else if (*tok.u32 == '(') { // Set CC to "Jump Always" val = 0; @@ -753,10 +772,7 @@ int GenerateRISCCode(int state) } if (val < 0 || val > 31) - { - error("condition constant out of range"); - return ERROR; - } + return error("condition constant out of range"); // Store condition code reg1 = val; @@ -764,7 +780,7 @@ int GenerateRISCCode(int state) if (type == RI_JR) { // JR cc,n - if (expr(r_expr, &eval, &eattr, &esym) != OK) + if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x0F); if ((challoc - ch_size) < 4) @@ -772,7 +788,7 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup(FU_WORD | FU_JR, sloc, r_expr); + AddFixup(FU_WORD | FU_JR, sloc, (TOKENPTR)r_expr); reg2 = 0; } else @@ -780,7 +796,7 @@ int GenerateRISCCode(int state) reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2; if ((reg2 < -16) || (reg2 > 15)) - error("PC relative overflow"); + error("PC relative overflow (outside of -16 to 15)"); } BuildRISCIntructionWord(parm, reg2, reg1); @@ -788,16 +804,16 @@ int GenerateRISCCode(int state) else { // JUMP cc, (Rn) - if (*tok != '(') + if (*tok.u32 != '(') return MalformedOpcode(0x10); - tok++; + tok.u32++; reg2 = GetRegister(FU_REGTWO); - if (*tok != ')') + if (*tok.u32 != ')') return MalformedOpcode(0x11); - tok++; + tok.u32++; at_eol(); BuildRISCIntructionWord(parm, reg2, reg1); } @@ -806,8 +822,7 @@ int GenerateRISCCode(int state) // Should never get here :-D default: - error("Unknown risc opcode type"); - return ERROR; + return error("Unknown RISC opcode type"); } lastOpcode = type;