X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=riscasm.c;h=78bae9c290a3f506088050a3644de1546e4fe142;hp=b4a06d7559d064f5bde2d3ac874a52d30a3fc610;hb=e86444a037c470d010786006fbcaa7d6b56effdb;hpb=3f2bccb78ab4cd59654d521c8aedfe5512ee6608

diff --git a/riscasm.c b/riscasm.c
index b4a06d7..78bae9c 100644
--- a/riscasm.c
+++ b/riscasm.c
@@ -101,8 +101,8 @@ const struct opcoderecord roptbl[] = {
 	{ MR_NORMI,   RI_TWO,    56 },
 	{ MR_NOP,     RI_NONE,   57 },
 	{ MR_SAT24,   RI_ONE,    62 },
-	{ MR_UNPACK,  RI_ONE,    63 + GPUONLY },
-	{ MR_PACK,    RI_ONE,    63 + GPUONLY },
+	{ MR_UNPACK,  RI_ONE,    63 + GPUONLY | (0 << 6) },
+	{ MR_PACK,    RI_ONE,    63 + GPUONLY | (1 << 6) },
 	{ MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
 	{ MR_MOVE,    RI_MOVE,   0 },
 	{ MR_LOAD,    RI_LOAD,   0 },
@@ -140,13 +140,13 @@ void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
 	// Check for absolute address setting
 	if (!orgwarning && !orgactive)
 	{
-//		warn("GPU/DSP code outside of absolute section");
 		warn("RISC code generated with no origin defined");
 		orgwarning = 1;
 	}
 
 	int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
 	D_word(value);
+//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
 }
 
 
@@ -224,7 +224,8 @@ int GenerateRISCCode(int state)
 		break;
 
 	// Single operand instructions (Rd)
-	// ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK
+	// ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
+	// UNPACK
 	case RI_ONE:
 		reg2 = GetRegister(FU_REGTWO);
 		at_eol();
@@ -232,8 +233,8 @@ int GenerateRISCCode(int state)
 		break;   
 
 	// Two operand instructions (Rs,Rd)
-	// ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT, 
-	// MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
+	// ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
+	// MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
 	case RI_TWO:                      
 		if (parm == 37)
 			altbankok = 1;                      // MOVEFA
@@ -258,7 +259,8 @@ int GenerateRISCCode(int state)
 	case RI_NUM_31:
 
 	// Numeric operand (n,Rd) where n = 1..32
-	// ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ
+	// ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
+	// RORQ
 	case RI_NUM_32:
 		switch (type)
 		{
@@ -321,6 +323,15 @@ int GenerateRISCCode(int state)
 		tok++;
 		riscImmTokenSeen = 1;
 
+		// Check for equated register after # and return error if so
+		if (*tok == SYMBOL)
+		{
+			sy = lookup(string[tok[1]], LABEL, 0);
+
+			if (sy && (sy->sattre & EQUATEDREG))
+				return error("equated register in 1st operand of MOVEI instruction");
+		}
+
 		if (expr(r_expr, &eval, &eattr, &esym) != OK)
 			return MalformedOpcode(0x04);
 
@@ -348,7 +359,7 @@ int GenerateRISCCode(int state)
 		{
 			if (eattr & TDB)
 //{
-//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
+//printf("RISCASM: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
 				rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
 //}
 		}