X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=riscasm.c;h=78bae9c290a3f506088050a3644de1546e4fe142;hp=2754600b2dabdcee7561eae01cb717e64c6cc4aa;hb=bb77eaee83ffa56a181fa1b92f4ea7de248a3af4;hpb=9df4696c6d38b7908dd83f95509fc14f2f7c799c diff --git a/riscasm.c b/riscasm.c index 2754600..78bae9c 100644 --- a/riscasm.c +++ b/riscasm.c @@ -3,7 +3,7 @@ // RISCA.C - GPU/DSP Assembler // Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986 -// Source Utilised with the Kind Permission of Landon Dyer +// Source utilised with the kind permission of Landon Dyer // #include "riscasm.h" @@ -15,11 +15,11 @@ #include "mark.h" #include "amode.h" -#define DEF_MR // Declar keyword values -#include "risckw.h" // Incl generated risc keywords +#define DEF_MR // Declare keyword values +#include "risckw.h" // Incl. generated risc keywords #define DEF_KW // Declare keyword values -#include "kwtab.h" // Incl generated keyword tables & defs +#include "kwtab.h" // Incl. generated keyword tables & defs unsigned altbankok = 0; // Ok to use alternate register bank @@ -27,23 +27,24 @@ unsigned orgactive = 0; // RISC org directive active unsigned orgaddr = 0; // Org'd address unsigned orgwarning = 0; // Has an ORG warning been issued int lastOpcode = -1; // Last RISC opcode assembled +uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen -char reg_err[] = "missing register R0...R31"; +const char reg_err[] = "missing register R0...R31"; -// Jaguar Jump Condition Names -char condname[MAXINTERNCC][5] = { +// Jaguar jump condition names +const char condname[MAXINTERNCC][5] = { "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ", "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO", "PL", "MI", "F" }; -// Jaguar Jump Condition Numbers -char condnumber[] = { +// Jaguar jump condition numbers +const char condnumber[] = { 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26, 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31 }; -struct opcoderecord roptbl[] = { +const struct opcoderecord roptbl[] = { { MR_ADD, RI_TWO, 0 }, { MR_ADDC, RI_TWO, 1 }, { MR_ADDQ, RI_NUM_32, 2 }, @@ -100,8 +101,8 @@ struct opcoderecord roptbl[] = { { MR_NORMI, RI_TWO, 56 }, { MR_NOP, RI_NONE, 57 }, { MR_SAT24, RI_ONE, 62 }, - { MR_UNPACK, RI_ONE, 63 + GPUONLY }, - { MR_PACK, RI_ONE, 63 + GPUONLY }, + { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) }, + { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) }, { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY }, { MR_MOVE, RI_MOVE, 0 }, { MR_LOAD, RI_LOAD, 0 }, @@ -110,7 +111,7 @@ struct opcoderecord roptbl[] = { // -// Convert a String to Uppercase +// Convert a string to uppercase // void strtoupper(char * s) { @@ -127,30 +128,30 @@ static inline int MalformedOpcode(int signal) { char buf[16]; sprintf(buf, "%02X", signal); - errors("Malformed opcode [internal $%s]", buf); - return ERROR; + return errors("Malformed opcode [internal $%s]", buf); } // -// Build RISC Instruction Word +// Build RISC instruction word // void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2) { // Check for absolute address setting if (!orgwarning && !orgactive) { - warn("GPU/DSP code outside of absolute section"); + warn("RISC code generated with no origin defined"); orgwarning = 1; } int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F); D_word(value); +//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value); } // -// Get a RISC Register +// Get a RISC register // int GetRegister(WORD rattr) { @@ -161,8 +162,6 @@ int GetRegister(WORD rattr) // Evaluate what's in the global "tok" buffer if (expr(r_expr, &eval, &eattr, &esym) != OK) - // Hmm, the evaluator should report the error to us... -// return MalformedOpcode(0x00); return ERROR; if ((challoc - ch_size) < 4) @@ -170,7 +169,7 @@ int GetRegister(WORD rattr) if (!(eattr & DEFINED)) { - fixup((WORD)(FU_WORD | rattr), sloc, r_expr); + AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr); return 0; } @@ -179,13 +178,12 @@ int GetRegister(WORD rattr) return eval; // Otherwise, it's out of range & we flag an error - error(reg_err); - return ERROR; + return error(reg_err); } // -// Do RISC Code Generation +// Do RISC code generation // int GenerateRISCCode(int state) { @@ -208,15 +206,13 @@ int GenerateRISCCode(int state) // Get opcode parameter and type unsigned short parm = (WORD)(roptbl[state - 3000].parm); unsigned type = roptbl[state - 3000].typ; + riscImmTokenSeen = 0; // Set to "token not seen yet" // Detect whether the opcode parmeter passed determines that the opcode is // specific to only one of the RISC processors and ensure it is legal in // the current code section. If not then show error and return. if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu)) - { - error("Opcode is not valid in this code section"); - return ERROR; - } + return error("Opcode is not valid in this code section"); // Process RISC opcode switch (type) @@ -228,7 +224,8 @@ int GenerateRISCCode(int state) break; // Single operand instructions (Rd) - // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK + // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, + // UNPACK case RI_ONE: reg2 = GetRegister(FU_REGTWO); at_eol(); @@ -236,8 +233,8 @@ int GenerateRISCCode(int state) break; // Two operand instructions (Rs,Rd) - // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT, - // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR + // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, + // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR case RI_TWO: if (parm == 37) altbankok = 1; // MOVEFA @@ -262,7 +259,8 @@ int GenerateRISCCode(int state) case RI_NUM_31: // Numeric operand (n,Rd) where n = 1..32 - // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ + // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, + // RORQ case RI_NUM_32: switch (type) { @@ -285,6 +283,7 @@ int GenerateRISCCode(int state) return MalformedOpcode(0x01); tok++; + riscImmTokenSeen = 1; if (expr(r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x02); @@ -294,16 +293,13 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup((WORD)(FU_WORD | attrflg), sloc, r_expr); + AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr); reg1 = 0; } else { if ((int)eval < reg1 || (int)eval > reg2) - { - error("constant out of range"); - return ERROR; - } + return error("constant out of range"); if (parm & SUB32) reg1 = 32 - eval; @@ -325,6 +321,16 @@ int GenerateRISCCode(int state) return MalformedOpcode(0x03); tok++; + riscImmTokenSeen = 1; + + // Check for equated register after # and return error if so + if (*tok == SYMBOL) + { + sy = lookup(string[tok[1]], LABEL, 0); + + if (sy && (sy->sattre & EQUATEDREG)) + return error("equated register in 1st operand of MOVEI instruction"); + } if (expr(r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x04); @@ -346,14 +352,14 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr); + AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr); eval = 0; } else { if (eattr & TDB) //{ -//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); +//printf("RISCASM: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL); //} } @@ -467,10 +473,7 @@ int GenerateRISCCode(int state) chcheck(4L); if (!(eattr & DEFINED)) - { - error("constant expected after '+'"); - return ERROR; - } + return error("constant expected after '+'"); reg1 = eval; @@ -483,10 +486,7 @@ int GenerateRISCCode(int state) else { if (reg1 < 1 || reg1 > 32) - { - error("constant in LOAD out of range"); - return ERROR; - } + return error("constant in LOAD out of range"); if (reg1 == 32) reg1 = 0; @@ -528,7 +528,6 @@ int GenerateRISCCode(int state) if (*tok == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); sy = lookup(string[tok[1]], LABEL, 0); if (!sy) @@ -568,7 +567,6 @@ int GenerateRISCCode(int state) if (*tok == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); sy = lookup(string[tok[1]], LABEL, 0); if (!sy) @@ -595,7 +593,7 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup(FU_WORD | FU_REGTWO, sloc, r_expr); + AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr); reg2 = 0; } else @@ -611,10 +609,7 @@ int GenerateRISCCode(int state) else { if (reg2 < 1 || reg2 > 32) - { - error("constant in STORE out of range"); - return ERROR; - } + return error("constant in STORE out of range"); if (reg2 == 32) reg2 = 0; @@ -731,10 +726,7 @@ int GenerateRISCCode(int state) val = ccsym->svalue; } else - { - error("unknown condition code"); - return ERROR; - } + return error("unknown condition code"); } tok += 2; @@ -753,10 +745,7 @@ int GenerateRISCCode(int state) } if (val < 0 || val > 31) - { - error("condition constant out of range"); - return ERROR; - } + return error("condition constant out of range"); // Store condition code reg1 = val; @@ -772,7 +761,7 @@ int GenerateRISCCode(int state) if (!(eattr & DEFINED)) { - fixup(FU_WORD | FU_JR, sloc, r_expr); + AddFixup(FU_WORD | FU_JR, sloc, r_expr); reg2 = 0; } else @@ -806,8 +795,7 @@ int GenerateRISCCode(int state) // Should never get here :-D default: - error("Unknown risc opcode type"); - return ERROR; + return error("Unknown RISC opcode type"); } lastOpcode = type;