X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=riscasm.c;h=2c291ffe9daad4b687f938dc35509312c044771b;hp=fbc8f81cf605ff2a14178c7754b9c64bac94718b;hb=60f204cb9e3905100da0d89f14bb40db764acd9e;hpb=f6e6a55c4cdaf0dffa0897792dc5926c7b173a23 diff --git a/riscasm.c b/riscasm.c index fbc8f81..2c291ff 100644 --- a/riscasm.c +++ b/riscasm.c @@ -1,9 +1,9 @@ // // RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System // RISCA.C - GPU/DSP Assembler -// Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends +// Copyright (C) 199x Landon Dyer, 2011 - 2017 Reboot and Friends // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986 -// Source Utilised with the Kind Permission of Landon Dyer +// Source utilised with the kind permission of Landon Dyer // #include "riscasm.h" @@ -15,34 +15,36 @@ #include "mark.h" #include "amode.h" -#define DEF_MR // Declar keyword values -#include "risckw.h" // Incl generated risc keywords +#define DEF_MR // Declare keyword values +#include "risckw.h" // Incl. generated risc keywords -#define DEF_KW // Declare keyword values -#include "kwtab.h" // Incl generated keyword tables & defs +#define DEF_KW // Declare keyword values +#include "kwtab.h" // Incl. generated keyword tables & defs unsigned altbankok = 0; // Ok to use alternate register bank unsigned orgactive = 0; // RISC org directive active unsigned orgaddr = 0; // Org'd address unsigned orgwarning = 0; // Has an ORG warning been issued +int lastOpcode = -1; // Last RISC opcode assembled +uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen -char reg_err[] = "missing register R0...R31"; +const char reg_err[] = "missing register R0...R31"; -// Jaguar Jump Condition Names -char condname[MAXINTERNCC][5] = { +// Jaguar jump condition names +const char condname[MAXINTERNCC][5] = { "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ", - "N", "N_NZ", "N_Z ", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO", + "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO", "PL", "MI", "F" }; -// Jaguar Jump Condition Numbers -char condnumber[] = { +// Jaguar jump condition numbers +const char condnumber[] = { 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26, 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31 }; -struct opcoderecord roptbl[] = { +const struct opcoderecord roptbl[] = { { MR_ADD, RI_TWO, 0 }, { MR_ADDC, RI_TWO, 1 }, { MR_ADDQ, RI_NUM_32, 2 }, @@ -99,8 +101,8 @@ struct opcoderecord roptbl[] = { { MR_NORMI, RI_TWO, 56 }, { MR_NOP, RI_NONE, 57 }, { MR_SAT24, RI_ONE, 62 }, - { MR_UNPACK, RI_ONE, 63 + GPUONLY }, - { MR_PACK, RI_ONE, 63 + GPUONLY }, + { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) }, + { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) }, { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY }, { MR_MOVE, RI_MOVE, 0 }, { MR_LOAD, RI_LOAD, 0 }, @@ -109,20 +111,12 @@ struct opcoderecord roptbl[] = { // -// Convert a String to Uppercase +// Convert a string to uppercase // void strtoupper(char * s) { -#if 0 - while (*s) - { - *s = (char)(toupper(*s)); - s++; - } -#else while (*s) *s++ &= 0xDF; -#endif } @@ -130,32 +124,60 @@ void strtoupper(char * s) // Function to return "malformed expression" error // This is done mainly to remove a bunch of GOTO statements in the parser // -static inline int MalformedOpcode(void) +static inline int MalformedOpcode(int signal) +{ + char buf[16]; + sprintf(buf, "%02X", signal); + return errors("Malformed opcode [internal $%s]", buf); +} + +// +// Function to return "Illegal Indexed Register" error +// Anyone trying to index something other than R14 or R15 +// +static inline int IllegalIndexedRegister(int reg) { - error("Malformed opcode"); - return ERROR; + char buf[16]; + sprintf(buf, "%d", reg - KW_R0); + return errors("Attempted index reference with non-indexable register (r%s)", buf); } +// +// Function to return "Illegal Indexed Register" error for EQUR scenarios +// Trying to use register value within EQUR that isn't 14 or 15 +// +static inline int IllegalIndexedRegisterEqur(SYM *sy) +{ + //char buf[160]; + char *buf = NULL; + buf = (char *)malloc((strlen(sy->sname) + 7) * sizeof(char)); + if (NULL != buf) { + sprintf(buf, "%s = r%d",sy->sname, sy->svalue); + return errors("Attempted index reference with non-indexable register within EQUR (%s)", buf); + } + return errors("Unable to allocate memory! (IllegalIndexRegisterEqur)", "OOPS"); +} // -// Build RISC Instruction Word +// Build RISC instruction word // void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2) { // Check for absolute address setting if (!orgwarning && !orgactive) { - warn("GPU/DSP code outside of absolute section"); + warn("RISC code generated with no origin defined"); orgwarning = 1; } int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F); D_word(value); +//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value); } // -// Get a RISC Register +// Get a RISC register // int GetRegister(WORD rattr) { @@ -166,23 +188,14 @@ int GetRegister(WORD rattr) // Evaluate what's in the global "tok" buffer if (expr(r_expr, &eval, &eattr, &esym) != OK) - return MalformedOpcode(); + return ERROR; if ((challoc - ch_size) < 4) chcheck(4L); - // See if this symbol has been defined, then undefined: -//does nothing -//segfaults now (esym == NULL?) -/* if (esym->sattre & UNDEF_EQUR) - { - error("undefined register"); - return ERROR; - }*/ - if (!(eattr & DEFINED)) { - fixup((WORD)(FU_WORD | rattr), sloc, r_expr); + AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr); return 0; } @@ -191,13 +204,12 @@ int GetRegister(WORD rattr) return eval; // Otherwise, it's out of range & we flag an error - error(reg_err); - return ERROR; + return error(reg_err); } // -// Do RISC Code Generation +// Do RISC code generation // int GenerateRISCCode(int state) { @@ -220,42 +232,41 @@ int GenerateRISCCode(int state) // Get opcode parameter and type unsigned short parm = (WORD)(roptbl[state - 3000].parm); unsigned type = roptbl[state - 3000].typ; + riscImmTokenSeen = 0; // Set to "token not seen yet" // Detect whether the opcode parmeter passed determines that the opcode is // specific to only one of the RISC processors and ensure it is legal in // the current code section. If not then show error and return. if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu)) - { - error("Opcode is not valid in this code section"); - return ERROR; - } + return error("Opcode is not valid in this code section"); // Process RISC opcode switch (type) { // No operand instructions - // NOP - case RI_NONE: + // NOP (57) + case RI_NONE: BuildRISCIntructionWord(parm, 0, 0); break; // Single operand instructions (Rd) - // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK + // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, + // UNPACK case RI_ONE: reg2 = GetRegister(FU_REGTWO); at_eol(); BuildRISCIntructionWord(parm, parm >> 6, reg2); - break; + break; // Two operand instructions (Rs,Rd) - // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT, - // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR - case RI_TWO: + // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, + // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR + case RI_TWO: if (parm == 37) altbankok = 1; // MOVEFA reg1 = GetRegister(FU_REGONE); - CHECK_COMMA; + CHECK_COMMA; if (parm == 36) altbankok = 1; // MOVETA @@ -274,7 +285,8 @@ int GenerateRISCCode(int state) case RI_NUM_31: // Numeric operand (n,Rd) where n = 1..32 - // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ + // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, + // RORQ case RI_NUM_32: switch (type) { @@ -294,31 +306,29 @@ int GenerateRISCCode(int state) attrflg |= FU_SUB32; if (*tok != '#') - return MalformedOpcode(); + return MalformedOpcode(0x01); tok++; + riscImmTokenSeen = 1; if (expr(r_expr, &eval, &eattr, &esym) != OK) - return MalformedOpcode(); + return MalformedOpcode(0x02); if ((challoc - ch_size) < 4) chcheck(4L); if (!(eattr & DEFINED)) { - fixup((WORD)(FU_WORD | attrflg), sloc, r_expr); + AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr); reg1 = 0; } else { if ((int)eval < reg1 || (int)eval > reg2) - { - error("constant out of range"); - return ERROR; - } + return error("constant out of range"); - if (parm & SUB32) - reg1 = 32 - eval; + if (parm & SUB32) + reg1 = 32 - eval; else if (type == RI_NUM_32) reg1 = (reg1 == 32 ? 0 : eval); else @@ -334,31 +344,54 @@ int GenerateRISCCode(int state) // Move Immediate--n,Rn--n in Second Word case RI_MOVEI: if (*tok != '#') - return MalformedOpcode(); + return MalformedOpcode(0x03); tok++; + riscImmTokenSeen = 1; + + // Check for equated register after # and return error if so + if (*tok == SYMBOL) + { + sy = lookup(string[tok[1]], LABEL, 0); + + if (sy && (sy->sattre & EQUATEDREG)) + return error("equated register in 1st operand of MOVEI instruction"); + } if (expr(r_expr, &eval, &eattr, &esym) != OK) - return MalformedOpcode(); + return MalformedOpcode(0x04); + + if (lastOpcode == RI_JUMP || lastOpcode == RI_JR) + { + if (legacy_flag) + { + // User doesn't care, emit a NOP to fix + BuildRISCIntructionWord(57, 0, 0); + warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE"); + } + else + warn("MOVEI immediately follows JUMP"); + } if ((challoc - ch_size) < 4) chcheck(4L); if (!(eattr & DEFINED)) { - fixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr); + AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr); eval = 0; } else { if (eattr & TDB) //{ -//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); - rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL); +//printf("RISCASM: Doing MarkRelocatable for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); + MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL); //} } - val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000); +// val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000); + val = WORDSWAP32(eval); CHECK_COMMA; reg2 = GetRegister(FU_REGTWO); at_eol(); @@ -387,17 +420,23 @@ int GenerateRISCCode(int state) break; // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59 - case RI_LOAD: + case RI_LOAD: indexed = 0; parm = 41; if (*tok != '(') - return MalformedOpcode(); + return MalformedOpcode(0x05); tok++; - if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) - indexed = (*tok - KW_R0); + if ((*(tok + 1) == '+') || (*(tok + 1) == '-')) { + // Trying to make indexed call + if ((*tok == KW_R14 || *tok == KW_R15)) { + indexed = (*tok - KW_R0); + } else { + return IllegalIndexedRegister(*tok); + } + } if (*tok == SYMBOL) { @@ -412,11 +451,13 @@ int GenerateRISCCode(int state) if (sy->sattre & EQUATEDREG) { - if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) - && (*(tok + 2) != ')')) - { - indexed = (sy->svalue & 0x1F); - tok++; + if ((*(tok + 2) == '+') || (*(tok + 2) == '-')) { + if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) { + indexed = (sy->svalue & 0x1F); + tok++; + } else { + return IllegalIndexedRegisterEqur(sy); + } } } } @@ -461,16 +502,13 @@ int GenerateRISCCode(int state) else { if (expr(r_expr, &eval, &eattr, &esym) != OK) - return MalformedOpcode(); + return MalformedOpcode(0x06); if ((challoc - ch_size) < 4) chcheck(4L); if (!(eattr & DEFINED)) - { - error("constant expected"); - return ERROR; - } + return error("constant expected after '+'"); reg1 = eval; @@ -478,15 +516,12 @@ int GenerateRISCCode(int state) { reg1 = 14 + (parm - 58); parm = 41; - warn("NULL offset removed"); + warn("NULL offset in LOAD ignored"); } else { if (reg1 < 1 || reg1 > 32) - { - error("constant out of range"); - return ERROR; - } + return error("constant in LOAD out of range"); if (reg1 == 32) reg1 = 0; @@ -502,7 +537,7 @@ int GenerateRISCCode(int state) } if (*tok != ')') - return MalformedOpcode(); + return MalformedOpcode(0x07); tok++; CHECK_COMMA; @@ -512,23 +547,22 @@ int GenerateRISCCode(int state) break; // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61 - case RI_STORE: + case RI_STORE: parm = 47; reg1 = GetRegister(FU_REGONE); CHECK_COMMA; if (*tok != '(') - return MalformedOpcode(); + return MalformedOpcode(0x08); tok++; indexed = 0; - if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) + if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) indexed = (*tok - KW_R0); if (*tok == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); sy = lookup(string[tok[1]], LABEL, 0); if (!sy) @@ -537,7 +571,7 @@ int GenerateRISCCode(int state) return ERROR; } - if (sy->sattre & EQUATEDREG) + if (sy->sattre & EQUATEDREG) { if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) && (*(tok + 2) != ')')) @@ -568,7 +602,6 @@ int GenerateRISCCode(int state) if (*tok == SYMBOL) { -// sy = lookup((char *)tok[1], LABEL, 0); sy = lookup(string[tok[1]], LABEL, 0); if (!sy) @@ -588,14 +621,14 @@ int GenerateRISCCode(int state) else { if (expr(r_expr, &eval, &eattr, &esym) != OK) - return MalformedOpcode(); + return MalformedOpcode(0x09); if ((challoc - ch_size) < 4) chcheck(4L); if (!(eattr & DEFINED)) { - fixup(FU_WORD | FU_REGTWO, sloc, r_expr); + AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr); reg2 = 0; } else @@ -606,15 +639,12 @@ int GenerateRISCCode(int state) { reg2 = 14 + (parm - 60); parm = 47; - warn("NULL offset removed"); + warn("NULL offset in STORE ignored"); } else { if (reg2 < 1 || reg2 > 32) - { - error("constant out of range"); - return ERROR; - } + return error("constant in STORE out of range"); if (reg2 == 32) reg2 = 0; @@ -631,7 +661,7 @@ int GenerateRISCCode(int state) } if (*tok != ')') - return MalformedOpcode(); + return MalformedOpcode(0x0A); tok++; at_eol(); @@ -639,15 +669,15 @@ int GenerateRISCCode(int state) break; // LOADB/LOADP/LOADW (Rn),Rn - case RI_LOADN: + case RI_LOADN: if (*tok != '(') - return MalformedOpcode(); + return MalformedOpcode(0x0B); tok++; reg1 = GetRegister(FU_REGONE); if (*tok != ')') - return MalformedOpcode(); + return MalformedOpcode(0x0C); tok++; CHECK_COMMA; @@ -657,18 +687,18 @@ int GenerateRISCCode(int state) break; // STOREB/STOREP/STOREW Rn,(Rn) - case RI_STOREN: + case RI_STOREN: reg1 = GetRegister(FU_REGONE); CHECK_COMMA; if (*tok != '(') - return MalformedOpcode(); + return MalformedOpcode(0x0D); tok++; reg2 = GetRegister(FU_REGTWO); if (*tok != ')') - return MalformedOpcode(); + return MalformedOpcode(0x0E); tok++; at_eol(); @@ -731,10 +761,7 @@ int GenerateRISCCode(int state) val = ccsym->svalue; } else - { - error("unknown condition code"); - return ERROR; - } + return error("unknown condition code"); } tok += 2; @@ -753,10 +780,7 @@ int GenerateRISCCode(int state) } if (val < 0 || val > 31) - { - error("condition constant out of range"); - return ERROR; - } + return error("condition constant out of range"); // Store condition code reg1 = val; @@ -765,14 +789,14 @@ int GenerateRISCCode(int state) { // JR cc,n if (expr(r_expr, &eval, &eattr, &esym) != OK) - return MalformedOpcode(); + return MalformedOpcode(0x0F); if ((challoc - ch_size) < 4) chcheck(4L); if (!(eattr & DEFINED)) { - fixup(FU_WORD | FU_JR, sloc, r_expr); + AddFixup(FU_WORD | FU_JR, sloc, r_expr); reg2 = 0; } else @@ -789,13 +813,13 @@ int GenerateRISCCode(int state) { // JUMP cc, (Rn) if (*tok != '(') - return MalformedOpcode(); + return MalformedOpcode(0x10); tok++; reg2 = GetRegister(FU_REGTWO); if (*tok != ')') - return MalformedOpcode(); + return MalformedOpcode(0x11); tok++; at_eol(); @@ -806,10 +830,10 @@ int GenerateRISCCode(int state) // Should never get here :-D default: - error("Unknown risc opcode type"); - return ERROR; + return error("Unknown RISC opcode type"); } + lastOpcode = type; return 0; }