X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=riscasm.c;h=2c291ffe9daad4b687f938dc35509312c044771b;hp=52925558f9faefb5412407ac30a958442f81f5ba;hb=60f204cb9e3905100da0d89f14bb40db764acd9e;hpb=d95ee7f628ceac9af515079fb6797476557a23d2 diff --git a/riscasm.c b/riscasm.c index 5292555..2c291ff 100644 --- a/riscasm.c +++ b/riscasm.c @@ -1,7 +1,7 @@ // // RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System // RISCA.C - GPU/DSP Assembler -// Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends +// Copyright (C) 199x Landon Dyer, 2011 - 2017 Reboot and Friends // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986 // Source utilised with the kind permission of Landon Dyer // @@ -18,7 +18,7 @@ #define DEF_MR // Declare keyword values #include "risckw.h" // Incl. generated risc keywords -#define DEF_KW // Declare keyword values +#define DEF_KW // Declare keyword values #include "kwtab.h" // Incl. generated keyword tables & defs @@ -27,17 +27,18 @@ unsigned orgactive = 0; // RISC org directive active unsigned orgaddr = 0; // Org'd address unsigned orgwarning = 0; // Has an ORG warning been issued int lastOpcode = -1; // Last RISC opcode assembled +uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen const char reg_err[] = "missing register R0...R31"; -// Jaguar Jump Condition Names -const char condname[MAXINTERNCC][5] = { +// Jaguar jump condition names +const char condname[MAXINTERNCC][5] = { "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ", "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO", "PL", "MI", "F" }; -// Jaguar Jump Condition Numbers +// Jaguar jump condition numbers const char condnumber[] = { 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26, 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31 @@ -100,8 +101,8 @@ const struct opcoderecord roptbl[] = { { MR_NORMI, RI_TWO, 56 }, { MR_NOP, RI_NONE, 57 }, { MR_SAT24, RI_ONE, 62 }, - { MR_UNPACK, RI_ONE, 63 + GPUONLY }, - { MR_PACK, RI_ONE, 63 + GPUONLY }, + { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) }, + { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) }, { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY }, { MR_MOVE, RI_MOVE, 0 }, { MR_LOAD, RI_LOAD, 0 }, @@ -130,6 +131,32 @@ static inline int MalformedOpcode(int signal) return errors("Malformed opcode [internal $%s]", buf); } +// +// Function to return "Illegal Indexed Register" error +// Anyone trying to index something other than R14 or R15 +// +static inline int IllegalIndexedRegister(int reg) +{ + char buf[16]; + sprintf(buf, "%d", reg - KW_R0); + return errors("Attempted index reference with non-indexable register (r%s)", buf); +} + +// +// Function to return "Illegal Indexed Register" error for EQUR scenarios +// Trying to use register value within EQUR that isn't 14 or 15 +// +static inline int IllegalIndexedRegisterEqur(SYM *sy) +{ + //char buf[160]; + char *buf = NULL; + buf = (char *)malloc((strlen(sy->sname) + 7) * sizeof(char)); + if (NULL != buf) { + sprintf(buf, "%s = r%d",sy->sname, sy->svalue); + return errors("Attempted index reference with non-indexable register within EQUR (%s)", buf); + } + return errors("Unable to allocate memory! (IllegalIndexRegisterEqur)", "OOPS"); +} // // Build RISC instruction word @@ -139,13 +166,13 @@ void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2) // Check for absolute address setting if (!orgwarning && !orgactive) { -// warn("GPU/DSP code outside of absolute section"); warn("RISC code generated with no origin defined"); orgwarning = 1; } int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F); D_word(value); +//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value); } @@ -168,7 +195,7 @@ int GetRegister(WORD rattr) if (!(eattr & DEFINED)) { - AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr); + AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr); return 0; } @@ -205,6 +232,7 @@ int GenerateRISCCode(int state) // Get opcode parameter and type unsigned short parm = (WORD)(roptbl[state - 3000].parm); unsigned type = roptbl[state - 3000].typ; + riscImmTokenSeen = 0; // Set to "token not seen yet" // Detect whether the opcode parmeter passed determines that the opcode is // specific to only one of the RISC processors and ensure it is legal in @@ -222,22 +250,23 @@ int GenerateRISCCode(int state) break; // Single operand instructions (Rd) - // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, UNPACK + // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S, + // UNPACK case RI_ONE: reg2 = GetRegister(FU_REGTWO); at_eol(); BuildRISCIntructionWord(parm, parm >> 6, reg2); - break; + break; // Two operand instructions (Rs,Rd) - // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, MMULT, - // MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR - case RI_TWO: + // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT, + // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR + case RI_TWO: if (parm == 37) altbankok = 1; // MOVEFA reg1 = GetRegister(FU_REGONE); - CHECK_COMMA; + CHECK_COMMA; if (parm == 36) altbankok = 1; // MOVETA @@ -256,7 +285,8 @@ int GenerateRISCCode(int state) case RI_NUM_31: // Numeric operand (n,Rd) where n = 1..32 - // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, RORQ + // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ, + // RORQ case RI_NUM_32: switch (type) { @@ -279,6 +309,7 @@ int GenerateRISCCode(int state) return MalformedOpcode(0x01); tok++; + riscImmTokenSeen = 1; if (expr(r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x02); @@ -296,8 +327,8 @@ int GenerateRISCCode(int state) if ((int)eval < reg1 || (int)eval > reg2) return error("constant out of range"); - if (parm & SUB32) - reg1 = 32 - eval; + if (parm & SUB32) + reg1 = 32 - eval; else if (type == RI_NUM_32) reg1 = (reg1 == 32 ? 0 : eval); else @@ -316,6 +347,16 @@ int GenerateRISCCode(int state) return MalformedOpcode(0x03); tok++; + riscImmTokenSeen = 1; + + // Check for equated register after # and return error if so + if (*tok == SYMBOL) + { + sy = lookup(string[tok[1]], LABEL, 0); + + if (sy && (sy->sattre & EQUATEDREG)) + return error("equated register in 1st operand of MOVEI instruction"); + } if (expr(r_expr, &eval, &eattr, &esym) != OK) return MalformedOpcode(0x04); @@ -344,12 +385,13 @@ int GenerateRISCCode(int state) { if (eattr & TDB) //{ -//printf("risca: Doing rmark for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); - rmark(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL); +//printf("RISCASM: Doing MarkRelocatable for RI_MOVEI (tdb=$%X)...\n", eattr & TDB); + MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL); //} } - val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000); +// val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000); + val = WORDSWAP32(eval); CHECK_COMMA; reg2 = GetRegister(FU_REGTWO); at_eol(); @@ -378,7 +420,7 @@ int GenerateRISCCode(int state) break; // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59 - case RI_LOAD: + case RI_LOAD: indexed = 0; parm = 41; @@ -387,8 +429,14 @@ int GenerateRISCCode(int state) tok++; - if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) - indexed = (*tok - KW_R0); + if ((*(tok + 1) == '+') || (*(tok + 1) == '-')) { + // Trying to make indexed call + if ((*tok == KW_R14 || *tok == KW_R15)) { + indexed = (*tok - KW_R0); + } else { + return IllegalIndexedRegister(*tok); + } + } if (*tok == SYMBOL) { @@ -403,11 +451,13 @@ int GenerateRISCCode(int state) if (sy->sattre & EQUATEDREG) { - if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) - && (*(tok + 2) != ')')) - { - indexed = (sy->svalue & 0x1F); - tok++; + if ((*(tok + 2) == '+') || (*(tok + 2) == '-')) { + if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) { + indexed = (sy->svalue & 0x1F); + tok++; + } else { + return IllegalIndexedRegisterEqur(sy); + } } } } @@ -497,7 +547,7 @@ int GenerateRISCCode(int state) break; // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61 - case RI_STORE: + case RI_STORE: parm = 47; reg1 = GetRegister(FU_REGONE); CHECK_COMMA; @@ -508,7 +558,7 @@ int GenerateRISCCode(int state) tok++; indexed = 0; - if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) + if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')')) indexed = (*tok - KW_R0); if (*tok == SYMBOL) @@ -521,7 +571,7 @@ int GenerateRISCCode(int state) return ERROR; } - if (sy->sattre & EQUATEDREG) + if (sy->sattre & EQUATEDREG) { if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) && (*(tok + 2) != ')')) @@ -619,7 +669,7 @@ int GenerateRISCCode(int state) break; // LOADB/LOADP/LOADW (Rn),Rn - case RI_LOADN: + case RI_LOADN: if (*tok != '(') return MalformedOpcode(0x0B); @@ -637,7 +687,7 @@ int GenerateRISCCode(int state) break; // STOREB/STOREP/STOREW Rn,(Rn) - case RI_STOREN: + case RI_STOREN: reg1 = GetRegister(FU_REGONE); CHECK_COMMA;