X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=mach.c;h=ef4c8c6837c88cbf3c43675a96eebf4c6655ff64;hp=2db0db309d08494986001a3257c0a8dca324e23e;hb=76299dcc588e5f5ba7270fd4bacc5872152f088e;hpb=2ede3731285f3bc20f5493de593442e872db4d32 diff --git a/mach.c b/mach.c index 2db0db3..ef4c8c6 100644 --- a/mach.c +++ b/mach.c @@ -11,11 +11,11 @@ #include "direct.h" #include "eagen.h" #include "error.h" +#include "expr.h" #include "procln.h" #include "riscasm.h" #include "sect.h" #include "token.h" -#include "expr.h" #define DEF_KW #include "kwtab.h" @@ -168,9 +168,9 @@ char unsupport[] = "unsupported for selected CPU"; // Include code tables MNTAB machtab[] = { - { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 - #include "68ktab.h" - { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry + { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 +#include "68ktab.h" + { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry }; // Register number << 9 @@ -208,10 +208,10 @@ WORD lwsiz_8[] = { // Byte/Word/long size (0=.w, 1=.l) in bit 9 WORD lwsiz_9[] = { (WORD)-1, - 0, // Byte - 1<<9, (WORD)-1, // Word - 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long - 1<<9 // Word (SIZN) + 0, // Byte + 1<<9, (WORD)-1, // Word + 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long + 1<<9 // Word (SIZN) }; // Addressing mode in bits 6..11 (register/mode fields are reversed) @@ -452,6 +452,22 @@ int m_abcd(WORD inst, WORD siz) // int m_adda(WORD inst, WORD siz) { + if (a0exattr & DEFINED) + { + if (CHECK_OPTS(OPT_ADDA_ADDQ)) + if (a0exval > 1 && a0exval <= 8) + // Immediate is between 1 and 8 so let's convert to addq + return m_addq(B16(01010000, 00000000), siz); + if (CHECK_OPTS(OPT_ADDA_LEA)) + if (a0exval > 8) + { + // Immediate is larger than 8 so let's convert to lea + am0 = ADISP; // Change addressing mode + a0reg = a1reg; // In ADISP a0reg is used instead of a1reg! + return m_lea(B16(01000001, 11011000), SIZW); + } + } + inst |= am0 | a0reg | lwsiz_8[siz] | reg_9[a1reg]; D_word(inst); ea0gen(siz); // Generate EA @@ -739,6 +755,7 @@ int m_move(WORD inst, WORD size) return OK; } + // // Handle MOVE // MOVE @@ -1093,18 +1110,13 @@ int m_clra(WORD inst, WORD siz) int m_clrd(WORD inst, WORD siz) { if (!CHECK_OPTS(OPT_CLR_DX)) - { inst |= a0reg; - D_word(inst); - - return OK; - } else - { inst = (a0reg << 9) | B16(01110000, 00000000); - D_word(inst); - return OK; - } + + D_word(inst); + + return OK; } @@ -1302,7 +1314,7 @@ int m_cas(WORD inst, WORD siz) if (*tok != EOL) return error("extra (unexpected) text found"); - // Reject invalud ea modes + // Reject invalid ea modes amsk = amsktab[am0]; if ((amsk & (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE)) == 0) @@ -1892,6 +1904,7 @@ int m_divsl(WORD inst, WORD siz) return OK; } + // // divul.l // @@ -2489,6 +2502,7 @@ int m_pflush(WORD inst, WORD siz) return OK; } + // // pflushr (68851) // @@ -2547,12 +2561,11 @@ int m_pflushr(WORD inst, WORD siz) int m_pload(WORD inst, WORD siz, WORD extension) { // TODO: 68851 support is not added yet. - // None of the ST series of computers had a 68020 + 68551 socket and since + // None of the ST series of computers had a 68020 + 68851 socket and since // this is an Atari targetted assembler... CHECKNO30; inst |= am1; - D_word(inst); switch (am0) @@ -2585,16 +2598,19 @@ int m_pload(WORD inst, WORD siz, WORD extension) return OK; } + int m_ploadr(WORD inst, WORD siz) { return m_pload(inst, siz, 1 << 9); } + int m_ploadw(WORD inst, WORD siz) { return m_pload(inst, siz, 0 << 9); } + // // pmove (68030/68851) // @@ -2602,15 +2618,13 @@ int m_pmove(WORD inst, WORD siz) { int inst2,reg; - // TODO: 68851 support is not added yet. - // None of the ST series of computers had - // a 68020 + 68851 socket and since this is - // an Atari targetted assembler.... - // (same for 68EC030) + // TODO: 68851 support is not added yet. None of the ST series of + // computers had a 68020 + 68851 socket and since this is an Atari + // targetted assembler.... (same for 68EC030) CHECKNO30; - inst2 = inst & (1 << 8); //Copy the flush bit over to inst2 in case we're called from m_pmovefd - inst &= ~(1 << 8); //And mask it out + inst2 = inst & (1 << 8); // Copy the flush bit over to inst2 in case we're called from m_pmovefd + inst &= ~(1 << 8); // And mask it out if (am0 == CREG) { @@ -2642,7 +2656,6 @@ int m_pmove(WORD inst, WORD siz) if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN))) return error(siz_error); - if (am0 == CREG) { inst |= am1 | a1reg; @@ -2698,17 +2711,15 @@ int m_pmovefd(WORD inst, WORD siz) return m_pmove(inst | (1 << 8), siz); } + // // ptrapcc (68851) // int m_ptrapcc(WORD inst, WORD siz) { CHECKNO20; - // We stash the 5 condition bits - // inside the opcode in 68ktab - // (bits 0-4), so we need to extract - // them first and fill in - // the clobbered bits. + // We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4), + // so we need to extract them first and fill in the clobbered bits. WORD opcode = inst & 0x1F; inst = (inst & 0xFFE0) | (0x18); @@ -2732,6 +2743,7 @@ int m_ptrapcc(WORD inst, WORD siz) D_word(inst); D_word(opcode); } + return OK; } @@ -2831,8 +2843,8 @@ int m_fsabs(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01011000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2840,8 +2852,8 @@ int m_fdabs(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01011100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2867,8 +2879,8 @@ int m_fsadd(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100010), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2876,8 +2888,8 @@ int m_fdadd(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100110), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2985,8 +2997,8 @@ int m_fsdiv(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -2994,8 +3006,8 @@ int m_fddiv(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3111,7 +3123,6 @@ int m_fmod(WORD inst, WORD siz) // int m_fmove(WORD inst, WORD siz) { - // EA to register if ((am0 == FREG) && (am1 < AM_USP)) { @@ -3136,7 +3147,6 @@ int m_fmove(WORD inst, WORD siz) case SIZP: inst |= (3 << 10); // In P size we have 2 cases: {#k} where k is immediate // and {Dn} where Dn=Data register - if (bfparam1) { // Dn @@ -3158,7 +3168,6 @@ int m_fmove(WORD inst, WORD siz) break; } - // Destination specifier inst |= (a0reg << 7); @@ -3261,8 +3270,8 @@ int m_fmovescr(WORD inst, WORD siz) ea0gen(siz); return OK; } - else - return error("m_fmovescr says: wut?"); + + return error("m_fmovescr says: wut?"); } // @@ -3320,7 +3329,7 @@ int m_fmovem(WORD inst, WORD siz) WORD regmask; WORD datareg; - if (siz == SIZX || siz==SIZN) + if (siz == SIZX || siz == SIZN) { if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) { @@ -3553,8 +3562,8 @@ int m_fdneg(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01011110), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3592,11 +3601,8 @@ int m_fscale(WORD inst, WORD siz) // int m_fscc(WORD inst, WORD siz) { - // We stash the 5 condition bits - // inside the opcode in 68ktab - // (bits 4-0), so we need to extract - // them first and fill in - // the clobbered bits. + // We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0), + // so we need to extract them first and fill in the clobbered bits. WORD opcode = inst & 0x1F; inst &= 0xFFE0; inst |= am0 | a0reg; @@ -3606,19 +3612,17 @@ int m_fscc(WORD inst, WORD siz) return OK; } + // // FTRAPcc (6888X, 68040) // - int m_ftrapcc(WORD inst, WORD siz) { - // We stash the 5 condition bits - // inside the opcode in 68ktab - // (bits 3-7), so we need to extract - // them first and fill in - // the clobbered bits. + // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7), + // so we need to extract them first and fill in the clobbered bits. WORD opcode = (inst >> 3) & 0x1F; inst = (inst & 0xFF07) | (0xF << 3); + if (siz == SIZW) { inst |= 2; @@ -3640,9 +3644,11 @@ int m_ftrapcc(WORD inst, WORD siz) D_word(opcode); return OK; } + return OK; } + // // fsgldiv (6888X, 68040) // @@ -3675,19 +3681,20 @@ int m_fsin(WORD inst, WORD siz) // int m_fsincos(WORD inst, WORD siz) { - // Swap a1reg, a2reg as a2reg should be stored - // in the bitfield gen_fpu generates + // Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu + // generates int temp; temp = a2reg; a2reg = a1reg; a1reg = temp; + if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK) { chptr[-1] |= a2reg; return OK; } - else - return ERROR; + + return ERROR; } @@ -3722,8 +3729,8 @@ int m_fdfsqrt(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01000101), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3740,8 +3747,8 @@ int m_fsfsub(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01101000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); } @@ -3749,8 +3756,8 @@ int m_fdsub(WORD inst, WORD siz) { if (activefpu == FPU_68040) return gen_fpu(inst, siz, B8(01101100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + + return error("Unsupported in current FPU"); }