X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=mach.c;h=9a9882e6b7c5c669c8a58c19f18ff58fab51c163;hp=3c7a30c17fc319a74fc978960ad879e1becaf87a;hb=HEAD;hpb=5559ac02922836380db93969986836bb004c8b37

diff --git a/mach.c b/mach.c
index 3c7a30c..1fb1607 100644
--- a/mach.c
+++ b/mach.c
@@ -17,8 +17,8 @@
 #include "sect.h"
 #include "token.h"
 
-#define DEF_KW
-#include "kwtab.h"
+#define DEF_REG68
+#include "68kregs.h"
 
 // Exported variables
 int movep = 0; // Global flag to indicate we're generating a movep instruction
@@ -1073,7 +1073,7 @@ int m_movem(WORD inst, WORD siz)
 		goto immed1;
 	}
 
-	if ((*tok >= KW_D0) && (*tok <= KW_A7))
+	if ((*tok >= REG68_D0) && (*tok <= REG68_A7))
 	{
 		// <rlist>, ea
 		if (reglist(&rmask) < 0)
@@ -1365,7 +1365,7 @@ int m_cas(WORD inst, WORD siz)
 	}
 
 	// Dc
-	if ((*tok < KW_D0) && (*tok > KW_D7))
+	if ((*tok < REG68_D0) && (*tok > REG68_D7))
 		return error("CAS accepts only data registers");
 
 	inst2 = (*tok++) & 7;
@@ -1374,7 +1374,7 @@ int m_cas(WORD inst, WORD siz)
 		return error("missing comma");
 
 	// Du
-	if ((*tok < KW_D0) && (*tok > KW_D7))
+	if ((*tok < REG68_D0) && (*tok > REG68_D7))
 		return error("CAS accepts only data registers");
 
 	inst2 |= ((*tok++) & 7) << 6;
@@ -1435,7 +1435,7 @@ int m_cas2(WORD inst, WORD siz)
 	}
 
 	// Dc1
-	if ((*tok < KW_D0) && (*tok > KW_D7))
+	if ((*tok < REG68_D0) && (*tok > REG68_D7))
 		return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
 
 	inst2 = (*tok++) & 7;
@@ -1444,7 +1444,7 @@ int m_cas2(WORD inst, WORD siz)
 		return error("missing colon");
 
 	// Dc2
-	if ((*tok < KW_D0) && (*tok > KW_D7))
+	if ((*tok < REG68_D0) && (*tok > REG68_D7))
 		return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
 
 	inst3 = (*tok++) & 7;
@@ -1453,7 +1453,7 @@ int m_cas2(WORD inst, WORD siz)
 		return error("missing comma");
 
 	// Du1
-	if ((*tok < KW_D0) && (*tok > KW_D7))
+	if ((*tok < REG68_D0) && (*tok > REG68_D7))
 		return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
 
 	inst2 |= ((*tok++) & 7) << 6;
@@ -1462,7 +1462,7 @@ int m_cas2(WORD inst, WORD siz)
 		return error("missing colon");
 
 	// Du2
-	if ((*tok < KW_D0) && (*tok > KW_D7))
+	if ((*tok < REG68_D0) && (*tok > REG68_D7))
 		return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
 
 	inst3 |= ((*tok++) & 7) << 6;
@@ -1473,9 +1473,9 @@ int m_cas2(WORD inst, WORD siz)
 	// Rn1
 	if (*tok++ != '(')
 		return error("missing (");
-	if ((*tok >= KW_D0) && (*tok <= KW_D7))
+	if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
 		inst2 |= (((*tok++) & 7) << 12) | (0 << 15);
-	else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+	else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
 		inst2 |= (((*tok++) & 7) << 12) | (1 << 15);
 	else
 		return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
@@ -1489,9 +1489,9 @@ int m_cas2(WORD inst, WORD siz)
 	// Rn2
 	if (*tok++ != '(')
 		return error("missing (");
-	if ((*tok >= KW_D0) && (*tok <= KW_D7))
+	if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
 		inst3 |= (((*tok++) & 7) << 12) | (0 << 15);
-	else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+	else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
 		inst3 |= (((*tok++) & 7) << 12) | (1 << 15);
 	else
 		return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
@@ -1884,7 +1884,7 @@ int m_pack(WORD inst, WORD siz)
 	if (siz != SIZN)
 		return error("bad size suffix");
 
-	if (*tok >= KW_D0 && *tok <= KW_D7)
+	if (*tok >= REG68_D0 && *tok <= REG68_D7)
 	{
 		// Dx,Dy,#<adjustment>
 		inst |= (0 << 3);   // R/M
@@ -1893,7 +1893,7 @@ int m_pack(WORD inst, WORD siz)
 		if (*tok != ',' && tok[2] != ',')
 			return error("missing comma");
 
-		if (tok[1] < KW_D0 && tok[1] > KW_D7)
+		if (tok[1] < REG68_D0 && tok[1] > REG68_D7)
 			return error(syntax_error);
 
 		inst |= ((tok[1] & 7)<<9);
@@ -1910,10 +1910,10 @@ int m_pack(WORD inst, WORD siz)
 		if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ','))
 			return error(syntax_error);
 
-		if (tok[1] < KW_A0 && tok[1] > KW_A7)
+		if (tok[1] < REG68_A0 && tok[1] > REG68_A7)
 			return error(syntax_error);
 
-		if (tok[5] < KW_A0 && tok[6] > KW_A7)
+		if (tok[5] < REG68_A0 && tok[6] > REG68_A7)
 			return error(syntax_error);
 
 		inst |= ((tok[1] & 7) << 0);
@@ -2044,13 +2044,13 @@ int m_cinv(WORD inst, WORD siz)
 		inst |= (0 << 6) | (a1reg);
 	switch (a0reg)
 	{
-	case 0:     // KW_IC40
+	case 0:     // REG68_IC40
 		inst |= (2 << 6) | (a1reg);
 		break;
-	case 1:     // KW_DC40
+	case 1:     // REG68_DC40
 		inst |= (1 << 6) | (a1reg);
 		break;
-	case 2:     // KW_BC40
+	case 2:     // REG68_BC40
 		inst |= (3 << 6) | (a1reg);
 		break;
 	}
@@ -2247,21 +2247,21 @@ int m_pflush(WORD inst, WORD siz)
 
 			fc = (uint16_t)a0exval;
 			break;
-		case KW_D0:
-		case KW_D1:
-		case KW_D2:
-		case KW_D3:
-		case KW_D4:
-		case KW_D5:
-		case KW_D6:
-		case KW_D7:
+		case REG68_D0:
+		case REG68_D1:
+		case REG68_D2:
+		case REG68_D3:
+		case REG68_D4:
+		case REG68_D5:
+		case REG68_D6:
+		case REG68_D7:
 			fc = (1 << 4) | (*tok++ & 7);
 			break;
-		case KW_SFC:
+		case REG68_SFC:
 			fc = 0;
 			tok++;
 			break;
-		case KW_DFC:
+		case REG68_DFC:
 			fc = 1;
 			tok++;
 			break;
@@ -2333,7 +2333,7 @@ int m_pflush(WORD inst, WORD siz)
 		if (*tok != '(' && tok[2] != ')')
 			return error(syntax_error);
 
-		if (tok[1] < KW_A0 && tok[1] > KW_A7)
+		if (tok[1] < REG68_A0 && tok[1] > REG68_A7)
 			return error("expected (An)");
 
 		if ((inst & 7) == 7)
@@ -2438,9 +2438,9 @@ int m_pload(WORD inst, WORD siz, WORD extension)
 	switch (am0)
 	{
 	case CREG:
-		if (a0reg == KW_SFC - KW_SFC)
+		if (a0reg == REG68_SFC - REG68_SFC)
 			inst = 0;
-		else if (a0reg == KW_DFC - KW_SFC)
+		else if (a0reg == REG68_DFC - REG68_SFC)
 			inst = 1;
 		else
 			return error("illegal control register specified");
@@ -2514,15 +2514,15 @@ int m_pmove(WORD inst, WORD siz)
 	// and the transparent translation registers(TT0 and TT1).
 	// It is a word operation for the MMU status register.
 
-	if (((reg == (KW_URP - KW_SFC)) || (reg == (KW_SRP - KW_SFC)))
+	if (((reg == (REG68_URP - REG68_SFC)) || (reg == (REG68_SRP - REG68_SFC)))
 		&& ((siz != SIZD) && (siz != SIZN)))
 		return error(siz_error);
 
-	if (((reg == (KW_TC - KW_SFC)) || (reg == (KW_TT0 - KW_SFC)) || (reg == (KW_TT1 - KW_SFC)))
+	if (((reg == (REG68_TC - REG68_SFC)) || (reg == (REG68_TT0 - REG68_SFC)) || (reg == (REG68_TT1 - REG68_SFC)))
 		&& ((siz != SIZL) && (siz != SIZN)))
 		return error(siz_error);
 
-	if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN)))
+	if ((reg == (REG68_MMUSR - REG68_SFC)) && ((siz != SIZW) && (siz != SIZN)))
 		return error(siz_error);
 
 	if (am0 == CREG)
@@ -2536,19 +2536,19 @@ int m_pmove(WORD inst, WORD siz)
 		D_word(inst);
 	}
 
-	switch (reg + KW_SFC)
+	switch (reg + REG68_SFC)
 	{
-	case KW_TC:
+	case REG68_TC:
 		inst2 |= (0 << 10) + (1 << 14); break;
-	case KW_SRP:
+	case REG68_SRP:
 		inst2 |= (2 << 10) + (1 << 14); break;
-	case KW_CRP:
+	case REG68_CRP:
 		inst2 |= (3 << 10) + (1 << 14); break;
-	case KW_TT0:
+	case REG68_TT0:
 		inst2 |= (2 << 10) + (0 << 13); break;
-	case KW_TT1:
+	case REG68_TT1:
 		inst2 |= (3 << 10) + (0 << 13); break;
-	case KW_MMUSR:
+	case REG68_MMUSR:
 		if (am0 == CREG)
 			inst2 |= (1 << 9) + (3 << 13);
 		else
@@ -2637,9 +2637,9 @@ int m_ptest(WORD inst, WORD siz, WORD extension)
 		switch (am0)
 		{
 		case CREG:
-			if (a0reg == KW_SFC - KW_SFC)
+			if (a0reg == REG68_SFC - REG68_SFC)
 				extension |= 0;
-			else if (a0reg == KW_DFC - KW_SFC)
+			else if (a0reg == REG68_DFC - REG68_SFC)
 				extension |= 1;
 			else
 				return error("illegal control register specified");
@@ -2684,7 +2684,7 @@ int m_ptest(WORD inst, WORD siz, WORD extension)
 		{
 			CHECK_COMMA
 
-			if ((*tok >= KW_A0) && (*tok <= KW_A7))
+			if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
 			{
 				extension |= (1 << 8) | ((*tok++ & 7) << 4);
 			}
@@ -3338,7 +3338,7 @@ int m_fmovem(WORD inst, WORD siz)
 
 	if (siz == SIZX || siz == SIZN)
 	{
-		if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+		if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
 		{
 			// fmovem.x <rlist>,ea
 			if (fpu_reglist_left(&regmask) < 0)
@@ -3361,7 +3361,7 @@ int m_fmovem(WORD inst, WORD siz)
 			ea0gen(siz);
 			return OK;
 		}
-		else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+		else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
 		{
 			// fmovem.x Dn,ea
 			datareg = (*tok++ & 7) << 10;
@@ -3399,7 +3399,7 @@ int m_fmovem(WORD inst, WORD siz)
 			if (*tok++ != ',')
 				return error("missing comma");
 
-			if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+			if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
 			{
 				// fmovem.x ea,<rlist>
 				if (fpu_reglist_right(&regmask) < 0)
@@ -3431,14 +3431,14 @@ int m_fmovem(WORD inst, WORD siz)
 	}
 	else if (siz == SIZL)
 	{
-		if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR))
+		if ((*tok == REG68_FPCR) || (*tok == REG68_FPSR) || (*tok == REG68_FPIAR))
 		{
 			// fmovem.l <rlist>,ea
 			regmask = (1 << 15) | (1 << 13);
 			int no_control_regs = 0;
 
 fmovem_loop_1:
-			if (*tok == KW_FPCR)
+			if (*tok == REG68_FPCR)
 			{
 				regmask |= (1 << 12);
 				tok++;
@@ -3446,7 +3446,7 @@ fmovem_loop_1:
 				goto fmovem_loop_1;
 			}
 
-			if (*tok == KW_FPSR)
+			if (*tok == REG68_FPSR)
 			{
 				regmask |= (1 << 11);
 				tok++;
@@ -3454,7 +3454,7 @@ fmovem_loop_1:
 				goto fmovem_loop_1;
 			}
 
-			if (*tok == KW_FPIAR)
+			if (*tok == REG68_FPIAR)
 			{
 				regmask |= (1 << 10);
 				tok++;
@@ -3501,21 +3501,21 @@ fmovem_loop_1:
 			regmask = (1 << 15) | (0 << 13);
 
 fmovem_loop_2:
-			if (*tok == KW_FPCR)
+			if (*tok == REG68_FPCR)
 			{
 				regmask |= (1 << 12);
 				tok++;
 				goto fmovem_loop_2;
 			}
 
-			if (*tok == KW_FPSR)
+			if (*tok == REG68_FPSR)
 			{
 				regmask |= (1 << 11);
 				tok++;
 				goto fmovem_loop_2;
 			}
 
-			if (*tok == KW_FPIAR)
+			if (*tok == REG68_FPIAR)
 			{
 				regmask |= (1 << 10);
 				tok++;