X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=mach.c;h=7c1ab8ea6ae7e1d750f1233ec36875c97721cadb;hp=19dc67dbaed9231437f69a341f6e334e11b19f76;hb=81c752326a21408c84f98a18aed065491a88b779;hpb=5cd8a4814b805f1ef8ce689423eb5eeba12573c5 diff --git a/mach.c b/mach.c index 19dc67d..7c1ab8e 100644 --- a/mach.c +++ b/mach.c @@ -1,18 +1,19 @@ // -// RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System +// RMAC - Reboot's Macro Assembler for all Atari computers // MACH.C - Code Generation -// Copyright (C) 199x Landon Dyer, 2017 Reboot and Friends +// Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986 // Source utilised with the kind permission of Landon Dyer // #include "mach.h" +#include "amode.h" +#include "direct.h" #include "eagen.h" #include "error.h" -#include "direct.h" +#include "expr.h" #include "procln.h" #include "riscasm.h" -#include "rmac.h" #include "sect.h" #include "token.h" @@ -22,6 +23,137 @@ // Exported variables int movep = 0; // Global flag to indicate we're generating a movep instruction +// Function prototypes +int m_unimp(WORD, WORD), m_badmode(WORD, WORD); +int m_self(WORD, WORD); +int m_abcd(WORD, WORD); +int m_reg(WORD, WORD); +int m_imm(WORD, WORD); +int m_imm8(WORD, WORD); +int m_shi(WORD, WORD); +int m_shr(WORD, WORD); +int m_bitop(WORD, WORD); +int m_exg(WORD, WORD); +int m_ea(WORD, WORD); +int m_lea(WORD, WORD); +int m_br(WORD, WORD); +int m_dbra(WORD, WORD); +int m_link(WORD, WORD); +int m_adda(WORD, WORD); +int m_addq(WORD, WORD); +int m_move(WORD, WORD); +int m_moveq(WORD, WORD); +int m_usp(WORD, WORD); +int m_movep(WORD, WORD); +int m_trap(WORD, WORD); +int m_movem(WORD, WORD); +int m_clra(WORD, WORD); +int m_clrd(WORD, WORD); + +int m_move30(WORD, WORD); // 68020/30/40/60 +int m_br30(WORD inst, WORD siz); +int m_ea030(WORD inst, WORD siz); +int m_bfop(WORD inst, WORD siz); +int m_callm(WORD inst, WORD siz); +int m_cas(WORD inst, WORD siz); +int m_cas2(WORD inst, WORD siz); +int m_chk2(WORD inst, WORD siz); +int m_cmp2(WORD inst, WORD siz); +int m_bkpt(WORD inst, WORD siz); +int m_cpbr(WORD inst, WORD siz); +int m_cpdbr(WORD inst, WORD siz); +int m_muls(WORD inst, WORD siz); +int m_move16a(WORD inst, WORD siz); +int m_move16b(WORD inst, WORD siz); +int m_pack(WORD inst, WORD siz); +int m_rtm(WORD inst, WORD siz); +int m_rtd(WORD inst, WORD siz); +int m_trapcc(WORD inst, WORD siz); +int m_cinv(WORD inst, WORD siz); +int m_cprest(WORD inst, WORD siz); +int m_movec(WORD inst, WORD siz); +int m_moves(WORD inst, WORD siz); +int m_lpstop(WORD inst, WORD siz); +int m_plpa(WORD inst, WORD siz); + +// PMMU +int m_pbcc(WORD inst, WORD siz); +int m_pflusha(WORD inst, WORD siz); +int m_pflush(WORD inst, WORD siz); +int m_pflushr(WORD inst, WORD siz); +int m_pflushan(WORD inst, WORD siz); +int m_pload(WORD inst, WORD siz, WORD extension); +int m_pmove(WORD inst, WORD siz); +int m_pmovefd(WORD inst, WORD siz); +int m_ptest(WORD inst, WORD siz); +int m_ptrapcc(WORD inst, WORD siz); +int m_ploadr(WORD inst, WORD siz); +int m_ploadw(WORD inst, WORD siz); + +// FPU +int m_fabs(WORD inst, WORD siz); +int m_facos(WORD inst, WORD siz); +int m_fadd(WORD inst, WORD siz); +int m_fasin(WORD inst, WORD siz); +int m_fatan(WORD inst, WORD siz); +int m_fatanh(WORD inst, WORD siz); +int m_fcmp(WORD inst, WORD siz); +int m_fcos(WORD inst, WORD siz); +int m_fcosh(WORD inst, WORD siz); +int m_fdabs(WORD inst, WORD siz); +int m_fdadd(WORD inst, WORD siz); +int m_fdbcc(WORD inst, WORD siz); +int m_fddiv(WORD inst, WORD siz); +int m_fdfsqrt(WORD inst, WORD siz); +int m_fdiv(WORD inst, WORD siz); +int m_fdmove(WORD inst, WORD siz); +int m_fdmul(WORD inst, WORD siz); +int m_fdneg(WORD inst, WORD siz); +int m_fdsub(WORD inst, WORD siz); +int m_fetox(WORD inst, WORD siz); +int m_fetoxm1(WORD inst, WORD siz); +int m_fgetexp(WORD inst, WORD siz); +int m_fgetman(WORD inst, WORD siz); +int m_fint(WORD inst, WORD siz); +int m_fintrz(WORD inst, WORD siz); +int m_flog10(WORD inst, WORD siz); +int m_flog2(WORD inst, WORD siz); +int m_flogn(WORD inst, WORD siz); +int m_flognp1(WORD inst, WORD siz); +int m_fmod(WORD inst, WORD siz); +int m_fmove(WORD inst, WORD siz); +int m_fmovescr(WORD inst, WORD siz); +int m_fmovecr(WORD inst, WORD siz); +int m_fmovem(WORD inst, WORD siz); +int m_fmul(WORD inst, WORD siz); +int m_fneg(WORD inst, WORD siz); +int m_fnop(WORD inst, WORD siz); +int m_frem(WORD inst, WORD siz); +int m_frestore(WORD inst, WORD siz); +int m_fsabs(WORD inst, WORD siz); +int m_fsadd(WORD inst, WORD siz); +int m_fscc(WORD inst, WORD siz); +int m_fscale(WORD inst, WORD siz); +int m_fsdiv(WORD inst, WORD siz); +int m_fsfsqrt(WORD inst, WORD siz); +int m_fsfsub(WORD inst, WORD siz); +int m_fsgldiv(WORD inst, WORD siz); +int m_fsglmul(WORD inst, WORD siz); +int m_fsin(WORD inst, WORD siz); +int m_fsincos(WORD inst, WORD siz); +int m_fsinh(WORD inst, WORD siz); +int m_fsmove(WORD inst, WORD siz); +int m_fsmul(WORD inst, WORD siz); +int m_fsneg(WORD inst, WORD siz); +int m_fsqrt(WORD inst, WORD siz); +int m_fsub(WORD inst, WORD siz); +int m_ftan(WORD inst, WORD siz); +int m_ftanh(WORD inst, WORD siz); +int m_ftentox(WORD inst, WORD siz); +int m_ftst(WORD inst, WORD siz); +int m_ftwotox(WORD inst, WORD siz); +int m_ftrapcc(WORD inst, WORD siz); + // Common error messages char range_error[] = "expression out of range"; char abs_error[] = "illegal absolute expression"; @@ -32,16 +164,11 @@ char undef_error[] = "undefined expression"; char fwd_error[] = "forward or undefined expression"; char unsupport[] = "unsupported for selected CPU"; -extern int ea0gen(WORD); -extern int ea1gen(WORD); -extern int mulmode; - // Include code tables MNTAB machtab[] = { -// { (WORD)-1, (unsigned long)-1L, (unsigned long)-1L, 0x0000, 0, m_badmode }, // 0 - { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 - #include "68ktab.h" - { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry + { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 +#include "68ktab.h" + { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry }; // Register number << 9 @@ -79,10 +206,10 @@ WORD lwsiz_8[] = { // Byte/Word/long size (0=.w, 1=.l) in bit 9 WORD lwsiz_9[] = { (WORD)-1, - 0, // Byte - 1<<9, (WORD)-1, // Word - 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long - 1<<9 // Word (SIZN) + 0, // Byte + 1<<9, (WORD)-1, // Word + 1<<10, (WORD)-1, (WORD)-1, (WORD)-1, // Long + 1<<9 // Word (SIZN) }; // Addressing mode in bits 6..11 (register/mode fields are reversed) @@ -124,9 +251,10 @@ WORD CREGlut[21] = { 0x006, // Data Access Control Register 0 (DACR1) 0x007, // Data Access Control Register 1 (DACR1) // 68851 only - 0xfff // CPU Root Pointer (CRP) - There's no movec with CRP in it, this is just a guard entry + 0xFFF // CPU Root Pointer (CRP) - There's no movec with CRP in it, this is just a guard entry }; + // Error messages int m_unimp(WORD unused1, WORD unused2) { @@ -210,84 +338,90 @@ int m_ea(WORD inst, WORD siz) return OK; } + // -// Check if lea x(an),an can be optimised to -// addq.w #x,an - otherwise fall back to m_ea. +// Check if lea x(an),an can be optimised to addq.w #x,an--otherwise fall back +// to m_ea. // int m_lea(WORD inst, WORD siz) { - if (optim_flags[OPT_LEA_ADDQ]) - if (am0==ADISP && a0reg==a1reg && (a0exattr & DEFINED)) - if (a0exval>0 && a0exval<=8) - { - inst=B16(01010000,01001000)|((a0exval&7)<<9)|(a0reg); - D_word(inst); - warn("lea size(An),An converted to addq #size,An"); - return OK; - } + if (CHECK_OPTS(OPT_LEA_ADDQ) + && ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED)) + && ((a0exval > 0) && (a0exval <= 8))) + { + inst = B16(01010000, 01001000) | (((uint16_t)a0exval & 7) << 9) | (a0reg); + D_word(inst); + warn("lea size(An),An converted to addq #size,An"); + return OK; + } - return m_ea(inst,siz); + return m_ea(inst, siz); } + int m_ea030(WORD inst, WORD siz) { - CHECK00; - - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr + CHECK00; + WORD flg = inst; // Save flag bits + inst &= ~0x3F; // Clobber flag bits in instr - // Install "standard" instr size bits + // Install "standard" instr size bits if (flg & 4) inst |= siz_6[siz]; if (flg & 16) { - // OR-in register number + // OR-in register number if (flg & 8) { - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 + inst |= reg_9[a1reg]; // ea1reg in bits 9..11 } else { - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 + inst |= reg_9[a0reg]; // ea0reg in bits 9..11 } } if (flg & 1) { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr + // Use am1 + inst |= am1 | a1reg; // Get ea1 into instr + D_word(inst); // Deposit instr - // Generate ea0 if requested + // Generate ea0 if requested if (flg & 2) ea0gen(siz); - ea1gen(siz); // Generate ea1 + ea1gen(siz); // Generate ea1 } else { - // Use am0 - //inst |= am0 | a0reg; // Get ea0 into instr - if (am0 == AREG) - //We get here if we're doing 020+ addressing and an address register is used. - //For example, something like "tst a0". A bit of a corner case, so kludge it - a0reg = a0reg + 8; - else if (am0 == PCDISP) - //Another corner case (possibly!), so kludge ahoy - inst |= am0; // Get ea0 into instr - else if (am0 == IMMED) - inst |= am0 | a0reg; // Get ea0 into instr - else if (am0 == AM_CCR) - inst |= am1 | a1reg; - else if (am0 == AIND) - inst |= am0; - - inst |= a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 - - // Generate ea1 if requested + // Use am0 + if (am0 == AREG) + // We get here if we're doing 020+ addressing and an address + // register is used. For example, something like "tst a0". A bit of + // a corner case, so kludge it + a0reg = a0reg + 8; + else if (am0 == PCDISP) + // Another corner case (possibly!), so kludge ahoy + inst |= am0; // Get ea0 into instr + else if (am0 == IMMED && am1 == MEMPOST) + { + // Added for addi/andi/cmpi/eori/ori/subi #xx,(bd,An,Dm) + inst |= a1reg | AINDEXED; + } + else if (am0 == IMMED) + inst |= am0 | a0reg; // Get ea0 into instr + else if (am0 == AM_CCR) + inst |= am1 | a1reg; + else if (am0 == AIND) + inst |= am0; + + inst |= a0reg; // Get ea0 into instr + D_word(inst); // Deposit instr + ea0gen(siz); // Generate ea0 + + // Generate ea1 if requested if (flg & 2) ea1gen(siz); } @@ -321,6 +455,22 @@ int m_abcd(WORD inst, WORD siz) // int m_adda(WORD inst, WORD siz) { + if (a0exattr & DEFINED) + { + if (CHECK_OPTS(OPT_ADDA_ADDQ)) + if (a0exval > 1 && a0exval <= 8) + // Immediate is between 1 and 8 so let's convert to addq + return m_addq(B16(01010000, 00000000), siz); + if (CHECK_OPTS(OPT_ADDA_LEA)) + if (a0exval > 8) + { + // Immediate is larger than 8 so let's convert to lea + am0 = ADISP; // Change addressing mode + a0reg = a1reg; // In ADISP a0reg is used instead of a1reg! + return m_lea(B16(01000001, 11011000), SIZW); + } + } + inst |= am0 | a0reg | lwsiz_8[siz] | reg_9[a1reg]; D_word(inst); ea0gen(siz); // Generate EA @@ -450,8 +600,6 @@ int m_bitop(WORD inst, WORD siz) int m_dbra(WORD inst, WORD siz) { - VALUE v; - siz = siz; inst |= a0reg; D_word(inst); @@ -461,7 +609,7 @@ int m_dbra(WORD inst, WORD siz) if ((a1exattr & TDB) != cursect) return error(rel_error); - v = a1exval - sloc; + uint32_t v = (uint32_t)a1exval - sloc; if (v + 0x8000 > 0x10000) return error(range_error); @@ -488,14 +636,14 @@ int m_exg(WORD inst, WORD siz) siz = siz; if (am0 == DREG && am1 == DREG) - m = 0x0040; // Dn,Dn + m = 0x0040; // Dn,Dn else if (am0 == AREG && am1 == AREG) - m = 0x0048; // An,An + m = 0x0048; // An,An else { if (am0 == AREG) - { // Dn,An or An,Dn - m = a1reg; // Get AREG into a1reg + { // Dn,An or An,Dn + m = a1reg; // Get AREG into a1reg a1reg = a0reg; a0reg = m; } @@ -515,15 +663,17 @@ int m_exg(WORD inst, WORD siz) // int m_link(WORD inst, WORD siz) { - if (siz != SIZL) - { - } - else - { - CHECK00; - inst &= ~((3 << 9)|(1<<6)|(1<<4)); - inst |= 1 << 3; - } + if (siz != SIZL) + { + // Is this an error condition??? + } + else + { + CHECK00; + inst &= ~((3 << 9) | (1 << 6) | (1 << 4)); + inst |= 1 << 3; + } + inst |= a0reg; D_word(inst); ea1gen(siz); @@ -531,27 +681,28 @@ int m_link(WORD inst, WORD siz) return OK; } + WORD extra_addressing[16]= { - 0, //0100 (bd,An,Xn) - 0, //0101 ([bd,An],Xn,od) - 0x180, //0102 ([bc,An,Xn],od) (111 110 110 111) - 0, //0103 (bd,PC,Xn) - 0, //0104 ([bd,PC],Xn,od) - 0, //0105 ([bc,PC,Xn],od) - 0, //0106 - 0, //0107 - 0, //0110 - 0, //0111 Nothing - 0x30, //0112 (Dn.w) - 0x30, //0113 (Dn.l) - 0, //0114 - 0, //0115 - 0, //0116 - 0 //0117 - + 0x30, // 0100 (bd,An,Xn) + 0x30, // 0101 ([bd,An],Xn,od) + 0x30, // 0102 ([bc,An,Xn],od) + 0x30, // 0103 (bd,PC,Xn) + 0x30, // 0104 ([bd,PC],Xn,od) + 0x30, // 0105 ([bc,PC,Xn],od) + 0, // 0106 + 0, // 0107 + 0, // 0110 + 0, // 0111 Nothing + 0x30, // 0112 (Dn.w) + 0x30, // 0113 (Dn.l) + 0, // 0114 + 0, // 0115 + 0, // 0116 + 0 // 0117 }; + // // Handle MOVE // MOVE @@ -564,8 +715,12 @@ int m_move(WORD inst, WORD size) int siz = (int)size; // Try to optimize to MOVEQ - if (optim_flags[OPT_MOVEL_MOVEQ] && siz == SIZL && am0 == IMMED && am1 == DREG - && (a0exattr & (TDB|DEFINED)) == DEFINED && a0exval + 0x80 < 0x100) + // N.B.: We can get away with casting the uint64_t to a 32-bit value + // because it checks for a SIZL (i.e., a 32-bit value). + if (CHECK_OPTS(OPT_MOVEL_MOVEQ) + && (siz == SIZL) && (am0 == IMMED) && (am1 == DREG) + && ((a0exattr & (TDB | DEFINED)) == DEFINED) + && ((uint32_t)a0exval + 0x80 < 0x100)) { m_moveq((WORD)0x7000, (WORD)0); @@ -574,21 +729,21 @@ int m_move(WORD inst, WORD size) } else { - if (am0= ADISP) - ea0gen((WORD)siz); + if (am0 >= ADISP) + ea0gen((WORD)siz); - if (am1 >= ADISP) - ea1gen((WORD)siz | 0x8000); // Tell ea1gen we're move ea,ea - } - else //68020+ modes + if (am1 >= ADISP) + ea1gen((WORD)siz | 0x8000); // Tell ea1gen we're move ea,ea + } + else // 68020+ modes { - inst |= siz_12[siz] | reg_9[a1reg] | extra_addressing[am0-ABASE]; + inst |= siz_12[siz] | reg_9[a1reg] | extra_addressing[am0 - ABASE]; D_word(inst); @@ -603,39 +758,23 @@ int m_move(WORD inst, WORD size) return OK; } + // // Handle MOVE -// MOVE -// +// MOVE +// int m_move30(WORD inst, WORD size) { - // Cast the passed in value to an int int siz = (int)size; + inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE]; - /*if (am0= ADISP) - ea0gen((WORD)siz); - - if (am1 >= ADISP) - | 0x8000); // Tell ea1gen we're move ea,ea - } - else //68020+ modes - {*/ - inst |= siz_12[siz] | reg_9[a1reg&7] | a0reg | extra_addressing[am0-ABASE]; - - D_word(inst); + D_word(inst); - if (am0 >= ADISP) - ea0gen((WORD)siz); + if (am0 >= ADISP) + ea0gen((WORD)siz); - if (am1 >= ADISP) - ea1gen((WORD)siz); - /*}*/ + if (am1 >= ADISP) + ea1gen((WORD)siz); return OK; } @@ -672,7 +811,7 @@ int m_moveq(WORD inst, WORD siz) AddFixup(FU_BYTE | FU_SEXT, sloc + 1, a0expr); a0exval = 0; } - else if (a0exval + 0x100 >= 0x200) + else if ((uint32_t)a0exval + 0x100 >= 0x200) return error(range_error); inst |= reg_9[a1reg] | (a0exval & 0xFF); @@ -681,12 +820,15 @@ int m_moveq(WORD inst, WORD siz) return OK; } + // // movep Dn, disp(An) -- movep disp(An), Dn // int m_movep(WORD inst, WORD siz) { - movep = 1; // Tell ea0gen to lay off the 0(a0) optimisations on this one + // Tell ea0gen to lay off the 0(a0) optimisations on this one + movep = 1; + if (siz == SIZL) inst |= 0x0040; @@ -711,7 +853,7 @@ int m_movep(WORD inst, WORD siz) ea0gen(siz); } - movep = 0; + movep = 0; return 0; } @@ -721,8 +863,6 @@ int m_movep(WORD inst, WORD siz) // int m_br(WORD inst, WORD siz) { - VALUE v; - if (a0exattr & DEFINED) { if ((a0exattr & TDB) != cursect) @@ -731,24 +871,26 @@ int m_br(WORD inst, WORD siz) return error(rel_error); //} - v = a0exval - (sloc + 2); + uint32_t v = (uint32_t)a0exval - (sloc + 2); // Optimize branch instr. size if (siz == SIZN) { - if (optim_flags[OPT_BSR_BCC_S] && v != 0 && v + 0x80 < 0x100) + if (CHECK_OPTS(OPT_BSR_BCC_S) && (v != 0) && ((v + 0x80) < 0x100)) { // Fits in .B inst |= v & 0xFF; D_word(inst); + if (sbra_flag) warn("Bcc.w/BSR.w converted to .s"); + return OK; } else { // Fits in .W - if (v + 0x8000 > 0x10000) + if ((v + 0x8000) > 0x10000) return error(range_error); D_word(inst); @@ -759,7 +901,7 @@ int m_br(WORD inst, WORD siz) if (siz == SIZB || siz == SIZS) { - if (v + 0x80 >= 0x100) + if ((v + 0x80) >= 0x100) return error(range_error); inst |= v & 0xFF; @@ -767,7 +909,7 @@ int m_br(WORD inst, WORD siz) } else { - if (v + 0x8000 >= 0x10000) + if ((v + 0x8000) >= 0x10000) return error(range_error); D_word(inst); @@ -807,7 +949,7 @@ int m_addq(WORD inst, WORD siz) if (a0exattr & DEFINED) { - if (a0exval > 8 || a0exval == 0) // Range in 1..8 + if ((a0exval > 8) || (a0exval == 0)) // Range in 1..8 return error(range_error); inst |= (a0exval & 7) << 9; @@ -855,7 +997,7 @@ int m_trap(WORD inst, WORD siz) // int m_movem(WORD inst, WORD siz) { - VALUE eval; + uint64_t eval; WORD i; WORD w; WORD rmask; @@ -881,7 +1023,7 @@ int m_movem(WORD inst, WORD siz) goto immed1; } - if (*tok >= KW_D0 && *tok <= KW_A7) + if ((*tok >= KW_D0) && (*tok <= KW_A7)) { // , ea if (reglist(&rmask) < 0) @@ -906,7 +1048,7 @@ immed1: rmask = 0; for(i=0x8000; i; i>>=1, w>>=1) - rmask = (WORD)((rmask << 1) | w & 1); + rmask = (WORD)((rmask << 1) | (w & 1)); } } else @@ -962,9 +1104,26 @@ int m_clra(WORD inst, WORD siz) return OK; } + +// +// CLR.L Dn ==> CLR.L An or MOVEQ #0,Dx +// +int m_clrd(WORD inst, WORD siz) +{ + if (!CHECK_OPTS(OPT_CLR_DX)) + inst |= a0reg; + else + inst = (a0reg << 9) | B16(01110000, 00000000); + + D_word(inst); + + return OK; +} + + //////////////////////////////////////// // -// 68020/30/40 instructions +// 68020/30/40/60 instructions // //////////////////////////////////////// @@ -973,66 +1132,105 @@ int m_clra(WORD inst, WORD siz) // int m_br30(WORD inst, WORD siz) { - VALUE v; - - if (a0exattr & DEFINED) - { - if ((a0exattr & TDB) != cursect) - //{ - //printf("m_br(): a0exattr = %X, cursect = %X, a0exval = %X, sloc = %X\n", a0exattr, cursect, a0exval, sloc); - return error(rel_error); - //} - - v = a0exval - (sloc + 2); + if (a0exattr & DEFINED) + { + if ((a0exattr & TDB) != cursect) + return error(rel_error); - D_word(inst); - D_long(v); + uint32_t v = (uint32_t)a0exval - (sloc + 2); + D_word(inst); + D_long(v); - return OK; - } - else - { - // .L - AddFixup(FU_LONG | FU_PCREL | FU_SEXT, sloc, a0expr); - D_word(inst); - return OK; - } + return OK; + } + else + { + // .L + AddFixup(FU_LONG | FU_PCREL | FU_SEXT, sloc, a0expr); + D_word(inst); + return OK; + } } + // // bfchg, bfclr, bfexts, bfextu, bfffo, bfins, bfset // (68020, 68030, 68040) // int m_bfop(WORD inst, WORD siz) { - //TODO: is this needed or can we put that in the mask in 68ktab??? - if (am0 == AREG || am0== APOSTINC || am0 == APREDEC || am0 == IMMED|| am0 == ABASE || am0 == MEMPOST || am0 == MEMPRE || am0 == PCBASE || am0 == PCMPOST || am0 == PCMPRE) - return m_badmode(inst, siz); + if ((bfval1 > 31) || (bfval1 < 0)) + return error("bfxxx offset: immediate value must be between 0 and 31"); - //First instruction word - just the opcode and first EA - //Note: both am1 is ORed because solely of bfins - maybe it's a good idea to make a dedicated function for it? - if (am1 == AM_NONE) - am1 = 0; - D_word((inst|am0|a0reg|am1|a1reg)); - ea0gen(siz); // Generate EA + // First instruction word - just the opcode and first EA + // Note: both am1 is ORed because solely of bfins - maybe it's a good idea + // to make a dedicated function for it? + if (am1 == AM_NONE) + { + am1 = 0; + } + else + { + if (bfval2 > 31 || bfval2 < 0) + return error("bfxxx width: immediate value must be between 0 and 31"); - //Second instruction word - Dest register (if exists), Do, Offset, Dw, Width - inst = bfparam1 | bfparam2; - if (am1 == DREG) - inst |= a1reg << 12; - if (am0 == DREG) - inst |= a0reg << 12; - D_word(inst); + // For Dw both immediate and register number are stuffed + // into the same field O_o + bfparam2 = (bfval2 << 0); + } + + if (bfparam1 == 0) + bfparam1 = (bfval1 << 6); + else + bfparam1 = bfval1 << 12; + + //D_word((inst | am0 | a0reg | am1 | a1reg)); + if (inst == B16(11101111, 11000000)) + { + // bfins special case + D_word((inst | am1 | a1reg)); + } + else + { + D_word((inst | am0 | a0reg)); + } + + ea0gen(siz); // Generate EA + + // Second instruction word - Dest register (if exists), Do, Offset, Dw, Width + if (inst == B16(11101111, 11000000)) + { + // bfins special case + inst = bfparam1 | bfparam2; + + if (am1 == DREG) + inst |= a0reg << 12; + + D_word(inst); + } + else + { + inst = bfparam1 | bfparam2; + + if (am1 == DREG) + inst |= a0reg << 0; + + if (am0 == DREG) + inst |= a1reg << 12; + + D_word(inst); + } return OK; } + // // bkpt (68EC000, 68010, 68020, 68030, 68040, CPU32) // int m_bkpt(WORD inst, WORD siz) { - CHECK00; + CHECK00; if (a0exattr & DEFINED) { @@ -1045,20 +1243,21 @@ int m_bkpt(WORD inst, WORD siz) inst |= a0exval; D_word(inst); } - else + else return error(undef_error); return OK; } + // // callm (68020) // int m_callm(WORD inst, WORD siz) { - CHECKNO20; + CHECKNO20; - inst |= am1; + inst |= am1; D_word(inst); if (a0exattr & DEFINED) @@ -1069,305 +1268,312 @@ int m_callm(WORD inst, WORD siz) if (a0exval > 255) return error(range_error); - inst = a0exval; + inst = (uint16_t)a0exval; D_word(inst); } - else + else return error(undef_error); - ea1gen(siz); + ea1gen(siz); return OK; } + // // cas (68020, 68030, 68040) // int m_cas(WORD inst, WORD siz) { - WORD inst2; - LONG amsk; - int modes; + WORD inst2; + LONG amsk; + int modes; + + if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) + return error(unsupport); + + switch (siz) + { + case SIZB: + inst |= 1 << 9; + break; + case SIZW: + case SIZN: + inst |= 2 << 9; + break; + case SIZL: + inst |= 3 << 9; + break; + default: + return error("bad size suffix"); + break; + } - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); + // Dc + if ((*tok < KW_D0) && (*tok > KW_D7)) + return error("CAS accepts only data registers"); - switch (siz) - { - case SIZB: - inst |= 1 << 9; - break; - case SIZW: - case SIZN: - inst |= 2 << 9; - break; - case SIZL: - inst |= 3 << 9; - break; - default: - return error("bad size suffix"); - break; - } + inst2 = (*tok++) & 7; - // Dc - if ((*tok < KW_D0) && (*tok > KW_D7)) - return error("CAS accepts only data registers"); - inst2 = (*tok++) & 7; + if (*tok++ != ',') + return error("missing comma"); - if (*tok++ != ',') - return error("missing comma"); + // Du + if ((*tok < KW_D0) && (*tok > KW_D7)) + return error("CAS accepts only data registers"); - // Du - if ((*tok < KW_D0) && (*tok > KW_D7)) - return error("CAS accepts only data registers"); - inst2 |= ((*tok++) & 7)<<6; + inst2 |= ((*tok++) & 7) << 6; - if (*tok++ != ',') - return error("missing comma"); + if (*tok++ != ',') + return error("missing comma"); - // ea - if ((modes=amode(1)) < 0) - return OK; + // ea + if ((modes = amode(1)) < 0) + return OK; + + if (modes > 1) + return error("too many ea fields"); - if (modes > 1) - return error("too many ea fields"); + if (*tok != EOL) + return error("extra (unexpected) text found"); - if (*tok!=EOL) - return error("extra (unexpected) text found"); + // Reject invalid ea modes + amsk = amsktab[am0]; - // Reject invalud ea modes - amsk = amsktab[am0]; - if (amsk&(M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE) == 0) - return error("unsupported addressing mode"); + if ((amsk & (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE)) == 0) + return error("unsupported addressing mode"); - inst |= am0 | a0reg; - D_word(inst); - D_word(inst2); - ea0gen(siz); + inst |= am0 | a0reg; + D_word(inst); + D_word(inst2); + ea0gen(siz); - return OK; + return OK; } + // // cas2 (68020, 68030, 68040) // int m_cas2(WORD inst, WORD siz) { - WORD inst2, inst3; - LONG amsk; - - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); - - switch (siz) - { - case SIZB: - inst |= 1 << 9; - break; - case SIZW: - case SIZN: - inst |= 2 << 9; - break; - case SIZL: - inst |= 3 << 9; - break; - default: - return error("bad size suffix"); - break; - } - - // Dc1 - if ((*tok < KW_D0) && (*tok > KW_D7)) - return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); - inst2 = (*tok++) & 7; - - if (*tok++ != ':') - return error("missing colon"); - - // Dc2 - if ((*tok < KW_D0) && (*tok > KW_D7)) - return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); - inst3 = (*tok++) & 7; - - if (*tok++ != ',') - return error("missing comma"); - - // Du1 - if ((*tok < KW_D0) && (*tok > KW_D7)) - return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); - inst2 |= ((*tok++) & 7)<<6; - - if (*tok++ != ':') - return error("missing colon"); - - // Du2 - if ((*tok < KW_D0) && (*tok > KW_D7)) - return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); - inst3 |= ((*tok++) & 7) << 6; - - if (*tok++ != ',') - return error("missing comma"); - - // Rn1 - if (*tok++ != '(') - return error("missing ("); - if ((*tok >= KW_D0) && (*tok <= KW_D7)) - inst2 |= (((*tok++) & 7) << 12) | (0 << 15); - else if ((*tok >= KW_A0) && (*tok <= KW_A7)) - inst2 |= (((*tok++) & 7) << 12) | (1 << 15); - else - return error("CAS accepts either data or address registers for Rn1:Rn2 pair"); - - if (*tok++ != ')') - return error("missing ("); - - if (*tok++ != ':') - return error("missing colon"); - - // Rn2 - if (*tok++ != '(') - return error("missing ("); - if ((*tok >= KW_D0) && (*tok <= KW_D7)) - inst3 |= (((*tok++) & 7) << 12) | (0 << 15); - else if ((*tok >= KW_A0) && (*tok <= KW_A7)) - inst3 |= (((*tok++) & 7) << 12) | (1 << 15); - else - return error("CAS accepts either data or address registers for Rn1:Rn2 pair"); - - if (*tok++ != ')') - return error("missing ("); - - if (*tok != EOL) - return error("extra (unexpected) text found"); - - D_word(inst); - D_word(inst2); - D_word(inst3); - - return OK; + WORD inst2, inst3; + + if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) + return error(unsupport); + + switch (siz) + { + case SIZB: + inst |= 1 << 9; + break; + case SIZW: + case SIZN: + inst |= 2 << 9; + break; + case SIZL: + inst |= 3 << 9; + break; + default: + return error("bad size suffix"); + break; + } + + // Dc1 + if ((*tok < KW_D0) && (*tok > KW_D7)) + return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); + + inst2 = (*tok++) & 7; + + if (*tok++ != ':') + return error("missing colon"); + + // Dc2 + if ((*tok < KW_D0) && (*tok > KW_D7)) + return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); + + inst3 = (*tok++) & 7; + + if (*tok++ != ',') + return error("missing comma"); + + // Du1 + if ((*tok < KW_D0) && (*tok > KW_D7)) + return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); + + inst2 |= ((*tok++) & 7) << 6; + + if (*tok++ != ':') + return error("missing colon"); + + // Du2 + if ((*tok < KW_D0) && (*tok > KW_D7)) + return error("CAS2 accepts only data registers for Dx1:Dx2 pairs"); + + inst3 |= ((*tok++) & 7) << 6; + + if (*tok++ != ',') + return error("missing comma"); + + // Rn1 + if (*tok++ != '(') + return error("missing ("); + if ((*tok >= KW_D0) && (*tok <= KW_D7)) + inst2 |= (((*tok++) & 7) << 12) | (0 << 15); + else if ((*tok >= KW_A0) && (*tok <= KW_A7)) + inst2 |= (((*tok++) & 7) << 12) | (1 << 15); + else + return error("CAS accepts either data or address registers for Rn1:Rn2 pair"); + + if (*tok++ != ')') + return error("missing ("); + + if (*tok++ != ':') + return error("missing colon"); + + // Rn2 + if (*tok++ != '(') + return error("missing ("); + if ((*tok >= KW_D0) && (*tok <= KW_D7)) + inst3 |= (((*tok++) & 7) << 12) | (0 << 15); + else if ((*tok >= KW_A0) && (*tok <= KW_A7)) + inst3 |= (((*tok++) & 7) << 12) | (1 << 15); + else + return error("CAS accepts either data or address registers for Rn1:Rn2 pair"); + + if (*tok++ != ')') + return error("missing ("); + + if (*tok != EOL) + return error("extra (unexpected) text found"); + + D_word(inst); + D_word(inst2); + D_word(inst3); + + return OK; } + // // cmp2 (68020, 68030, 68040, CPU32) // int m_cmp2(WORD inst, WORD siz) { - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); - - switch (siz&15) - { - case SIZW: - case SIZN: - inst |= 1 << 9; - break; - case SIZL: - inst |= 2 << 9; - break; - default: - // SIZB - break; - } - - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr - - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; - - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } - - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr - - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); - - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 - - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } - - // If we're called from chk2 then bit 11 of size will be set. - // This is just a dumb mechanism to pass this, required by the extension word. - // (you might have noticed the siz&15 thing above!) - inst = (a1reg << 12)|(siz&(1<<11)); - if (am1 == AREG) - inst |= 1 << 15; + if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) + return error(unsupport); + + switch (siz & 0x000F) + { + case SIZW: + case SIZN: + inst |= 1 << 9; + break; + case SIZL: + inst |= 2 << 9; + break; + default: + // SIZB + break; + } + + WORD flg = inst; // Save flag bits + inst &= ~0x3F; // Clobber flag bits in instr + + // Install "standard" instr size bits + if (flg & 4) + inst |= siz_6[siz]; + + if (flg & 16) + { + // OR-in register number + if (flg & 8) + inst |= reg_9[a1reg]; // ea1reg in bits 9..11 + else + inst |= reg_9[a0reg]; // ea0reg in bits 9..11 + } + + if (flg & 1) + { + // Use am1 + inst |= am1 | a1reg; // Get ea1 into instr + D_word(inst); // Deposit instr + + // Generate ea0 if requested + if (flg & 2) + ea0gen(siz); + + ea1gen(siz); // Generate ea1 + } + else + { + // Use am0 + inst |= am0 | a0reg; // Get ea0 into instr + D_word(inst); // Deposit instr + ea0gen(siz); // Generate ea0 + + // Generate ea1 if requested + if (flg & 2) + ea1gen(siz); + } + + // If we're called from chk2 then bit 11 of size will be set. This is just + // a dumb mechanism to pass this, required by the extension word. (You might + // have noticed the siz & 15 thing above!) + inst = (a1reg << 12) | (siz & (1 << 11)); + + if (am1 == AREG) + inst |= 1 << 15; D_word(inst); return OK; } + // // chk2 (68020, 68030, 68040, CPU32) // int m_chk2(WORD inst, WORD siz) { - return m_cmp2(inst, siz | (1 << 11)); + return m_cmp2(inst, siz | (1 << 11)); } + // -// cpbcc(68020, 68030) +// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc)) +// TODO: Better checks for different instructions? // int m_cpbr(WORD inst, WORD siz) { - if ((activecpu & (CPU_68020 | CPU_68030)) == 0) - return error(unsupport); - - VALUE v; + if ((activecpu & (CPU_68020 | CPU_68030)) && (!activefpu == 0)) + return error(unsupport); if (a0exattr & DEFINED) { if ((a0exattr & TDB) != cursect) -//{ -//printf("m_br(): a0exattr = %X, cursect = %X, a0exval = %X, sloc = %X\n", a0exattr, cursect, a0exval, sloc); return error(rel_error); -//} - v = a0exval - (sloc + 2); + uint32_t v = (uint32_t)a0exval - (sloc + 2); // Optimize branch instr. size if (siz == SIZL) { - if (v != 0 && v + 0x8000 < 0x10000) + if ((v != 0) && ((v + 0x8000) < 0x10000)) { - inst |= (1 << 6); + inst |= (1 << 6); D_word(inst); - WARNING(check what s "optional coprocessor-defined extension words!") D_long(v); return OK; } } - else // SIZW/SIZN + else // SIZW/SIZN { - if (v + 0x8000 >= 0x10000) + if ((v + 0x8000) >= 0x10000) return error(range_error); + D_word(inst); - WARNING(check what s "optional coprocessor-defined extension words!") D_word(v); } @@ -1379,14 +1585,14 @@ int m_cpbr(WORD inst, WORD siz) if (siz == SIZL) { // .L - D_word(inst); - AddFixup(FU_LONG | FU_PCREL | FU_SEXT, sloc, a0expr); - D_long(0); + D_word(inst); + AddFixup(FU_LONG | FU_PCREL | FU_SEXT, sloc, a0expr); + D_long(0); return OK; } else { - // .W + // .W D_word(inst); AddFixup(FU_WORD | FU_PCREL | FU_SEXT, sloc, a0expr); D_word(0); @@ -1395,457 +1601,282 @@ int m_cpbr(WORD inst, WORD siz) return OK; } + // // cpdbcc(68020, 68030) // int m_cpdbr(WORD inst, WORD siz) { - if ((activecpu & (CPU_68020 | CPU_68030)) == 0) - return error(unsupport); + CHECK00; - return error("Not implemented yet."); + uint32_t v; + WORD condition = inst & 0x1F; // Grab condition sneakily placed in the lower 5 bits of inst + inst &= 0xFFE0; // And then mask them out - you ain't seen me, roit? - //return OK; -} + inst |= (1 << 9); // Bolt on FPU id + inst |= a0reg; -// -// divs.l -// -int m_divs(WORD inst, WORD siz) -{ - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); - - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr - - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; - - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } - - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr - - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); - - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 - - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } - - //D_word(inst); - //ea0gen(siz); - inst=a1reg+(a2reg<<12)+(1<<11); D_word(inst); - - return OK; -} -// -// muls.l -// -int m_muls(WORD inst, WORD siz) -{ - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); - - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr - - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; - - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } - - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr - - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); - - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 - - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } - - //D_word(inst); - //ea0gen(siz); - inst=a1reg+(a2reg<<12)+(1<<11); - inst|=mulmode; // add size bit - D_word(inst); - - return OK; -} -// -// divu.l -// -int m_divu(WORD inst, WORD siz) -{ - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); - //WARNING("divu.l d0,d1 is actually divul.l d0,d1:d1!!!") + D_word(condition); - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr - - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; - - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } - - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr + if (a1exattr & DEFINED) + { + if ((a1exattr & TDB) != cursect) + return error(rel_error); - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); + v = (uint32_t)a1exval - sloc; - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 + if (v + 0x8000 > 0x10000) + return error(range_error); - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } + D_word(v); + } + else + { + AddFixup(FU_WORD | FU_PCREL | FU_ISBRA, sloc, a1expr); + D_word(0); + } - //D_word(inst); - //ea0gen(siz); - inst=a1reg+(a2reg<<12); - D_word(inst); - - return OK; -} -// -// mulu.l -// -int m_mulu(WORD inst, WORD siz) -{ - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); - - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr - - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; - - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } - - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr - - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); - - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 - - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } - - //D_word(inst); - //ea0gen(siz); - inst=a1reg+(a2reg<<12); - inst|=mulmode; // add size bit - D_word(inst); - return OK; + } + // -// divsl.l +// muls.l / divs.l / divu.l / mulu.l (68020+) // -int m_divsl(WORD inst, WORD siz) +int m_muls(WORD inst, WORD siz) { - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); - - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr - - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; - - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } - - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr + if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) + return error(unsupport); - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); + WORD flg = inst; // Save flag bits + inst &= ~0x33F; // Clobber flag and extension bits in instr - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 + // Install "standard" instr size bits + if (flg & 4) + inst |= siz_6[siz]; - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } + if (flg & 16) + { + // OR-in register number + if (flg & 8) + inst |= reg_9[a1reg]; // ea1reg in bits 9..11 + else + inst |= reg_9[a0reg]; // ea0reg in bits 9..11 + } - //D_word(inst); - //ea0gen(siz); - inst=a1reg+(a2reg<<12)+(1<<11)+(1<<10); - D_word(inst); + // Regarding extension word: bit 11 is signed/unsigned selector + // bit 10 is 32/64 bit selector + // Both of these are packed in bits 9 and 8 of the instruction + // field in 68ktab. Extra compilcations arise from the fact we + // have to distinguish between divu/s.l Dn,Dm (which is encoded + // as divu/s.l Dn,Dm:Dm) and divu/s.l Dn,Dm:Dx - the first is + // 32 bit while the second 64 bit - return OK; -} + if (flg & 1) + { + // Use am1 + inst |= am1 | a1reg; // Get ea1 into instr + D_word(inst); // Deposit instr -// -// divul.l -// -int m_divul(WORD inst, WORD siz) -{ - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); + // Extension word + if (a1reg == a2reg) + inst = a1reg + (a2reg << 12) + ((flg & 0x200) << 2); + else + inst = a1reg + (a2reg << 12) + ((flg & 0x300) << 2); - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr + D_word(inst); - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; + // Generate ea0 if requested + if (flg & 2) + ea0gen(siz); - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } + ea1gen(siz); // Generate ea1 - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr + return OK; + } + else + { + // Use am0 + inst |= am0 | a0reg; // Get ea0 into instr + D_word(inst); // Deposit instr - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); + // Extension word + if (a1reg == a2reg) + inst = a1reg + (a2reg << 12) + ((flg & 0x200) << 2); + else + inst = a1reg + (a2reg << 12) + ((flg & 0x300) << 2); - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 + D_word(inst); - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } + ea0gen(siz); // Generate ea0 - //D_word(inst); - //ea0gen(siz); - inst=a1reg+(a2reg<<12)+(1<<10); - D_word(inst); + // Generate ea1 if requested + if (flg & 2) + ea1gen(siz); - return OK; + return OK; + } } + // // move16 (ax)+,(ay)+ // int m_move16a(WORD inst, WORD siz) { - if ((activecpu & (CPU_68040 | CPU_68060)) == 0) - return error(unsupport); + if ((activecpu & (CPU_68040 | CPU_68060)) == 0) + return error(unsupport); - inst|=a0reg; + inst |= a0reg; D_word(inst); - inst=(1<<15)+(a1reg<<12); + inst = (1 << 15) + (a1reg << 12); D_word(inst); return OK; } + // // move16 with absolute address // int m_move16b(WORD inst, WORD siz) { - if ((activecpu & (CPU_68040 | CPU_68060)) == 0) - return error(unsupport); + if ((activecpu & (CPU_68040 | CPU_68060)) == 0) + return error(unsupport); - int v; - inst|=a1reg; + int v; + inst |= a1reg; D_word(inst); - if (am0==APOSTINC) - if (am1==AIND) + if (am0 == APOSTINC) + { + if (am1 == AIND) return error("Wasn't this suppose to call m_move16a???"); else { - //move16 (ax)+,(xxx).L - inst|=0<<3; - v=a1exval; + // move16 (ax)+,(xxx).L + inst |= 0 << 3; + v = (int)a1exval; } - else if (am0==ABSL) - if (am1==AIND) + } + else if (am0 == ABSL) + { + if (am1 == AIND) { - //move16 (xxx).L,(ax)+ - inst|=1<<3; - v=a0exval; + // move16 (xxx).L,(ax)+ + inst |= 1 << 3; + v = (int)a0exval; } - else //APOSTINC + else // APOSTINC { - //move16 (xxx).L,(ax) - inst|=3<<3; - v=a0exval; + // move16 (xxx).L,(ax) + inst |= 3 << 3; + v = (int)a0exval; } - else if (am0==AIND) + } + else if (am0 == AIND) { - //move16 (ax),(xxx).L - inst|=2<<3; - v=a1exval; + // move16 (ax),(xxx).L + inst |= 2 << 3; + v = (int)a1exval; } + D_word(inst); D_long(v); + return OK; } + // -// pack/unpack +// pack/unpack (68020/68030/68040) // int m_pack(WORD inst, WORD siz) { - if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0) - return error(unsupport); + CHECK00; + + if (siz != SIZN) + return error("bad size suffix"); + + if (*tok >= KW_D0 && *tok <= KW_D7) + { + // Dx,Dy,# + inst |= (0 << 3); // R/M + inst |= (*tok++ & 7); + + if (*tok != ',' && tok[2] != ',') + return error("missing comma"); + + if (tok[1] < KW_D0 && tok[1] > KW_D7) + return error(syntax_error); + + inst |= ((tok[1] & 7)<<9); + tok = tok + 3; + D_word(inst); + // Fall through for adjustment (common in both valid cases) + } + else if (*tok == '-') + { + // -(Ax),-(Ay),# + inst |= (1 << 3); // R/M + tok++; // eat the minus + + if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ',')) + return error(syntax_error); + + if (tok[1] < KW_A0 && tok[1] > KW_A7) + return error(syntax_error); + + if (tok[5] < KW_A0 && tok[6] > KW_A7) + return error(syntax_error); + + inst |= ((tok[1] & 7) << 0); + inst |= ((tok[6] & 7) << 9); + tok = tok + 9; + D_word(inst); + // Fall through for adjustment (common in both valid cases) + } + else + return error("invalid syntax"); + + if ((*tok != CONST) && (*tok != SYMBOL) && (*tok != '-')) + return error(syntax_error); + + if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR) + return ERROR; + + if ((a0exattr & DEFINED) == 0) + return error(undef_error); + + if (a0exval + 0x8000 > 0x10000) + return error(""); - WARNING(Parsing stuff by hand here might be better) + if (*tok != EOL) + return error(extra_stuff); - //if (am0==DREG && am1==DREG) - //{ - // inst|=(1<<3)+(a0reg<<9)+(a1reg); - //} - //else if (am0==APREDEC && am1==APREDEC) - //{ - // inst|=(a0reg<<9)+(a1reg); - //} - //else - // return error("Only allowed combinations for pack/unpack are -(ax),-(ay) and dx,dy."); - // - //D_word(inst); + D_word((a0exval & 0xFFFF)); return OK; } + // // rtm Rn // int m_rtm(WORD inst, WORD siz) { - CHECKNO20; + CHECKNO20; - if (am0==DREG) + if (am0 == DREG) { - inst|=a0reg; + inst |= a0reg; } - else if (am0==AREG) + else if (am0 == AREG) { - inst|=(1<<3)+a0reg; + inst |= (1 << 3) + a0reg; } else return error("rtm only allows data or address registers."); @@ -1855,28 +1886,29 @@ int m_rtm(WORD inst, WORD siz) return OK; } + // // rtd #n // int m_rtd(WORD inst, WORD siz) { - CHECK00; + CHECK00; - if (a0exattr & DEFINED) - { - if (a0exattr & TDB) - return error(abs_error); + if (a0exattr & DEFINED) + { + if (a0exattr & TDB) + return error(abs_error); - if (a0exval+0x8000 <= 0x7fff) - return error(range_error); + if ((a0exval + 0x8000) <= 0x7FFF) + return error(range_error); - D_word(inst); - D_word(a0exval); - } - else - return error(undef_error); + D_word(inst); + D_word(a0exval); + } + else + return error(undef_error); - return OK; + return OK; } @@ -1885,30 +1917,28 @@ int m_rtd(WORD inst, WORD siz) // int m_trapcc(WORD inst, WORD siz) { - CHECK00; - - if (am0==AM_NONE) + CHECK00; + + if (am0 == AM_NONE) { D_word(inst); } - else if (am0==IMMED) + else if (am0 == IMMED) { - if (siz==SIZW) - { - if (a0exval<0x10000) + if (siz == SIZW) { - inst|=2; - D_word(inst); - D_word(a0exval); + if (a0exval < 0x10000) + { + inst |= 2; + D_word(inst); + D_word(a0exval); + } + else + return error("Immediate value too big"); } - else - { - return error("Immediate value too big"); - } - } - else //DOTL - { - inst|=3; + else //DOTL + { + inst |= 3; D_word(inst); D_long(a0exval); } @@ -1919,55 +1949,83 @@ int m_trapcc(WORD inst, WORD siz) return OK; } + // -// cinv (68040) +// cinvl/p/a (68040/68060) // int m_cinv(WORD inst, WORD siz) { - CHECKNO40; + CHECKNO40; + + if (am1 == AM_NONE) + inst |= (0 << 6) | (a1reg); + switch (a0reg) + { + case 0: // KW_IC40 + inst |= (2 << 6) | (a1reg); + break; + case 1: // KW_DC40 + inst |= (1 << 6) | (a1reg); + break; + case 2: // KW_BC40 + inst |= (3 << 6) | (a1reg); + break; + } + + D_word(inst); + return OK; +} - WARNING("cinvl ,(an) / cinvp ,(an) / cinva should work!") - if (am0==AM_NONE) - inst|=(0<<6)|(a1reg); - else if (am0==KW_IC40) - inst|=(2<<6)|(a1reg); - else if (am0==KW_DC40) - inst|=(1<<6)|(a1reg); - else if (am0==KW_BC40) - inst|=(3<<6)|(a1reg); +int m_fpusavrest(WORD inst, WORD siz) +{ + inst |= am0 | a0reg; D_word(inst); + ea0gen(siz); + return OK; - } + // -// cpRESTORE (68020, 68030) +// cpSAVE/cpRESTORE (68020, 68030) // int m_cprest(WORD inst, WORD siz) { - if (activecpu & !(CPU_68020|CPU_68030)) - return error(unsupport); + if (activecpu & !(CPU_68020 | CPU_68030)) + return error(unsupport); - inst|=am0|a0reg; - D_word(inst); - ea0gen(siz); + return m_fpusavrest(inst, siz); - return OK; } + +// +// FSAVE/FRESTORE (68040, 68060) +// +int m_frestore(WORD inst, WORD siz) +{ + if ((!(activecpu & (CPU_68040 | CPU_68060))) || + (activefpu&(FPU_68881 | FPU_68882))) + return error(unsupport); + + return m_fpusavrest(inst, siz); +} + + // -// movec (68010, 68020, 68030, 68040, CPU32) +// movec (68010, 68020, 68030, 68040, 68060, CPU32) // int m_movec(WORD inst, WORD siz) { - CHECK00; + CHECK00; - if (am0 == DREG || am0 == AREG) + if (am0 == DREG || am0 == AREG) { // movec Rn,Rc - inst|=1; + inst |= 1; D_word(inst); + if (am0 == DREG) { inst = (0 << 15) + (a0reg << 12) + CREGlut[a1reg]; @@ -1983,6 +2041,7 @@ int m_movec(WORD inst, WORD siz) { // movec Rc,Rn D_word(inst); + if (am1 == DREG) { inst = (0 << 15) + (a1reg << 12) + CREGlut[a0reg]; @@ -1998,98 +2057,85 @@ int m_movec(WORD inst, WORD siz) return OK; } + // // moves (68010, 68020, 68030, 68040, CPU32) // int m_moves(WORD inst, WORD siz) { - if (activecpu & !(CPU_68020 | CPU_68030 | CPU_68040)) - return error(unsupport); - - if (siz == SIZB) - { - inst |= 0 << 6; - } - else if (siz == SIZL) - { - inst |= 2 << 6; - } - else // SIZW/SIZN - { - inst |= 1 << 6; - } - - if (am0 == DREG) - { - inst |= am1 | a1reg; - D_word(inst); - inst = (a0reg << 12) | (1 << 11) | (0 << 15); - D_word(inst); - } - else if (am0 == AREG) - { - inst |= am1 | a1reg; - D_word(inst); - inst = (a0reg << 12) | (1 << 11) | (1 << 15); - D_word(inst); - } - else - { - if (am1 == DREG) - { - inst |= am0 | a0reg; - D_word(inst); - inst = (a1reg << 12) | (0 << 11) | (0 << 15); - D_word(inst); - } - else - { - inst |= am0 | a0reg; - D_word(inst); - inst = (a1reg << 12) | (0 << 11) | (1 << 15); - D_word(inst); - } - } - - return OK; - + if (activecpu & !(CPU_68020 | CPU_68030 | CPU_68040)) + return error(unsupport); + + if (siz == SIZB) + inst |= 0 << 6; + else if (siz == SIZL) + inst |= 2 << 6; + else // SIZW/SIZN + inst |= 1 << 6; + + if (am0 == DREG) + { + inst |= am1 | a1reg; + D_word(inst); + inst = (a0reg << 12) | (1 << 11) | (0 << 15); + D_word(inst); + } + else if (am0 == AREG) + { + inst |= am1 | a1reg; + D_word(inst); + inst = (a0reg << 12) | (1 << 11) | (1 << 15); + D_word(inst); + } + else + { + if (am1 == DREG) + { + inst |= am0 | a0reg; + D_word(inst); + inst = (a1reg << 12) | (0 << 11) | (0 << 15); + D_word(inst); + } + else + { + inst |= am0 | a0reg; + D_word(inst); + inst = (a1reg << 12) | (0 << 11) | (1 << 15); + D_word(inst); + } + } + + return OK; } + // // PBcc (MC68851) // int m_pbcc(WORD inst, WORD siz) { - CHECKNO20; - return error("Not implemented yet."); + CHECKNO20; + return error("Not implemented yet."); } -// -// pflusha (68030) -// -int m_pflusha(WORD inst, WORD siz) -{ - CHECKNO30; - - D_word(inst); - inst=((1 << 13) | (1 << 10)) | (0 << 5) | 0; - D_word(inst); - return OK; -} // -// pflush (68030, 68040, 68060) +// pflusha (68030, 68040) // -int m_pflush(WORD inst, WORD siz) +int m_pflusha(WORD inst, WORD siz) { if (activecpu == CPU_68030) { D_word(inst); - D_word(((1 << 13) | (1 << 10)) | (0 << 5) | 0); + inst = (1 << 13) | (1 << 10) | (0 << 5) | 0; + D_word(inst); + return OK; } - else if (activecpu == CPU_68040 || activecpu == CPU_68060) + else if (activecpu == CPU_68040) { - D_word(0xf918); + inst = B16(11110101, 00011000); + D_word(inst); + return OK; } else return error(unsupport); @@ -2097,228 +2143,471 @@ int m_pflush(WORD inst, WORD siz) return OK; } + // -// pflushr (68551) +// pflush (68030, 68040, 68060) // -int m_pflushr(WORD inst, WORD siz) +int m_pflush(WORD inst, WORD siz) { - CHECKNO20; - - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr - - // Install "standard" instr size bits - if (flg & 4) - inst |= siz_6[siz]; + if (activecpu == CPU_68030) + { + // PFLUSH FC, MASK + // PFLUSH FC, MASK, < ea > + WORD mask, fc; - if (flg & 16) - { - // OR-in register number - if (flg & 8) - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - else - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } + switch ((int)*tok) + { + case '#': + tok++; - if (flg & 1) - { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr + if (*tok != CONST && *tok != SYMBOL) + return error("function code should be an expression"); + + if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR) + return ERROR; + + if ((a0exattr & DEFINED) == 0) + return error("function code immediate should be defined"); + + if (a0exval > 7) + return error("function code out of range (0-7)"); + + fc = (uint16_t)a0exval; + break; + case KW_D0: + case KW_D1: + case KW_D2: + case KW_D3: + case KW_D4: + case KW_D5: + case KW_D6: + case KW_D7: + fc = (1 << 4) | (*tok++ & 7); + break; + case KW_SFC: + fc = 0; + tok++; + break; + case KW_DFC: + fc = 1; + tok++; + break; + default: + return error(syntax_error); + } - // Generate ea0 if requested - if (flg & 2) - ea0gen(siz); + if (*tok++ != ',') + return error("comma exptected"); - ea1gen(siz); // Generate ea1 - } - else - { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 + if (*tok++ != '#') + return error("mask should be an immediate value"); - // Generate ea1 if requested - if (flg & 2) - ea1gen(siz); - } + if (*tok != CONST && *tok != SYMBOL) + return error("mask is supposed to be immediate"); - D_word(B16(10100000, 00000000)); -} + if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR) + return ERROR; -// -// ploadr, ploadw (68030) -// -int m_pload(WORD inst, WORD siz) -{ - CHECKNO30; - return error("Not implemented yet."); -} + if ((a0exattr & DEFINED) == 0) + return error("mask immediate value should be defined"); -// -// pmove (68030) -// -int m_pmove(WORD inst, WORD siz) -{ - int inst2,reg; + if (a0exval > 7) + return error("function code out of range (0-7)"); - CHECKNO30; + mask = (uint16_t)a0exval << 5; - inst2 = inst&(1 << 8); //Copy the flush bit over to inst2 in case we're called from m_pmovefd - inst &= ~(1 << 8); //And mask it out - if (am0 == CREG) - { - reg=a0reg; - inst2|= (1<<9); + if (*tok == EOL) + { + // PFLUSH FC, MASK + D_word(inst); + inst = (1 << 13) | fc | mask | (4 << 10); + D_word(inst); + return OK; + } + else if (*tok == ',') + { + // PFLUSH FC, MASK, < ea > + tok++; + + if (amode(0) == ERROR) + return ERROR; + + if (*tok != EOL) + return error(extra_stuff); + + if (am0 == AIND || am0 == ABSW || am0 == ABSL || am0 == ADISP || am0 == ADISP || am0 == AINDEXED || am0 == ABASE || am0 == MEMPOST || am0 == MEMPRE) + { + inst |= am0 | a0reg; + D_word(inst); + inst = (1 << 13) | fc | mask | (6 << 10); + D_word(inst); + ea0gen(siz); + return OK; + } + else + return error("unsupported addressing mode"); + + } + else + return error(syntax_error); + + return OK; + } + else if (activecpu == CPU_68040 || activecpu == CPU_68060) + { + // PFLUSH(An) + // PFLUSHN(An) + if (*tok != '(' && tok[2] != ')') + return error(syntax_error); + + if (tok[1] < KW_A0 && tok[1] > KW_A7) + return error("expected (An)"); + + if ((inst & 7) == 7) + // With pflushn/pflush there's no easy way to distinguish between + // the two in 68040 mode. Ideally the opcode bitfields would have + // been hardcoded in 68ktab but there is aliasing between 68030 + // and 68040 opcode. So we just set the 3 lower bits to 1 in + // pflushn inside 68ktab and detect it here. + inst = (inst & 0xff8) | 8; + + inst |= (tok[1] & 7) | (5 << 8); + + if (tok[3] != EOL) + return error(extra_stuff); + + D_word(inst); + } + else + return error(unsupport); + + return OK; +} + + +// +// pflushan (68040, 68060) +// +int m_pflushan(WORD inst, WORD siz) +{ + if (activecpu == CPU_68040 || activecpu == CPU_68060) + D_word(inst); + + return OK; +} + + +// +// pflushr (68851) +// +int m_pflushr(WORD inst, WORD siz) +{ + CHECKNO20; + + WORD flg = inst; // Save flag bits + inst &= ~0x3F; // Clobber flag bits in instr + + // Install "standard" instr size bits + if (flg & 4) + inst |= siz_6[siz]; + + if (flg & 16) + { + // OR-in register number + if (flg & 8) + inst |= reg_9[a1reg]; // ea1reg in bits 9..11 + else + inst |= reg_9[a0reg]; // ea0reg in bits 9..11 + } + + if (flg & 1) + { + // Use am1 + inst |= am1 | a1reg; // Get ea1 into instr + D_word(inst); // Deposit instr + + // Generate ea0 if requested + if (flg & 2) + ea0gen(siz); + + ea1gen(siz); // Generate ea1 + } + else + { + // Use am0 + inst |= am0 | a0reg; // Get ea0 into instr + D_word(inst); // Deposit instr + ea0gen(siz); // Generate ea0 + + // Generate ea1 if requested + if (flg & 2) + ea1gen(siz); + } + + D_word(B16(10100000, 00000000)); + return OK; +} + + +// +// ploadr, ploadw (68030) +// +int m_pload(WORD inst, WORD siz, WORD extension) +{ + // TODO: 68851 support is not added yet. + // None of the ST series of computers had a 68020 + 68851 socket and since + // this is an Atari targetted assembler... + CHECKNO30; + + inst |= am1; + D_word(inst); + + switch (am0) + { + case CREG: + if (a0reg == KW_SFC - KW_SFC) + inst = 0; + else if (a0reg == KW_DFC - KW_SFC) + inst = 1; + else + return error("illegal control register specified"); + + break; + case DREG: + inst = (1 << 3) | a0reg; + break; + case IMMED: + if ((a0exattr & DEFINED) == 0) + return error("constant value must be defined"); + + inst = (2 << 3) | (uint16_t)a0exval; + break; + } + + inst |= extension | (1 << 13); + D_word(inst); + + ea1gen(siz); + + return OK; +} + + +int m_ploadr(WORD inst, WORD siz) +{ + return m_pload(inst, siz, 1 << 9); +} + + +int m_ploadw(WORD inst, WORD siz) +{ + return m_pload(inst, siz, 0 << 9); +} + + +// +// pmove (68030/68851) +// +int m_pmove(WORD inst, WORD siz) +{ + int inst2,reg; + + // TODO: 68851 support is not added yet. None of the ST series of + // computers had a 68020 + 68851 socket and since this is an Atari + // targetted assembler.... (same for 68EC030) + CHECKNO30; + + inst2 = inst & (1 << 8); // Copy the flush bit over to inst2 in case we're called from m_pmovefd + inst &= ~(1 << 8); // And mask it out + + if (am0 == CREG) + { + reg = a0reg; + inst2 |= (1 << 9); } else if (am1 == CREG) { reg = a1reg; - inst2|=0; + inst2 |= 0; } else return error("pmove sez: Wut?"); - if ((reg == KW_URP-KW_SFC || reg == KW_SRP-KW_SFC) && ((siz != SIZD) && (siz!=SIZN))) + // The instruction is a quad-word (8 byte) operation + // for the CPU root pointer and the supervisor root pointer. + // It is a long-word operation for the translation control register + // and the transparent translation registers(TT0 and TT1). + // It is a word operation for the MMU status register. + + if (((reg == (KW_URP - KW_SFC)) || (reg == (KW_SRP - KW_SFC))) + && ((siz != SIZD) && (siz != SIZN))) return error(siz_error); - if ((reg == KW_TC-KW_SFC || reg == KW_TT0-KW_SFC || reg == KW_TT1-KW_SFC) && ((siz != SIZL)&&(siz!=SIZN))) + + if (((reg == (KW_TC - KW_SFC)) || (reg == (KW_TT0 - KW_SFC)) || (reg == (KW_TT1 - KW_SFC))) + && ((siz != SIZL) && (siz != SIZN))) return error(siz_error); - if ((reg == KW_MMUSR-KW_SFC) && ((siz != SIZW)&&(siz!=SIZN))) + + if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN))) return error(siz_error); - WARNING(Not all addressing modes are legal here!) - if (am0 == CREG) - { - inst|=am1; - D_word(inst); - ea1gen(siz); - } - else if (am1 == CREG) - { - inst|=am0; - D_word(inst); - ea0gen(siz); - } + if (am0 == CREG) + { + inst |= am1 | a1reg; + D_word(inst); + } + else if (am1 == CREG) + { + inst |= am0 | a0reg; + D_word(inst); + } - switch (reg) + switch (reg + KW_SFC) { - case (KW_URP-KW_SFC): - inst2 |= (3 << 10) + (2 << 13); break; - case (KW_SRP-KW_SFC): - inst2 |= (2 << 10) + (2 << 13); break; - case (KW_TC-KW_SFC): - inst2 |= (0 << 10) + (2 << 13); break; - case (KW_TT0-KW_SFC): + case KW_TC: + inst2 |= (0 << 10) + (1 << 14); break; + case KW_SRP: + inst2 |= (2 << 10) + (1 << 14); break; + case KW_CRP: + inst2 |= (3 << 10) + (1 << 14); break; + case KW_TT0: inst2 |= (2 << 10) + (0 << 13); break; - case (KW_TT1-KW_SFC): + case KW_TT1: inst2 |= (3 << 10) + (0 << 13); break; - case (KW_MMUSR-KW_SFC): - inst2 |= (3 << 10) + (3 << 13); break; - case (KW_CRP-KW_SFC) : //68851 only - inst2 |= (3 << 10) + (2 << 13); break; + case KW_MMUSR: + if (am0 == CREG) + inst2 |= (1 << 9) + (3 << 13); + else + inst2 |= (0 << 9) + (3 << 13); + break; + default: + return error("unsupported register"); + break; } D_word(inst2); + if (am0 == CREG) + ea1gen(siz); + else if (am1 == CREG) + ea0gen(siz); + return OK; } + // // pmovefd (68030) // int m_pmovefd(WORD inst, WORD siz) { - CHECKNO30; + CHECKNO30; - return m_pmove(inst|(1<<8),siz); + return m_pmove(inst | (1 << 8), siz); } + // // ptrapcc (68851) // -int m_ptrapbs(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000000)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000000)); D_long(a0exval); } return OK; } -int m_ptrapbc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000001)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000001)); D_long(a0exval); } return OK; } -int m_ptrapls(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000010)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000010)); D_long(a0exval); } return OK; } -int m_ptraplc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000011)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000011)); D_long(a0exval); } return OK; } -int m_ptrapss(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000100)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000100)); D_long(a0exval); } return OK; } -int m_ptrapsc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000101)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000101)); D_long(a0exval); } return OK; } -int m_ptrapas(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000110)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000110)); D_long(a0exval); } return OK; } -int m_ptrapac(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000111)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000111)); D_long(a0exval); } return OK; } -int m_ptrapws(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001000)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001000)); D_long(a0exval); } return OK; } -int m_ptrapwc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001001)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001001)); D_long(a0exval); } return OK; } -int m_ptrapis(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001010)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001010)); D_long(a0exval); } return OK; } -int m_ptrapic(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001011)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001011)); D_long(a0exval); } return OK; } -int m_ptrapgc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001100)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001100)); D_long(a0exval); } return OK; } -int m_ptrapgs(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001101)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001101)); D_long(a0exval); } return OK; } -int m_ptrapcs(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001110)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001110)); D_long(a0exval); } return OK; } -int m_ptrapcc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001111)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001111)); D_long(a0exval); } return OK; } -int m_ptrapbsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000000)); return OK; } -int m_ptrapbcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000001)); return OK; } -int m_ptraplsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000010)); return OK; } -int m_ptraplcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000011)); return OK; } -int m_ptrapssn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000100)); return OK; } -int m_ptrapscn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000101)); return OK; } -int m_ptrapasn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000110)); return OK; } -int m_ptrapacn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000111)); return OK; } -int m_ptrapwsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001000)); return OK; } -int m_ptrapwcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001001)); return OK; } -int m_ptrapisn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001010)); return OK; } -int m_ptrapicn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001011)); return OK; } -int m_ptrapgsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001100)); return OK; } -int m_ptrapgcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001101)); return OK; } -int m_ptrapcsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001110)); return OK; } -int m_ptrapccn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001111)); return OK; } +int m_ptrapcc(WORD inst, WORD siz) +{ + CHECKNO20; + // We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4), + // so we need to extract them first and fill in the clobbered bits. + WORD opcode = inst & 0x1F; + inst = (inst & 0xFFE0) | (0x18); + + if (siz == SIZW) + { + inst |= 2; + D_word(inst); + D_word(opcode); + D_word(a0exval); + } + else if (siz == SIZL) + { + inst |= 3; + D_word(inst); + D_word(opcode); + D_long(a0exval); + } + else if (siz == SIZN) + { + inst |= 4; + D_word(inst); + D_word(opcode); + } + + return OK; +} + // // ptestr, ptestw (68030) // int m_ptest(WORD inst, WORD siz) { - CHECKNO30; + CHECKNO30; + if (activecpu == CPU_68030) return error("Not implemented yet."); else if (activecpu == CPU_68040) return error("Not implemented yet."); + return ERROR; } +////////////////////////////////////////////////////////////////////////////// +// +// 68020/30/40/60 instructions +// Note: the map of which instructions are allowed on which CPUs came from the +// 68060 manual, section D-1 (page 392 of the PDF). The current implementation +// is missing checks for the EC models which have a simplified FPU. +// +////////////////////////////////////////////////////////////////////////////// + + #define FPU_NOWARN 0 -#define FPU_P_EMUL 1 -#define FPU_P2_EMU 2 -#define FPU_FPSP 4 +#define FPU_FPSP 1 + // // Generate a FPU opcode // static inline int gen_fpu(WORD inst, WORD siz, WORD opmode, WORD emul) { - if (am0 0x10000) + if ((v + 0x8000) > 0x10000) return error(range_error); D_word(v); @@ -2476,784 +2804,1009 @@ int m_fdbcc(WORD inst, WORD siz) D_word(0); } + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + return OK; } - - // -// fdiv (6888X, 68040) +// fdiv (6888X, 68040, 68060) // int m_fdiv(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100000), FPU_NOWARN); } + + +// +// fsdiv (68040, 68060) +// int m_fsdiv(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100000), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + + +// +// fddiv (68040, 68060) +// int m_fddiv(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100100), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + // -// fetox (6888X, 68040FPSP) +// fetox (6888X, 68040FPSP, 68060FPSP) // int m_fetox(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010000), FPU_FPSP); } + // -// fetoxm1 (6888X, 68040FPSP) +// fetoxm1 (6888X, 68040FPSP, 68060FPSP) // int m_fetoxm1(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001000), FPU_FPSP); } + // -// fgetexp (6888X, 68040FPSP) +// fgetexp (6888X, 68040FPSP, 68060FPSP) // int m_fgetexp(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00011110), FPU_FPSP); } + // -// fgetman (6888X, 68040FPSP) +// fgetman (6888X, 68040FPSP, 68060FPSP) // int m_fgetman(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00011111), FPU_FPSP); } + // -// fint (6888X, 68040FPSP) +// fint (6888X, 68040FPSP, 68060) // int m_fint(WORD inst, WORD siz) { - if (am1==AM_NONE) - // special case - fint fpx = fint fpx,fpx - a1reg=a0reg; - return gen_fpu(inst, siz, B8(00000001), FPU_FPSP); + if (am1 == AM_NONE) + // special case - fint fpx = fint fpx,fpx + a1reg = a0reg; + + if (activefpu == FPU_68040) + warn("Instruction is emulated in 68040"); + + return gen_fpu(inst, siz, B8(00000001), FPU_NOWARN); } + // -// fintrz (6888X, 68040FPSP) +// fintrz (6888X, 68040FPSP, 68060) // int m_fintrz(WORD inst, WORD siz) { - if (am1==AM_NONE) - // special case - fintrz fpx = fintrz fpx,fpx - a1reg=a0reg; - return gen_fpu(inst, siz, B8(00000011), FPU_FPSP); + if (am1 == AM_NONE) + // special case - fintrz fpx = fintrz fpx,fpx + a1reg = a0reg; + + if (activefpu == FPU_68040) + warn("Instruction is emulated in 68040"); + + return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN); } + // -// flog10 (6888X, 68040FPSP) +// flog10 (6888X, 68040FPSP, 68060FPSP) // int m_flog10(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010101), FPU_FPSP); } + // -// flog2 (6888X, 68040FPSP) +// flog2 (6888X, 68040FPSP, 68060FPSP) // int m_flog2(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010110), FPU_FPSP); } + // -// flogn (6888X, 68040FPSP) +// flogn (6888X, 68040FPSP, 68060FPSP) // int m_flogn(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010100), FPU_FPSP); } + // -// flognp1 (6888X, 68040FPSP) +// flognp1 (68040FPSP, 68060FPSP) // int m_flognp1(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00000110), FPU_FPSP); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(00000110), FPU_FPSP); + + return error("Unsupported in current FPU"); } + // -// fmod (6888X, 68040FPSP) +// fmod (6888X, 68040FPSP, 68060FPSP) // int m_fmod(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00100001), FPU_FPSP); } + // -// fmove (6888X, 68040) +// fmove (6888X, 68040, 68060) // int m_fmove(WORD inst, WORD siz) { + CHECKNOFPU; - ////////////ea to register - if (am0==FREG&&am1ea - - //ea - inst|=am1|a1reg; + // fpx->ea + // EA + inst |= am1 | a1reg; D_word(inst); - //r/m - //if (am0==DREG) - inst=3<<13; - //else - // inst=0; - - WARNING("K-factor logic is totally bogus - fix!") + // R/M + inst = 3 << 13; - //source specifier + // Source specifier switch (siz) { - case SIZB: inst |= (6<<10); break; - case SIZW: inst |= (4<<10); break; - case SIZL: inst |= (0<<10); break; + case SIZB: inst |= (6 << 10); break; + case SIZW: inst |= (4 << 10); break; + case SIZL: inst |= (0 << 10); break; case SIZN: - case SIZS: inst |= (1<<10); break; - case SIZD: inst |= (5<<10); break; - case SIZX: inst |= (2<<10); break; - case SIZP: inst |= (3<<10); if (bfparam1) inst|=1<<12; inst|=(bfparam1&0x7ff)>>2; break; - default: return error("Something bad happened, possibly."); break; - } + case SIZS: inst |= (1 << 10); break; + case SIZD: inst |= (5 << 10); break; + case SIZX: inst |= (2 << 10); break; + case SIZP: inst |= (3 << 10); + // In P size we have 2 cases: {#k} where k is immediate + // and {Dn} where Dn=Data register + if (bfparam1) + { + // Dn + inst |= 1 << 12; + inst |= bfval1 << 4; + } + else + { + // #k + if (bfval1 > 63 && bfval1 < -64) + return error("K-factor must be between -64 and 63"); - //immediate {} value - if (bf0exval>=1<<6) - return error("K-factor must be between 0 and 31"); - if ((!bfparam1) && siz==SIZP) - inst|=bf0exval; + inst |= bfval1 & 127; + } - //destination specifier - inst|=(a0reg<<7); + break; + default: + return error("Something bad happened, possibly."); + break; + } - //opmode - inst|=0; + // Destination specifier + inst |= (a0reg << 7); - D_word(inst); - ea1gen(siz); + // Opmode + inst |= 0; + D_word(inst); + ea1gen(siz); } - else if (am0fpx + // ea->fpx - //ea - inst|=am0|a0reg; + // EA + inst |= am0 | a0reg; D_word(inst); - //r/m - //if (am0==DREG) - inst=1<<14; - //else - // inst=0; + // R/M + inst = 1 << 14; - //source specifier + // Source specifier switch (siz) { - case SIZB: inst |= (6<<10); break; - case SIZW: inst |= (4<<10); break; - case SIZL: inst |= (0<<10); break; + case SIZB: inst |= (6 << 10); break; + case SIZW: inst |= (4 << 10); break; + case SIZL: inst |= (0 << 10); break; case SIZN: - case SIZS: inst |= (1<<10); break; - case SIZD: inst |= (5<<10); break; - case SIZX: inst |= (2<<10); break; - case SIZP: inst |= (3<<10); break; - default: return error("Something bad happened, possibly."); break; + case SIZS: inst |= (1 << 10); break; + case SIZD: inst |= (5 << 10); break; + case SIZX: inst |= (2 << 10); break; + case SIZP: inst |= (3 << 10); break; + default: + return error("Something bad happened, possibly."); + break; } - //destination specifier - inst|=(a1reg<<7); + // Destination specifier + inst |= (a1reg << 7); - //opmode - inst|=0; + // Opmode + inst |= 0; D_word(inst); - ea0gen(siz); - + ea0gen(siz); } - else if (am0==FREG&&am1==FREG) + else if ((am0 == FREG) && (am1 == FREG)) { - //ea + // register-to-register + // Essentially ea to register with R/0=0 + + // EA D_word(inst); - //r/m - inst=0<<14; + // R/M + inst = 0 << 14; - //source specifier - if (siz!=SIZX) + // Source specifier + if (siz != SIZX && siz != SIZN) return error("Invalid size"); - //source register - inst|=(a0reg<<10); + // Source register + inst |= (a0reg << 10); - //destination register - inst|=(a1reg<<7); + // Destination register + inst |= (a1reg << 7); D_word(inst); } - return OK; - ///////////register to memory - //ea - //destination format - //source register - //k-factor (if required) - - - //return error("Not implemented yet."); - //return gen_fpu(inst, siz, B8(00101101), FPU_P_EMUL); + return OK; } + // -// fmove (6888X, 68040) +// fmove (6888X, 68040, 68060) // int m_fmovescr(WORD inst, WORD siz) { - ///////////Move Floating-Point System Control Register (FPCR) - //ea - //dr - //register select - if (am0==FPSCR&&am1=KW_FP0 && *tok<=KW_FP7) - { - //fmovem.x ,ea - if (fpu_reglist_left(®mask) < 0) - return OK; - if (*tok++ != ',') - return error("missing comma"); - if (amode(0) < 0) - return OK; - inst|=am0|a0reg; - if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC))) - return error("invalid addressing mode"); - D_word(inst); - inst=((1<<15)|(1<<14))|(1<<13)|(0<<11)|regmask; - D_word(inst); - ea0gen(siz); - return OK; - } - else if (*tok >= KW_D0 && *tok <= KW_D7) - { - //fmovem.x Dn,ea - datareg=(*tok++&7)<<10; - if (*tok++ != ',') - return error("missing comma"); - if (amode(0) < 0) - return OK; - inst|=am0|a0reg; - if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC))) - return error("invalid addressing mode"); - D_word(inst); - inst=((1<<15)|(1<<14))|(1<<13)|(1<<11)|(datareg<<4); - D_word(inst); - ea0gen(siz); - return OK; - } - else - { - //fmovem.x ea,... - if (amode(0) < 0) - return OK; - inst|=am0|a0reg; - if (*tok++ != ',') - return error("missing comma"); - if (*tok>=KW_FP0 && *tok<=KW_FP7) - { - //fmovem.x ea, - if (fpu_reglist_right(®mask) < 0) - return OK; - D_word(inst); - inst=((1<<15)|(1<<14))|(0<<13)|(2<<11)|regmask; - D_word(inst); - ea0gen(siz); - return OK; - } - else - { - //fmovem.x ea,Dn - datareg=(*tok++&7)<<10; - D_word(inst); - inst=((1<<15)|(1<<14))|(0<<13)|(3<<11)|(datareg<<4); - D_word(inst); - ea0gen(siz); - return OK; - } - } - } - else if (siz == SIZL||siz==SIZN) - { - if (*tok==KW_FPCR || *tok==KW_FPSR || *tok==KW_FPIAR) - { - //fmovem.l ,ea - regmask=(1<<15)|(1<<13); + CHECKNOFPU; + + WORD regmask; + WORD datareg; + + if (siz == SIZX || siz == SIZN) + { + if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + { + // fmovem.x ,ea + if (fpu_reglist_left(®mask) < 0) + return OK; + + if (*tok++ != ',') + return error("missing comma"); + + if (amode(0) < 0) + return OK; + + inst |= am0 | a0reg; + + if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC))) + return error("invalid addressing mode"); + + D_word(inst); + inst = (1 << 15) | (1 << 14) | (1 << 13) | (0 << 11) | regmask; + D_word(inst); + ea0gen(siz); + return OK; + } + else if ((*tok >= KW_D0) && (*tok <= KW_D7)) + { + // fmovem.x Dn,ea + datareg = (*tok++ & 7) << 10; + + if (*tok++ != ',') + return error("missing comma"); + + if (amode(0) < 0) + return OK; + + inst |= am0 | a0reg; + + if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC))) + return error("invalid addressing mode"); + + // Quote from the 060 manual: + // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list." + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + + D_word(inst); + inst = (1 << 15) | (1 << 14) | (1 << 13) | (1 << 11) | (datareg << 4); + D_word(inst); + ea0gen(siz); + return OK; + } + else + { + // fmovem.x ea,... + if (amode(0) < 0) + return OK; + + inst |= am0 | a0reg; + + if (*tok++ != ',') + return error("missing comma"); + + if ((*tok >= KW_FP0) && (*tok <= KW_FP7)) + { + // fmovem.x ea, + if (fpu_reglist_right(®mask) < 0) + return OK; + + D_word(inst); + inst = (1 << 15) | (1 << 14) | (0 << 13) | (2 << 11) | regmask; + D_word(inst); + ea0gen(siz); + return OK; + } + else + { + // fmovem.x ea,Dn + datareg = (*tok++ & 7) << 10; + + // Quote from the 060 manual: + // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list." + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + + D_word(inst); + inst = (1 << 15) | (1 << 14) | (0 << 13) | (3 << 11) | (datareg << 4); + D_word(inst); + ea0gen(siz); + return OK; + } + } + } + else if (siz == SIZL) + { + if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR)) + { + // fmovem.l ,ea + regmask = (1 << 15) | (1 << 13); + int no_control_regs = 0; + fmovem_loop_1: - if (*tok==KW_FPCR) - { - regmask|=(1<<12); - tok++; - goto fmovem_loop_1; - } - if (*tok==KW_FPSR) - { - regmask|=(1<<11); - tok++; - goto fmovem_loop_1; - } - if (*tok==KW_FPIAR) - { - regmask|=(1<<10); - tok++; - goto fmovem_loop_1; - } - if (*tok=='/' || *tok=='-') - { - tok++; - goto fmovem_loop_1; - } - if (*tok++ != ',') - return error("missing comma"); - if (amode(0) < 0) - return OK; - inst|=am0|a0reg; - D_word(inst); - D_word(regmask); - ea0gen(siz); - } - else - { - //fmovem.l ea, - if (amode(0) < 0) - return OK; - inst|=am0|a0reg; - if (*tok++ != ',') - return error("missing comma"); - regmask=(1<<15)|(0<<13); + if (*tok == KW_FPCR) + { + regmask |= (1 << 12); + tok++; + no_control_regs++; + goto fmovem_loop_1; + } + + if (*tok == KW_FPSR) + { + regmask |= (1 << 11); + tok++; + no_control_regs++; + goto fmovem_loop_1; + } + + if (*tok == KW_FPIAR) + { + regmask |= (1 << 10); + tok++; + no_control_regs++; + goto fmovem_loop_1; + } + + if ((*tok == '/') || (*tok == '-')) + { + tok++; + goto fmovem_loop_1; + } + + if (*tok++ != ',') + return error("missing comma"); + + if (amode(0) < 0) + return OK; + + // Quote from the 060 manual: + // "[..] when the processor attempts to execute an FMOVEM.L instruction with + // an immediate addressing mode to more than one floating - point + // control register (FPCR, FPSR, FPIAR)[..]" + if (activefpu == FPU_68060) + if (no_control_regs > 1 && am0 == IMMED) + warn("Instruction is emulated in 68060"); + + inst |= am0 | a0reg; + D_word(inst); + D_word(regmask); + ea0gen(siz); + } + else + { + // fmovem.l ea, + if (amode(0) < 0) + return OK; + + inst |= am0 | a0reg; + + if (*tok++ != ',') + return error("missing comma"); + + regmask = (1 << 15) | (0 << 13); + fmovem_loop_2: - if (*tok==KW_FPCR) - { - regmask|=(1<<12); - tok++; - goto fmovem_loop_2; - } - if (*tok==KW_FPSR) - { - regmask|=(1<<11); - tok++; - goto fmovem_loop_2; - } - if (*tok==KW_FPIAR) - { - regmask|=(1<<10); - tok++; - goto fmovem_loop_2; - } - if (*tok=='/' || *tok=='-') - { - tok++; - goto fmovem_loop_2; - } - if (*tok!=EOL) - return error("extra (unexpected) text found"); - inst|=am0|a0reg; - D_word(inst); - D_word(regmask); - ea0gen(siz); - } - } - else + if (*tok == KW_FPCR) + { + regmask |= (1 << 12); + tok++; + goto fmovem_loop_2; + } + + if (*tok == KW_FPSR) + { + regmask |= (1 << 11); + tok++; + goto fmovem_loop_2; + } + + if (*tok == KW_FPIAR) + { + regmask |= (1 << 10); + tok++; + goto fmovem_loop_2; + } + + if ((*tok == '/') || (*tok == '-')) + { + tok++; + goto fmovem_loop_2; + } + + if (*tok != EOL) + return error("extra (unexpected) text found"); + + inst |= am0 | a0reg; + D_word(inst); + D_word(regmask); + ea0gen(siz); + } + } + else return error("bad size suffix"); - return OK; + return OK; } + // -// fmul (6888X, 68040) +// fmul (6888X, 68040, 68060) // int m_fmul(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100011), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100011), FPU_NOWARN); } + + +// +// fsmul (68040, 68060) +// int m_fsmul(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100011), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + + +// +// fdmul (68040) +// int m_fdmul(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01100111), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01100111), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + // -// fneg (6888X, 68040) +// fneg (6888X, 68040, 68060) // int m_fneg(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00011010), FPU_P_EMUL); + CHECKNOFPU; + + if (am1 == AM_NONE) + { + a1reg = a0reg; + return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN); + } + + return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN); } + + +// +// fsneg (68040, 68060) +// int m_fsneg(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011010), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + { + if (am1 == AM_NONE) + { + a1reg = a0reg; + return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN); + } + + return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN); + } + + return error("Unsupported in current FPU"); } + + +// +// fdneg (68040, 68060) +// int m_fdneg(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01011110), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + { + if (am1 == AM_NONE) + { + a1reg = a0reg; + return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN); + } + + return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN); + } + + return error("Unsupported in current FPU"); } + // -// fnop (6888X, 68040) +// fnop (6888X, 68040, 68060) // int m_fnop(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00000000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00000000), FPU_NOWARN); } + // -// frem (6888X, 68040FPSP) +// frem (6888X, 68040FPSP, 68060FPSP) // int m_frem(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00100101), FPU_FPSP); } + // -// fscale (6888X, 68040FPSP) +// fscale (6888X, 68040FPSP, 68060FPSP) // int m_fscale(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00100110), FPU_FPSP); } + +// +// FScc (6888X, 68040, 68060), cpScc (68851, 68030), PScc (68851) +// TODO: Add check for PScc to ensure 68020+68851 active +// TODO: Add check for cpScc to ensure 68020+68851, 68030 +// +int m_fscc(WORD inst, WORD siz) +{ + CHECKNOFPU; + + // We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0), + // so we need to extract them first and fill in the clobbered bits. + WORD opcode = inst & 0x1F; + inst &= 0xFFE0; + inst |= am0 | a0reg; + D_word(inst); + ea0gen(siz); + D_word(opcode); + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + return OK; +} + + // -// FScc (6888X, 68040) -// -int m_fseq (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000001)); return OK;} -int m_fsne (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001110)); return OK;} -int m_fsgt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010010)); return OK;} -int m_fsngt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011101)); return OK;} -int m_fsge (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010011)); return OK;} -int m_fsnge (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011100)); return OK;} -int m_fslt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010100)); return OK;} -int m_fsnlt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011011)); return OK;} -int m_fsle (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010101)); return OK;} -int m_fsnle (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011010)); return OK;} -int m_fsgl (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010110)); return OK;} -int m_fsngl (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011001)); return OK;} -int m_fsgle (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010111)); return OK;} -int m_fsngle(WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011000)); return OK;} -int m_fsogt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000010)); return OK;} -int m_fsule (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001101)); return OK;} -int m_fsoge (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000011)); return OK;} -int m_fsult (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001100)); return OK;} -int m_fsolt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000100)); return OK;} -int m_fsuge (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001011)); return OK;} -int m_fsole (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000101)); return OK;} -int m_fsugt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001010)); return OK;} -int m_fsogl (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000110)); return OK;} -int m_fsueq (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001001)); return OK;} -int m_fsor (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000111)); return OK;} -int m_fsun (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001000)); return OK;} -int m_fsf (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000000)); return OK;} -int m_fst (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001111)); return OK;} -int m_fssf (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010000)); return OK;} -int m_fsst (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011111)); return OK;} -int m_fsseq (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010001)); return OK;} -int m_fssne (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011110)); return OK;} - -// -// FTRAPcc (6888X, 68040) -// - -int m_ftrapeq (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000001)); D_long(a0exval); } return OK;} -int m_ftrapne (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001110)); D_long(a0exval); } return OK;} -int m_ftrapgt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010010)); D_long(a0exval); } return OK;} -int m_ftrapngt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011101)); D_long(a0exval); } return OK;} -int m_ftrapge (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010011)); D_long(a0exval); } return OK;} -int m_ftrapnge (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011100)); D_long(a0exval); } return OK;} -int m_ftraplt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010100)); D_long(a0exval); } return OK;} -int m_ftrapnlt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011011)); D_long(a0exval); } return OK;} -int m_ftraple (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010101)); D_long(a0exval); } return OK;} -int m_ftrapnle (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011010)); D_long(a0exval); } return OK;} -int m_ftrapgl (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010110)); D_long(a0exval); } return OK;} -int m_ftrapngl (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011001)); D_long(a0exval); } return OK;} -int m_ftrapgle (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010111)); D_long(a0exval); } return OK;} -int m_ftrapngle(WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011000)); D_long(a0exval); } return OK;} -int m_ftrapogt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000010)); D_long(a0exval); } return OK;} -int m_ftrapule (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001101)); D_long(a0exval); } return OK;} -int m_ftrapoge (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000011)); D_long(a0exval); } return OK;} -int m_ftrapult (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001100)); D_long(a0exval); } return OK;} -int m_ftrapolt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000100)); D_long(a0exval); } return OK;} -int m_ftrapuge (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001011)); D_long(a0exval); } return OK;} -int m_ftrapole (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000101)); D_long(a0exval); } return OK;} -int m_ftrapugt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001010)); D_long(a0exval); } return OK;} -int m_ftrapogl (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000110)); D_long(a0exval); } return OK;} -int m_ftrapueq (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001001)); D_long(a0exval); } return OK;} -int m_ftrapor (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000111)); D_long(a0exval); } return OK;} -int m_ftrapun (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001000)); D_long(a0exval); } return OK;} -int m_ftrapf (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000000)); D_long(a0exval); } return OK;} -int m_ftrapt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001111)); D_long(a0exval); } return OK;} -int m_ftrapsf (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010000)); D_long(a0exval); } return OK;} -int m_ftrapst (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011111)); D_long(a0exval); } return OK;} -int m_ftrapseq (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010001)); D_long(a0exval); } return OK;} -int m_ftrapsne (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011110)); D_long(a0exval); } return OK;} - -int m_ftrapeqn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000001)); return OK;} -int m_ftrapnen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001110)); return OK;} -int m_ftrapgtn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010010)); return OK;} -int m_ftrapngtn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011101)); return OK;} -int m_ftrapgen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010011)); return OK;} -int m_ftrapngen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011100)); return OK;} -int m_ftrapltn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010100)); return OK;} -int m_ftrapnltn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011011)); return OK;} -int m_ftraplen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010101)); return OK;} -int m_ftrapnlen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011010)); return OK;} -int m_ftrapgln (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010110)); return OK;} -int m_ftrapngln (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011001)); return OK;} -int m_ftrapglen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010111)); return OK;} -int m_ftrapnglen(WORD inst, WORD siz) { D_word(inst); D_word(B8(00011000)); return OK;} -int m_ftrapogtn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000010)); return OK;} -int m_ftrapulen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001101)); return OK;} -int m_ftrapogen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000011)); return OK;} -int m_ftrapultn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001100)); return OK;} -int m_ftrapoltn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000100)); return OK;} -int m_ftrapugen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001011)); return OK;} -int m_ftrapolen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000101)); return OK;} -int m_ftrapugtn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001010)); return OK;} -int m_ftrapogln (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000110)); return OK;} -int m_ftrapueqn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001001)); return OK;} -int m_ftraporn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000111)); return OK;} -int m_ftrapunn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001000)); return OK;} -int m_ftrapfn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000000)); return OK;} -int m_ftraptn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001111)); return OK;} -int m_ftrapsfn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010000)); return OK;} -int m_ftrapstn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011111)); return OK;} -int m_ftrapseqn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010001)); return OK;} -int m_ftrapsnen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011110)); return OK;} - - -// -// fsgldiv (6888X, 68040) +// fsgldiv (6888X, 68040FPSP, 68060FPSP) // int m_fsgldiv(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100100), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100100), FPU_FPSP); } + // -// fsglmul (6888X, 68040) +// fsglmul (6888X, 68040, 68060FPSP) // int m_fsglmul(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00100111), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00100111), FPU_FPSP); } + // -// fsin (6888X, 68040FPSP) +// fsin (6888X, 68040FPSP, 68060FPSP) // int m_fsin(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001110), FPU_FPSP); } + // -// fsincos (6888X, 68040FPSP) +// fsincos (6888X, 68040FPSP, 68060FPSP) // int m_fsincos(WORD inst, WORD siz) { - int temp; - if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP)==OK) + CHECKNOFPU; + + // Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu + // generates + int temp; + temp = a2reg; + a2reg = a1reg; + a1reg = temp; + + if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK) { chptr[-1] |= a2reg; return OK; } - else - return ERROR; + + return ERROR; } + // -// fsin (6888X, 68040FPSP) +// fsinh (6888X, 68040FPSP, 68060FPSP) // int m_fsinh(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00000010), FPU_FPSP); } + // -// fsqrt (6888X, 68040) +// fsqrt (6888X, 68040, 68060) // int m_fsqrt(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00000100), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00000100), FPU_NOWARN); } + + +// +// fsfsqrt (68040, 68060) +// int m_fsfsqrt(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01000001), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + + +// +// fdfsqrt (68040, 68060) +// int m_fdfsqrt(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01000101), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01000101), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + // -// fsub (6888X, 68040) +// fsub (6888X, 68040, 68060) // int m_fsub(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00101000), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00101000), FPU_NOWARN); } + + +// +// fsfsub (68040, 68060) +// int m_fsfsub(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01101000), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01101000), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + + +// +// fdfsub (68040, 68060) +// int m_fdsub(WORD inst, WORD siz) { - if (activefpu == FPU_68040) - return gen_fpu(inst, siz, B8(01101100), FPU_P_EMUL); - else - return error("Unsupported in current FPU"); + if (activefpu & (FPU_68040 | FPU_68060)) + return gen_fpu(inst, siz, B8(01101100), FPU_NOWARN); + + return error("Unsupported in current FPU"); } + // -// ftan (6888X, 68040FPSP) +// ftan (6888X, 68040FPSP, 68060FPSP) // int m_ftan(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001111), FPU_FPSP); } + // -// ftanh (6888X, 68040FPSP) +// ftanh (6888X, 68040FPSP, 68060FPSP) // int m_ftanh(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00001001), FPU_FPSP); } + // -// ftentox (6888X, 68040FPSP) +// ftentox (6888X, 68040FPSP, 68060FPSP) // int m_ftentox(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010010), FPU_FPSP); } + +// +// FTRAPcc (6888X, 68040, 68060FPSP) +// +int m_ftrapcc(WORD inst, WORD siz) +{ + CHECKNOFPU; + + // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7), + // so we need to extract them first and fill in the clobbered bits. + WORD opcode = (inst >> 3) & 0x1F; + inst = (inst & 0xFF07) | (0xF << 3); + + if (siz == SIZW) + { + inst |= 2; + D_word(inst); + D_word(opcode); + D_word(a0exval); + } + else if (siz == SIZL) + { + inst |= 3; + D_word(inst); + D_word(opcode); + D_long(a0exval); + } + else if (siz == SIZN) + { + inst |= 4; + D_word(inst); + D_word(opcode); + return OK; + } + + if (activefpu == FPU_68060) + warn("Instruction is emulated in 68060"); + + return OK; +} + + // -// ftst (6888X, 68040) +// ftst (6888X, 68040, 68060) // int m_ftst(WORD inst, WORD siz) { - return gen_fpu(inst, siz, B8(00111010), FPU_P_EMUL); + CHECKNOFPU; + return gen_fpu(inst, siz, B8(00111010), FPU_NOWARN); } + // -// ftwotox (6888X, 68040FPSP) +// ftwotox (6888X, 68040FPSP, 68060FPSP) // int m_ftwotox(WORD inst, WORD siz) { + CHECKNOFPU; return gen_fpu(inst, siz, B8(00010001), FPU_FPSP); } + +///////////////////////////////// +// // +// 68060 specific instructions // +// // +///////////////////////////////// + + +// +// lpstop (68060) +// +int m_lpstop(WORD inst, WORD siz) +{ + CHECKNO60; + D_word(B16(00000001, 11000000)); + + if (a0exattr & DEFINED) + { + D_word(a0exval); + } + else + { + AddFixup(FU_WORD, sloc, a0expr); + D_word(0); + } + + return OK; +} + + +// +// plpa (68060) +// +int m_plpa(WORD inst, WORD siz) +{ + CHECKNO60; + inst |= a0reg; // Install register + D_word(inst); + + return OK; +} +