X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=mach.c;h=69be7ea471873d11f8735b52dc75f09f7b52e192;hp=b3e36c7dc382c93b84599a1979f8da85920c7280;hb=60f204cb9e3905100da0d89f14bb40db764acd9e;hpb=917bfc1503181b7e762b73b9560bb834c12c64fa diff --git a/mach.c b/mach.c index b3e36c7..69be7ea 100644 --- a/mach.c +++ b/mach.c @@ -1,7 +1,7 @@ // // RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System // MACH.C - Code Generation -// Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends +// Copyright (C) 199x Landon Dyer, 2017 Reboot and Friends // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986 // Source utilised with the kind permission of Landon Dyer // @@ -19,7 +19,7 @@ #include "kwtab.h" -// Fucntion prototypes +// Fucntion prototypes int m_unimp(WORD, WORD), m_badmode(WORD, WORD), m_bad6mode(WORD, WORD), m_bad6inst(WORD, WORD); int m_self(WORD, WORD); int m_abcd(WORD, WORD); @@ -59,43 +59,42 @@ extern int ea1gen(WORD); // Include code tables MNTAB machtab[] = { -// { (WORD)-1, (unsigned long)-1L, (unsigned long)-1L, 0x0000, 0, m_badmode }, // 0 - { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 +// { (WORD)-1, (unsigned long)-1L, (unsigned long)-1L, 0x0000, 0, m_badmode }, // 0 + { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0 #include "68ktab.h" - { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry + { 0, 0L, 0L, 0x0000, 0, m_unimp } // Last entry }; // Register number << 9 WORD reg_9[8] = { - 0, 1<<9, 2<<9, 3<<9, - 4<<9, 5<<9, 6<<9, 7<<9 + 0, 1 << 9, 2 << 9, 3 << 9, 4 << 9, 5 << 9, 6 << 9, 7 << 9 }; // SIZB==>00, SIZW==>01, SIZL==>10, SIZN==>01 << 6 WORD siz_6[] = { - (WORD)-1, // n/a - 0, // SIZB - 1<<6, (WORD)-1, // SIZW, n/a - 2<<6, (WORD)-1, (WORD)-1, (WORD)-1, // SIZL, n/a, n/a, n/a - 1<<6 // SIZN + (WORD)-1, // n/a + 0, // SIZB + 1<<6, (WORD)-1, // SIZW, n/a + 2<<6, (WORD)-1, (WORD)-1, (WORD)-1, // SIZL, n/a, n/a, n/a + 1<<6 // SIZN }; // Byte/word/long size for MOVE instrs WORD siz_12[] = { (WORD)-1, - 0x1000, // Byte - 0x3000, (WORD)-1, // Word - 0x2000, (WORD)-1, (WORD)-1, (WORD)-1, // Long - 0x3000 // Word (SIZN) + 0x1000, // Byte + 0x3000, (WORD)-1, // Word + 0x2000, (WORD)-1, (WORD)-1, (WORD)-1, // Long + 0x3000 // Word (SIZN) }; // Word/long size (0=.w, 1=.l) in bit 8 WORD lwsiz_8[] = { - (WORD)-1, // n/a - (WORD)-1, // SIZB - 0, (WORD)-1, // SIZW, n/a - 1<<8, (WORD)-1, (WORD)-1, (WORD)-1, // SIZL, n/a, n/a, n/a - 0 // SIZN + (WORD)-1, // n/a + (WORD)-1, // SIZB + 0, (WORD)-1, // SIZW, n/a + 1<<8, (WORD)-1, (WORD)-1, (WORD)-1, // SIZL, n/a, n/a, n/a + 0 // SIZN }; // Addressing mode in bits 6..11 (register/mode fields are reversed) @@ -134,63 +133,59 @@ int m_self(WORD inst, WORD usused) // // Do one EA in bits 0..5 -// +// // Bits in `inst' have the following meaning: -// +// // Bit zero specifies which ea (ea0 or ea1) to generate in the lower six bits // of the instr. -// +// // If bit one is set, the OTHER ea (the one that wasn't generated by bit zero) // is generated after the instruction. Regardless of bit 0's value, ea0 is // always deposited in memory before ea1. -// +// // If bit two is set, standard size bits are set in the instr in bits 6 and 7. -// +// // If bit four is set, bit three specifies which eaXreg to place in bits 9..11 // of the instr. // int m_ea(WORD inst, WORD siz) { - WORD flg = inst; // Save flag bits - inst &= ~0x3F; // Clobber flag bits in instr + WORD flg = inst; // Save flag bits + inst &= ~0x3F; // Clobber flag bits in instr - // Install "standard" instr size bits + // Install "standard" instr size bits if (flg & 4) inst |= siz_6[siz]; if (flg & 16) { - // OR-in register number + // OR-in register number if (flg & 8) - { - inst |= reg_9[a1reg]; // ea1reg in bits 9..11 - } + inst |= reg_9[a1reg]; // ea1reg in bits 9..11 else - { - inst |= reg_9[a0reg]; // ea0reg in bits 9..11 - } + inst |= reg_9[a0reg]; // ea0reg in bits 9..11 } if (flg & 1) { - // Use am1 - inst |= am1 | a1reg; // Get ea1 into instr - D_word(inst); // Deposit instr + // Use am1 + inst |= am1 | a1reg; // Get ea1 into instr + D_word(inst); // Deposit instr - // Generate ea0 if requested + // Generate ea0 if requested if (flg & 2) ea0gen(siz); - ea1gen(siz); // Generate ea1 + ea1gen(siz); // Generate ea1 } else { - // Use am0 - inst |= am0 | a0reg; // Get ea0 into instr - D_word(inst); // Deposit instr - ea0gen(siz); // Generate ea0 + // Use am0 + inst |= am0 | a0reg; // Get ea0 into instr + D_word(inst); // Deposit instr + ea0gen(siz); // Generate ea0 - // Generate ea1 if requested + // Generate ea1 if requested if (flg & 2) ea1gen(siz); } @@ -207,7 +202,7 @@ int m_abcd(WORD inst, WORD siz) { if (inst & 1) { - // Install size bits + // Install size bits inst--; inst |= siz_6[siz]; } @@ -226,7 +221,7 @@ int m_adda(WORD inst, WORD siz) { inst |= am0 | a0reg | lwsiz_8[siz] | reg_9[a1reg]; D_word(inst); - ea0gen(siz); // Generate EA + ea0gen(siz); // Generate EA return 0; } @@ -235,19 +230,19 @@ int m_adda(WORD inst, WORD siz) // // If bit 0 of `inst' is 1, install size bits in bits 6..7 of instr. // If bit 1 of `inst' is 1, install a1reg in bits 9..11 of instr. -// +// int m_reg(WORD inst, WORD siz) { if (inst & 1) - // Install size bits + // Install size bits inst |= siz_6[siz]; if (inst & 2) - // Install other register (9..11) + // Install other register (9..11) inst |= reg_9[a1reg]; - inst &= ~7; // Clear off crufty bits - inst |= a0reg; // Install first register + inst &= ~7; // Clear off crufty bits + inst |= a0reg; // Install first register D_word(inst); return 0; @@ -323,11 +318,11 @@ int m_bitop(WORD inst, WORD siz) { // Enforce instruction sizes if (am1 == DREG) - { // X,Dn must be .n or .l + { // X,Dn must be .n or .l if (siz & (SIZB | SIZW)) return error(siz_error); } - else if (siz & (SIZW | SIZL)) // X,ea must be .n or .b + else if (siz & (SIZW | SIZL)) // X,ea must be .n or .b return error(siz_error); // Construct instr and EAs @@ -336,7 +331,7 @@ int m_bitop(WORD inst, WORD siz) if (am0 == IMMED) { D_word(inst); - ea0gen(SIZB); // Immediate bit number + ea0gen(SIZB); // Immediate bit number } else { @@ -344,7 +339,7 @@ int m_bitop(WORD inst, WORD siz) D_word(inst); } - // ea to bit-munch + // ea to bit-munch ea1gen(SIZB); return 0; @@ -391,14 +386,14 @@ int m_exg(WORD inst, WORD siz) siz = siz; if (am0 == DREG && am1 == DREG) - m = 0x0040; // Dn,Dn + m = 0x0040; // Dn,Dn else if (am0 == AREG && am1 == AREG) - m = 0x0048; // An,An + m = 0x0048; // An,An else { if (am0 == AREG) - { // Dn,An or An,Dn - m = a1reg; // Get AREG into a1reg + { // Dn,An or An,Dn + m = a1reg; // Get AREG into a1reg a1reg = a0reg; a0reg = m; } @@ -430,20 +425,20 @@ int m_link(WORD inst, WORD siz) // // Handle MOVE // MOVE -// +// // Optimize MOVE.L #,D0 to a MOVEQ // -//int m_move(WORD inst, int siz) int m_move(WORD inst, WORD size) { // Cast the passed in value to an int int siz = (int)size; // Try to optimize to MOVEQ - if (optim_flag && siz == SIZL && am0 == IMMED && am1 == DREG + if (optim_flags[OPT_MOVEL_MOVEQ] && siz == SIZL && am0 == IMMED && am1 == DREG && (a0exattr & (TDB|DEFINED)) == DEFINED && a0exval + 0x80 < 0x100) { m_moveq((WORD)0x7000, (WORD)0); + if (sbra_flag) warn("move.l #size,dx converted to moveq"); } @@ -457,7 +452,7 @@ int m_move(WORD inst, WORD size) ea0gen((WORD)siz); if (am1 >= ADISP) - ea1gen((WORD)siz); + ea1gen((WORD)siz | 0x8000); // Tell ea1gen we're move ea,ea } return 0; @@ -472,9 +467,9 @@ int m_usp(WORD inst, WORD siz) siz = siz; if (am0 == AM_USP) - inst |= a1reg; // USP, An + inst |= a1reg; // USP, An else - inst |= a0reg; // An, USP + inst |= a0reg; // An, USP D_word(inst); @@ -489,11 +484,11 @@ int m_moveq(WORD inst, WORD siz) { siz = siz; - // Arrange for future fixup + // Arrange for future fixup if (!(a0exattr & DEFINED)) { AddFixup(FU_BYTE | FU_SEXT, sloc + 1, a0expr); - a0exval = 0; + a0exval = 0; } else if (a0exval + 0x100 >= 0x200) return error(range_error); @@ -520,7 +515,7 @@ int m_movep(WORD inst, WORD siz) if (am1 == AIND) D_word(0) - else + else ea1gen(siz); } else @@ -530,7 +525,7 @@ int m_movep(WORD inst, WORD siz) if (am0 == AIND) D_word(0) - else + else ea0gen(siz); } @@ -558,9 +553,9 @@ int m_br(WORD inst, WORD siz) // Optimize branch instr. size if (siz == SIZN) { - if (optim_flag && v != 0 && v + 0x80 < 0x100) + if (optim_flags[OPT_BSR_BCC_S] && v != 0 && v + 0x80 < 0x100) { - // Fits in .B + // Fits in .B inst |= v & 0xFF; D_word(inst); if (sbra_flag) @@ -569,7 +564,7 @@ int m_br(WORD inst, WORD siz) } else { - // Fits in .W + // Fits in .W if (v + 0x8000 > 0x10000) return error(range_error); @@ -603,14 +598,14 @@ int m_br(WORD inst, WORD siz) if (siz == SIZB) { - // .B + // .B AddFixup(FU_BBRA | FU_PCREL | FU_SEXT, sloc, a0expr); D_word(inst); return 0; } else { - // .W + // .W D_word(inst); AddFixup(FU_WORD | FU_PCREL | FU_LBRA | FU_ISBRA, sloc, a0expr); D_word(0); @@ -629,7 +624,7 @@ int m_addq(WORD inst, WORD siz) if (a0exattr & DEFINED) { - if (a0exval > 8 || a0exval == 0) // Range in 1..8 + if (a0exval > 8 || a0exval == 0) // Range in 1..8 return error(range_error); inst |= (a0exval & 7) << 9; @@ -665,7 +660,7 @@ int m_trap(WORD inst, WORD siz) inst |= a0exval; D_word(inst); } - else + else return error(undef_error); return 0; @@ -690,7 +685,7 @@ int m_movem(WORD inst, WORD siz) if (*tok == '#') { - // Handle #, ea + // Handle #, ea tok++; if (abs_expr(&eval) != OK) @@ -705,7 +700,7 @@ int m_movem(WORD inst, WORD siz) if (*tok >= KW_D0 && *tok <= KW_A7) { - // , ea + // , ea if (reglist(&rmask) < 0) return 0; @@ -733,7 +728,7 @@ immed1: } else { - // ea, + // ea, if (amode(0) < 0) return 0; @@ -747,7 +742,7 @@ immed1: if (*tok == '#') { - // ea, # + // ea, # tok++; if (abs_expr(&eval) != OK)