X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=mach.c;h=2673aa9f5fb5063a44fb3831bf33cf033e13084d;hp=ac800eb665bdf0e77366c5adfbdd55faa3addb85;hb=29b32d134bc12831a8ddd098bf9aeeda26dcfe7c;hpb=da0013df9438aa14e478544307e925462d398cb3

diff --git a/mach.c b/mach.c
index ac800eb..2673aa9 100644
--- a/mach.c
+++ b/mach.c
@@ -11,9 +11,9 @@
 #include "direct.h"
 #include "eagen.h"
 #include "error.h"
+#include "expr.h"
 #include "procln.h"
 #include "riscasm.h"
-//#include "rmac.h"
 #include "sect.h"
 #include "token.h"
 
@@ -49,8 +49,9 @@ int m_movep(WORD, WORD);
 int m_trap(WORD, WORD);
 int m_movem(WORD, WORD);
 int m_clra(WORD, WORD);
+int m_clrd(WORD, WORD);
 
-int m_move30(WORD, WORD);			//68020/30/40/60
+int m_move30(WORD, WORD);			// 68020/30/40/60
 int m_br30(WORD inst, WORD siz);
 int m_ea030(WORD inst, WORD siz);
 int m_bfop(WORD inst, WORD siz);
@@ -84,42 +85,13 @@ int m_pbcc(WORD inst, WORD siz);
 int m_pflusha(WORD inst, WORD siz);
 int m_pflush(WORD inst, WORD siz);
 int m_pflushr(WORD inst, WORD siz);
-int m_pload(WORD inst, WORD siz);
+int m_pload(WORD inst, WORD siz, WORD extension);
 int m_pmove(WORD inst, WORD siz);
 int m_pmovefd(WORD inst, WORD siz);
 int m_ptest(WORD inst, WORD siz);
-int m_ptrapbs(WORD inst, WORD siz);
-int m_ptrapbc(WORD inst, WORD siz);
-int m_ptrapls(WORD inst, WORD siz);
-int m_ptraplc(WORD inst, WORD siz);
-int m_ptrapss(WORD inst, WORD siz);
-int m_ptrapsc(WORD inst, WORD siz);
-int m_ptrapas(WORD inst, WORD siz);
-int m_ptrapac(WORD inst, WORD siz);
-int m_ptrapws(WORD inst, WORD siz);
-int m_ptrapwc(WORD inst, WORD siz);
-int m_ptrapis(WORD inst, WORD siz);
-int m_ptrapic(WORD inst, WORD siz);
-int m_ptrapgc(WORD inst, WORD siz);
-int m_ptrapgs(WORD inst, WORD siz);
-int m_ptrapcs(WORD inst, WORD siz);
 int m_ptrapcc(WORD inst, WORD siz);
-int m_ptrapbsn(WORD inst, WORD siz);
-int m_ptrapbcn(WORD inst, WORD siz);
-int m_ptraplsn(WORD inst, WORD siz);
-int m_ptraplcn(WORD inst, WORD siz);
-int m_ptrapssn(WORD inst, WORD siz);
-int m_ptrapscn(WORD inst, WORD siz);
-int m_ptrapasn(WORD inst, WORD siz);
-int m_ptrapacn(WORD inst, WORD siz);
-int m_ptrapwsn(WORD inst, WORD siz);
-int m_ptrapwcn(WORD inst, WORD siz);
-int m_ptrapisn(WORD inst, WORD siz);
-int m_ptrapicn(WORD inst, WORD siz);
-int m_ptrapgsn(WORD inst, WORD siz);
-int m_ptrapgcn(WORD inst, WORD siz);
-int m_ptrapcsn(WORD inst, WORD siz);
-int m_ptrapccn(WORD inst, WORD siz);
+int m_ploadr(WORD inst, WORD siz);
+int m_ploadw(WORD inst, WORD siz);
 
 //FPU
 int m_fabs(WORD inst, WORD siz);
@@ -162,38 +134,7 @@ int m_fnop(WORD inst, WORD siz);
 int m_frem(WORD inst, WORD siz);
 int m_fsabs(WORD inst, WORD siz);
 int m_fsadd(WORD inst, WORD siz);
-int m_fseq(WORD inst, WORD siz);
-int m_fsne(WORD inst, WORD siz);
-int m_fsgt(WORD inst, WORD siz);
-int m_fsngt(WORD inst, WORD siz);
-int m_fsge(WORD inst, WORD siz);
-int m_fsnge(WORD inst, WORD siz);
-int m_fslt(WORD inst, WORD siz);
-int m_fsnlt(WORD inst, WORD siz);
-int m_fsle(WORD inst, WORD siz);
-int m_fsnle(WORD inst, WORD siz);
-int m_fsgl(WORD inst, WORD siz);
-int m_fsngl(WORD inst, WORD siz);
-int m_fsgle(WORD inst, WORD siz);
-int m_fsngle(WORD inst, WORD siz);
-int m_fsogt(WORD inst, WORD siz);
-int m_fsule(WORD inst, WORD siz);
-int m_fsoge(WORD inst, WORD siz);
-int m_fsult(WORD inst, WORD siz);
-int m_fsolt(WORD inst, WORD siz);
-int m_fsuge(WORD inst, WORD siz);
-int m_fsole(WORD inst, WORD siz);
-int m_fsugt(WORD inst, WORD siz);
-int m_fsogl(WORD inst, WORD siz);
-int m_fsueq(WORD inst, WORD siz);
-int m_fsor(WORD inst, WORD siz);
-int m_fsun(WORD inst, WORD siz);
-int m_fsf(WORD inst, WORD siz);
-int m_fst(WORD inst, WORD siz);
-int m_fssf(WORD inst, WORD siz);
-int m_fsst(WORD inst, WORD siz);
-int m_fsseq(WORD inst, WORD siz);
-int m_fssne(WORD inst, WORD siz);
+int m_fscc(WORD inst, WORD siz);
 int m_fscale(WORD inst, WORD siz);
 int m_fsdiv(WORD inst, WORD siz);
 int m_fsfsqrt(WORD inst, WORD siz);
@@ -213,70 +154,7 @@ int m_ftanh(WORD inst, WORD siz);
 int m_ftentox(WORD inst, WORD siz);
 int m_ftst(WORD inst, WORD siz);
 int m_ftwotox(WORD inst, WORD siz);
-int m_ftrapeq(WORD inst, WORD siz);
-int m_ftrapne(WORD inst, WORD siz);
-int m_ftrapgt(WORD inst, WORD siz);
-int m_ftrapngt(WORD inst, WORD siz);
-int m_ftrapge(WORD inst, WORD siz);
-int m_ftrapnge(WORD inst, WORD siz);
-int m_ftraplt(WORD inst, WORD siz);
-int m_ftrapnlt(WORD inst, WORD siz);
-int m_ftraple(WORD inst, WORD siz);
-int m_ftrapnle(WORD inst, WORD siz);
-int m_ftrapgl(WORD inst, WORD siz);
-int m_ftrapngl(WORD inst, WORD siz);
-int m_ftrapgle(WORD inst, WORD siz);
-int m_ftrapngle(WORD inst, WORD siz);
-int m_ftrapogt(WORD inst, WORD siz);
-int m_ftrapule(WORD inst, WORD siz);
-int m_ftrapoge(WORD inst, WORD siz);
-int m_ftrapult(WORD inst, WORD siz);
-int m_ftrapolt(WORD inst, WORD siz);
-int m_ftrapuge(WORD inst, WORD siz);
-int m_ftrapole(WORD inst, WORD siz);
-int m_ftrapugt(WORD inst, WORD siz);
-int m_ftrapogl(WORD inst, WORD siz);
-int m_ftrapueq(WORD inst, WORD siz);
-int m_ftrapor(WORD inst, WORD siz);
-int m_ftrapun(WORD inst, WORD siz);
-int m_ftrapf(WORD inst, WORD siz);
-int m_ftrapt(WORD inst, WORD siz);
-int m_ftrapsf(WORD inst, WORD siz);
-int m_ftrapst(WORD inst, WORD siz);
-int m_ftrapseq(WORD inst, WORD siz);
-int m_ftrapsne(WORD inst, WORD siz);
-int m_ftrapeqn(WORD inst, WORD siz);
-int m_ftrapnen(WORD inst, WORD siz);
-int m_ftrapgtn(WORD inst, WORD siz);
-int m_ftrapngtn(WORD inst, WORD siz);
-int m_ftrapgen(WORD inst, WORD siz);
-int m_ftrapngen(WORD inst, WORD siz);
-int m_ftrapltn(WORD inst, WORD siz);
-int m_ftrapnltn(WORD inst, WORD siz);
-int m_ftraplen(WORD inst, WORD siz);
-int m_ftrapnlen(WORD inst, WORD siz);
-int m_ftrapgln(WORD inst, WORD siz);
-int m_ftrapngln(WORD inst, WORD siz);
-int m_ftrapglen(WORD inst, WORD siz);
-int m_ftrapnglen(WORD inst, WORD siz);
-int m_ftrapogtn(WORD inst, WORD siz);
-int m_ftrapulen(WORD inst, WORD siz);
-int m_ftrapogen(WORD inst, WORD siz);
-int m_ftrapultn(WORD inst, WORD siz);
-int m_ftrapoltn(WORD inst, WORD siz);
-int m_ftrapugen(WORD inst, WORD siz);
-int m_ftrapolen(WORD inst, WORD siz);
-int m_ftrapugtn(WORD inst, WORD siz);
-int m_ftrapogln(WORD inst, WORD siz);
-int m_ftrapueqn(WORD inst, WORD siz);
-int m_ftraporn(WORD inst, WORD siz);
-int m_ftrapunn(WORD inst, WORD siz);
-int m_ftrapfn(WORD inst, WORD siz);
-int m_ftraptn(WORD inst, WORD siz);
-int m_ftrapsfn(WORD inst, WORD siz);
-int m_ftrapstn(WORD inst, WORD siz);
-int m_ftrapseqn(WORD inst, WORD siz);
-int m_ftrapsnen(WORD inst, WORD siz);
+int m_ftrapcc(WORD inst, WORD siz);
 
 // Common error messages
 char range_error[] = "expression out of range";
@@ -290,9 +168,9 @@ char unsupport[] = "unsupported for selected CPU";
 
 // Include code tables
 MNTAB machtab[] = {
-   { 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0
-   #include "68ktab.h"
-   {  0,  0L,  0L, 0x0000, 0, m_unimp   }            // Last entry
+	{ 0xFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000, 0, m_badmode }, // 0
+#include "68ktab.h"
+	{  0,  0L,  0L, 0x0000, 0, m_unimp   }            // Last entry
 };
 
 // Register number << 9
@@ -330,10 +208,10 @@ WORD lwsiz_8[] = {
 // Byte/Word/long size (0=.w, 1=.l) in bit 9
 WORD lwsiz_9[] = {
 	(WORD)-1,
-	0,                                                      // Byte
-	1<<9, (WORD)-1,                                         // Word
-	1<<10, (WORD)-1, (WORD)-1, (WORD)-1,                    // Long
-	1<<9                                                    // Word (SIZN)
+	0,                                               // Byte
+	1<<9, (WORD)-1,                                  // Word
+	1<<10, (WORD)-1, (WORD)-1, (WORD)-1,             // Long
+	1<<9                                             // Word (SIZN)
 };
 
 // Addressing mode in bits 6..11 (register/mode fields are reversed)
@@ -469,11 +347,11 @@ int m_ea(WORD inst, WORD siz)
 //
 int m_lea(WORD inst, WORD siz)
 {
-	if (optim_flags[OPT_LEA_ADDQ]
+	if (CHECK_OPTS(OPT_LEA_ADDQ)
 		&& ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED))
 		&& ((a0exval > 0) && (a0exval <= 8)))
 	{
-		inst = B16(01010000, 01001000) | ((a0exval & 7) << 9) | (a0reg);
+		inst = B16(01010000, 01001000) | (((uint16_t)a0exval & 7) << 9) | (a0reg);
 		D_word(inst);
 		warn("lea size(An),An converted to addq #size,An");
 		return OK;
@@ -703,8 +581,6 @@ int m_bitop(WORD inst, WORD siz)
 
 int m_dbra(WORD inst, WORD siz)
 {
-	VALUE v;
-
 	siz = siz;
 	inst |= a0reg;
 	D_word(inst);
@@ -714,7 +590,7 @@ int m_dbra(WORD inst, WORD siz)
 		if ((a1exattr & TDB) != cursect)
 			return error(rel_error);
 
-		v = a1exval - sloc;
+		uint32_t v = a1exval - sloc;
 
 		if (v + 0x8000 > 0x10000)
 			return error(range_error);
@@ -741,14 +617,14 @@ int m_exg(WORD inst, WORD siz)
 	siz = siz;
 
 	if (am0 == DREG && am1 == DREG)
-		m = 0x0040;                                           // Dn,Dn
+		m = 0x0040;                      // Dn,Dn
 	else if (am0 == AREG && am1 == AREG)
-		m = 0x0048;                                           // An,An
+		m = 0x0048;                      // An,An
 	else
 	{
 		if (am0 == AREG)
-		{                                     // Dn,An or An,Dn
-			m = a1reg;                                         // Get AREG into a1reg
+		{                                // Dn,An or An,Dn
+			m = a1reg;                   // Get AREG into a1reg
 			a1reg = a0reg;
 			a0reg = m;
 		}
@@ -789,22 +665,22 @@ int m_link(WORD inst, WORD siz)
 
 WORD extra_addressing[16]=
 {
-	0,     //0100 (bd,An,Xn)
-	0,     //0101 ([bd,An],Xn,od)
-	0x180, //0102 ([bc,An,Xn],od) (111 110 110 111)
-	0,     //0103 (bd,PC,Xn)
-	0,     //0104 ([bd,PC],Xn,od)
-	0,     //0105 ([bc,PC,Xn],od)
-	0,     //0106
-	0,     //0107
-	0,     //0110
-	0,     //0111 Nothing
-	0x30,  //0112 (Dn.w)
-	0x30,  //0113 (Dn.l)
-	0,     //0114
-	0,     //0115
-	0,     //0116
-	0      //0117
+	0,     // 0100 (bd,An,Xn)
+	0,     // 0101 ([bd,An],Xn,od)
+	0x180, // 0102 ([bc,An,Xn],od) (111 110 110 111)
+	0,     // 0103 (bd,PC,Xn)
+	0,     // 0104 ([bd,PC],Xn,od)
+	0,     // 0105 ([bc,PC,Xn],od)
+	0,     // 0106
+	0,     // 0107
+	0,     // 0110
+	0,     // 0111 Nothing
+	0x30,  // 0112 (Dn.w)
+	0x30,  // 0113 (Dn.l)
+	0,     // 0114
+	0,     // 0115
+	0,     // 0116
+	0      // 0117
 };
 
 
@@ -820,10 +696,12 @@ int m_move(WORD inst, WORD size)
 	int siz = (int)size;
 
 	// Try to optimize to MOVEQ
-	if (optim_flags[OPT_MOVEL_MOVEQ]
+	// N.B.: We can get away with casting the uint64_t to a 32-bit value
+	//       because it checks for a SIZL (i.e., a 32-bit value).
+	if (CHECK_OPTS(OPT_MOVEL_MOVEQ)
 		&& (siz == SIZL) && (am0 == IMMED) && (am1 == DREG)
 		&& ((a0exattr & (TDB | DEFINED)) == DEFINED)
-		&& (a0exval + 0x80 < 0x100))
+		&& ((uint32_t)a0exval + 0x80 < 0x100))
 	{
 		m_moveq((WORD)0x7000, (WORD)0);
 
@@ -832,7 +710,7 @@ int m_move(WORD inst, WORD size)
 	}
 	else
 	{
-		if ((am0 < ABASE) && (am1 < ABASE))			//68000 modes
+		if ((am0 < ABASE) && (am1 < ABASE))			// 68000 modes
 		{
 			inst |= siz_12[siz] | am_6[am1] | reg_9[a1reg] | am0 | a0reg;
 
@@ -844,7 +722,7 @@ int m_move(WORD inst, WORD size)
 			if (am1 >= ADISP)
 				ea1gen((WORD)siz | 0x8000);   // Tell ea1gen we're move ea,ea
 		}
-		else					//68020+ modes
+		else					// 68020+ modes
 		{
 			inst |= siz_12[siz] | reg_9[a1reg] | extra_addressing[am0 - ABASE];
 
@@ -861,15 +739,17 @@ int m_move(WORD inst, WORD size)
 	return OK;
 }
 
+
 //
 // Handle MOVE <C_ALL030> <C_ALTDATA>
 //        MOVE <C_ALL030> <M_AREG>
 //
 int m_move30(WORD inst, WORD size)
 {
-	// Cast the passed in value to an int
 	int siz = (int)size;
-	inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
+	// TODO: is extra_addressing necessary/correct?
+	//inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
+	inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg;
 
 	D_word(inst);
 
@@ -914,7 +794,7 @@ int m_moveq(WORD inst, WORD siz)
 		AddFixup(FU_BYTE | FU_SEXT, sloc + 1, a0expr);
 		a0exval = 0;
 	}
-	else if (a0exval + 0x100 >= 0x200)
+	else if ((uint32_t)a0exval + 0x100 >= 0x200)
 		return error(range_error);
 
 	inst |= reg_9[a1reg] | (a0exval & 0xFF);
@@ -930,7 +810,7 @@ int m_moveq(WORD inst, WORD siz)
 int m_movep(WORD inst, WORD siz)
 {
 	// Tell ea0gen to lay off the 0(a0) optimisations on this one
-    movep = 1;
+	movep = 1;
 
 	if (siz == SIZL)
 		inst |= 0x0040;
@@ -956,7 +836,7 @@ int m_movep(WORD inst, WORD siz)
 			ea0gen(siz);
 	}
 
-    movep = 0;
+	movep = 0;
 	return 0;
 }
 
@@ -966,8 +846,6 @@ int m_movep(WORD inst, WORD siz)
 //
 int m_br(WORD inst, WORD siz)
 {
-	VALUE v;
-
 	if (a0exattr & DEFINED)
 	{
 		if ((a0exattr & TDB) != cursect)
@@ -976,12 +854,12 @@ int m_br(WORD inst, WORD siz)
 			return error(rel_error);
 //}
 
-		v = a0exval - (sloc + 2);
+		uint32_t v = (uint32_t)a0exval - (sloc + 2);
 
 		// Optimize branch instr. size
 		if (siz == SIZN)
 		{
-			if (optim_flags[OPT_BSR_BCC_S] && (v != 0) && ((v + 0x80) < 0x100))
+			if (CHECK_OPTS(OPT_BSR_BCC_S) && (v != 0) && ((v + 0x80) < 0x100))
 			{
 				// Fits in .B
 				inst |= v & 0xFF;
@@ -1102,7 +980,7 @@ int m_trap(WORD inst, WORD siz)
 //
 int m_movem(WORD inst, WORD siz)
 {
-	VALUE eval;
+	uint64_t eval;
 	WORD i;
 	WORD w;
 	WORD rmask;
@@ -1210,6 +1088,22 @@ int m_clra(WORD inst, WORD siz)
 }
 
 
+//
+// CLR.L Dn ==> CLR.L An or MOVEQ #0,Dx
+//
+int m_clrd(WORD inst, WORD siz)
+{
+	if (!CHECK_OPTS(OPT_CLR_DX))
+		inst |= a0reg;
+	else
+		inst = (a0reg << 9) | B16(01110000, 00000000);
+
+	D_word(inst);
+
+	return OK;
+}
+
+
 ////////////////////////////////////////
 //
 // 68020/30/40 instructions
@@ -1226,7 +1120,7 @@ int m_br30(WORD inst, WORD siz)
 		if ((a0exattr & TDB) != cursect)
 			return error(rel_error);
 
-		VALUE v = a0exval - (sloc + 2);
+		uint32_t v = (uint32_t)a0exval - (sloc + 2);
 		D_word(inst);
 		D_long(v);
 
@@ -1248,23 +1142,39 @@ int m_br30(WORD inst, WORD siz)
 //
 int m_bfop(WORD inst, WORD siz)
 {
-	//TODO: is this needed or can we put that in the mask in 68ktab???
-	if (am0 == AREG || am0== APOSTINC || am0 == APREDEC || am0 == IMMED|| am0 == ABASE || am0 == MEMPOST || am0 == MEMPRE || am0 == PCBASE || am0 == PCMPOST || am0 == PCMPRE)
-		return m_badmode(inst, siz);
+	if ((bfval1 > 31) || (bfval1 < 0))
+		return error("bfxxx offset: immediate value must be between 0 and 31");
 
-	//First instruction word - just the opcode and first EA
-	//Note: both am1 is ORed because solely of bfins - maybe it's a good idea to make a dedicated function for it?
+	// First instruction word - just the opcode and first EA
+	// Note: both am1 is ORed because solely of bfins - maybe it's a good idea
+	// to make a dedicated function for it?
 	if (am1 == AM_NONE)
+	{
 		am1 = 0;
+	}
+	else
+	{
+		if (bfval2 > 31 || bfval2 < 0)
+			return error("bfxxx width: immediate value must be between 0 and 31");
+
+		// For Dw both immediate and register number are stuffed
+		// into the same field O_o
+		bfparam2 = (bfval2 << 0);
+	}
+
+	if (bfparam1 == 0)
+		bfparam1 = (bfval1 << 6);
+	else
+		bfparam1 = bfval1 << 12;
 
-	D_word((inst|am0|a0reg|am1|a1reg));
+	D_word((inst | am0 | a0reg | am1 | a1reg));
 	ea0gen(siz);	// Generate EA
 
-	//Second instruction word - Dest register (if exists), Do, Offset, Dw, Width
+	// Second instruction word - Dest register (if exists), Do, Offset, Dw, Width
 	inst = bfparam1 | bfparam2;
 
 	if (am1 == DREG)
-		inst |= a1reg << 12;
+		inst |= a1reg << 0;
 
 	if (am0 == DREG)
 		inst |= a0reg << 12;
@@ -1318,13 +1228,13 @@ int m_callm(WORD inst, WORD siz)
 		if (a0exval > 255)
 			return error(range_error);
 
-		inst = a0exval;
+		inst = (uint16_t)a0exval;
 		D_word(inst);
 	}
 	else
 		return error(undef_error);
 
-    ea1gen(siz);
+	ea1gen(siz);
 
 	return OK;
 
@@ -1385,7 +1295,7 @@ int m_cas(WORD inst, WORD siz)
 	if (modes > 1)
 		return error("too many ea fields");
 
-	if (*tok!=EOL)
+	if (*tok != EOL)
 		return error("extra (unexpected) text found");
 
 	// Reject invalud ea modes
@@ -1604,7 +1514,7 @@ int m_cpbr(WORD inst, WORD siz)
 		if ((a0exattr & TDB) != cursect)
 			return error(rel_error);
 
-		VALUE v = a0exval - (sloc + 2);
+		uint32_t v = (uint32_t)a0exval - (sloc + 2);
 
 		// Optimize branch instr. size
 		if (siz == SIZL)
@@ -1634,9 +1544,9 @@ int m_cpbr(WORD inst, WORD siz)
 	if (siz == SIZL)
 	{
 		// .L
-        D_word(inst);
-        AddFixup(FU_LONG | FU_PCREL | FU_SEXT, sloc, a0expr);
-        D_long(0);
+		D_word(inst);
+		AddFixup(FU_LONG | FU_PCREL | FU_SEXT, sloc, a0expr);
+		D_long(0);
 		return OK;
 	}
 	else
@@ -1656,12 +1566,38 @@ int m_cpbr(WORD inst, WORD siz)
 //
 int m_cpdbr(WORD inst, WORD siz)
 {
-	if ((activecpu & (CPU_68020 | CPU_68030)) == 0)
-		return error(unsupport);
+	CHECK00;
 
-	return error("Not implemented yet.");
+	uint32_t v;
+	WORD condition = inst & 0x1F; // Grab condition sneakily placed in the lower 5 bits of inst
+	inst &= 0xFFE0;               // And then mask them out - you ain't seen me, roit?
+
+	inst |= (1 << 9);	// Bolt on FPU id
+	inst |= a0reg;
 
-	//return OK;
+	D_word(inst);
+
+	D_word(condition);
+
+	if (a1exattr & DEFINED)
+	{
+		if ((a1exattr & TDB) != cursect)
+			return error(rel_error);
+
+		v = (uint32_t)a1exval - sloc;
+
+		if (v + 0x8000 > 0x10000)
+			return error(range_error);
+
+		D_word(v);
+	}
+	else
+	{
+		AddFixup(FU_WORD | FU_PCREL | FU_ISBRA, sloc, a1expr);
+		D_word(0);
+	}
+
+	return OK;
 }
 
 
@@ -1952,6 +1888,7 @@ int m_divsl(WORD inst, WORD siz)
 	return OK;
 }
 
+
 //
 // divul.l
 //
@@ -2044,7 +1981,7 @@ int m_move16b(WORD inst, WORD siz)
 		{
 			//move16 (ax)+,(xxx).L
 			inst |= 0 << 3;
-			v = a1exval;
+			v = (int)a1exval;
 		}
 	}
 	else if (am0 == ABSL)
@@ -2053,20 +1990,20 @@ int m_move16b(WORD inst, WORD siz)
 		{
 			//move16 (xxx).L,(ax)+
 			inst |= 1 << 3;
-			v = a0exval;
+			v = (int)a0exval;
 		}
 		else //APOSTINC
 		{
 			//move16 (xxx).L,(ax)
 			inst |= 3 << 3;
-			v = a0exval;
+			v = (int)a0exval;
 		}
 	}
 	else if (am0 == AIND)
 	{
 		//move16 (ax),(xxx).L
 		inst |= 2 << 3;
-		v = a1exval;
+		v = (int)a1exval;
 	}
 
 	D_word(inst);
@@ -2077,29 +2014,72 @@ int m_move16b(WORD inst, WORD siz)
 
 
 //
-// pack/unpack
+// pack/unpack (68020/68030/68040)
 //
 int m_pack(WORD inst, WORD siz)
 {
-	if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
-		return error(unsupport);
+	CHECK00;
 
-	WARNING(Parsing stuff by hand here might be better)
+	if (siz != SIZN)
+		return error("bad size suffix");
 
-#if 0
-	if ((am0 == DREG) && (am1 == DREG))
+	if (*tok >= KW_D0 && *tok <= KW_D7)
 	{
-		inst |= (1 << 3) + (a0reg << 9) + (a1reg);
+		// Dx,Dy,#<adjustment>
+		inst |= (0 << 3);   // R/M
+		inst |= (*tok++ & 7);
+
+		if (*tok != ',' && tok[2] != ',')
+			return error("missing comma");
+
+		if (tok[1] < KW_D0 && tok[1] > KW_D7)
+			return error(syntax_error);
+
+		inst |= ((tok[1] & 7)<<9);
+		tok = tok + 3;
+		D_word(inst);
+		// Fall through for adjustment (common in both valid cases)
 	}
-	else if ((am0 == APREDEC) && (am1 == APREDEC))
+	else if (*tok == '-')
 	{
-		inst |= (a0reg << 9) + (a1reg);
+		// -(Ax),-(Ay),#<adjustment>
+		inst |= (1 << 3);   // R/M
+		tok++;  // eat the minus
+
+		if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ','))
+			return error(syntax_error);
+
+		if (tok[1] < KW_A0 && tok[1] > KW_A7)
+			return error(syntax_error);
+
+		if (tok[5] < KW_A0 && tok[6] > KW_A7)
+			return error(syntax_error);
+
+		inst |= ((tok[1] & 7) << 0);
+		inst |= ((tok[6] & 7) << 9);
+		tok = tok + 9;
+		D_word(inst);
+		// Fall through for adjustment (common in both valid cases)
 	}
 	else
-		return error("Only allowed combinations for pack/unpack are -(ax),-(ay) and dx,dy.");
+		return error("invalid syntax");
 
-	D_word(inst);
-#endif
+	if ((*tok != CONST) && (*tok != SYMBOL) && (*tok != '-'))
+		return error(syntax_error);
+
+	if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR)
+		return ERROR;
+
+	if ((a0exattr & DEFINED) == 0)
+		return error(undef_error);
+
+	if (a0exval + 0x8000 > 0x10000)
+		return error("");
+
+	if (*tok != EOL)
+		return error(extra_stuff);
+
+	D_word((a0exval & 0xFFFF));
 
 	return OK;
 }
@@ -2193,21 +2173,26 @@ int m_trapcc(WORD inst, WORD siz)
 
 
 //
-// cinv (68040)
+// cinvl/p/a (68040)
 //
 int m_cinv(WORD inst, WORD siz)
 {
 	CHECKNO40;
-	WARNING("cinvl ,(an) / cinvp ,(an) / cinva should work!")
 
-	if (am0 == AM_NONE)
+	if (am1 == AM_NONE)
 		inst |= (0 << 6) | (a1reg);
-	else if (am0 == KW_IC40)
+	switch (a0reg)
+	{
+	case 0:     // KW_IC40
 		inst |= (2 << 6) | (a1reg);
-	else if (am0 == KW_DC40)
+		break;
+	case 1:     // KW_DC40
 		inst |= (1 << 6) | (a1reg);
-	else if (am0 == KW_BC40)
+		break;
+	case 2:     // KW_BC40
 		inst |= (3 << 6) | (a1reg);
+		break;
+	}
 
 	D_word(inst);
 	return OK;
@@ -2284,17 +2269,11 @@ int m_moves(WORD inst, WORD siz)
 		return error(unsupport);
 
 	if (siz == SIZB)
-	{
 		inst |= 0 << 6;
-	}
 	else if (siz == SIZL)
-	{
 		inst |= 2 << 6;
-	}
 	else // SIZW/SIZN
-	{
 		inst |= 1 << 6;
-	}
 
 	if (am0 == DREG)
 	{
@@ -2343,15 +2322,26 @@ int m_pbcc(WORD inst, WORD siz)
 
 
 //
-// pflusha (68030)
+// pflusha (68030, 68040)
 //
 int m_pflusha(WORD inst, WORD siz)
 {
-	CHECKNO30;
+	if (activecpu == CPU_68030)
+	{
+		D_word(inst);
+		inst = (1 << 13) | (1 << 10) | (0 << 5) | 0;
+		D_word(inst);
+		return OK;
+	}
+	else if (activecpu == CPU_68040)
+	{
+		inst = B16(11110101, 00011000);
+		D_word(inst);
+		return OK;
+	}
+	else
+		return error(unsupport);
 
-	D_word(inst);
-	inst = (1 << 13) | (1 << 10) | (0 << 5) | 0;
-	D_word(inst);
 	return OK;
 }
 
@@ -2363,12 +2353,132 @@ int m_pflush(WORD inst, WORD siz)
 {
 	if (activecpu == CPU_68030)
 	{
-		D_word(inst);
-		D_word((1 << 13) | (1 << 10) | (0 << 5) | 0);
+		// PFLUSH FC, MASK
+		// PFLUSH FC, MASK, < ea >
+		WORD mask, fc;
+
+		switch ((int)*tok)
+		{
+		case '#':
+			tok++;
+
+			if (*tok != CONST && *tok != SYMBOL)
+				return error("function code should be an expression");
+
+			if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR)
+				return ERROR;
+
+			if ((a0exattr & DEFINED) == 0)
+				return error("function code immediate should be defined");
+
+			if (a0exval > 7 && a0exval < 0)
+				return error("function code out of range (0-7)");
+
+			fc = (uint16_t)a0exval;
+			break;
+		case KW_D0:
+		case KW_D1:
+		case KW_D2:
+		case KW_D3:
+		case KW_D4:
+		case KW_D5:
+		case KW_D6:
+		case KW_D7:
+			fc = (1 << 4) | (*tok++ & 7);
+			break;
+		case KW_SFC:
+			fc = 0;
+			tok++;
+			break;
+		case KW_DFC:
+			fc = 1;
+			tok++;
+			break;
+		default:
+			return error(syntax_error);
+		}
+
+		if (*tok++ != ',')
+			return error("comma exptected");
+
+		if (*tok++ != '#')
+			return error("mask should be an immediate value");
+
+		if (*tok != CONST && *tok != SYMBOL)
+			return error("mask is supposed to be immediate");
+
+		if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR)
+			return ERROR;
+
+		if ((a0exattr & DEFINED) == 0)
+			return error("mask immediate value should be defined");
+
+		if (a0exval > 7 && a0exval < 0)
+			return error("function code out of range (0-7)");
+
+		mask = (uint16_t)a0exval << 5;
+
+		if (*tok == EOL)
+		{
+			// PFLUSH FC, MASK
+			D_word(inst);
+			inst = (1 << 13) | fc | mask | (4 << 10);
+			D_word(inst);
+			return OK;
+		}
+		else if (*tok == ',')
+		{
+			// PFLUSH FC, MASK, < ea >
+			tok++;
+
+			if (amode(0) == ERROR)
+				return ERROR;
+
+			if (*tok != EOL)
+				return error(extra_stuff);
+
+			if (am0 == AIND || am0 == ABSW || am0 == ABSL || am0 == ADISP || am0 == ADISP || am0 == AINDEXED || am0 == ABASE || am0 == MEMPOST || am0 == MEMPRE)
+			{
+				inst |= am0 | a0reg;
+				D_word(inst);
+				inst = (1 << 13) | fc | mask | (6 << 10);
+				D_word(inst);
+				ea0gen(siz);
+				return OK;
+			}
+			else
+				return error("unsupported addressing mode");
+
+		}
+		else
+			return error(syntax_error);
+
+		return OK;
 	}
 	else if (activecpu == CPU_68040 || activecpu == CPU_68060)
 	{
-		D_word(0xf918);
+		// PFLUSH(An)
+		// PFLUSHN(An)
+		if (*tok != '(' && tok[2] != ')')
+			return error(syntax_error);
+
+		if (tok[1] < KW_A0 && tok[1] > KW_A7)
+			return error("expected (An)");
+
+		if ((inst & 7) == 7)
+			// With pflushn/pflush there's no easy way to distinguish between
+			// the two in 68040 mode. Ideally the opcode bitfields would have
+			// been hardcoded in 68ktab but there is aliasing between 68030
+			// and 68040 opcode. So we just set the 3 lower bits to 1 in
+			// pflushn inside 68ktab and detect it here.
+			inst = (inst & 0xff8) | 8;
+
+		inst |= (tok[1] & 7) | (5 << 8);
+
+		if (tok[3] != EOL)
+			return error(extra_stuff);
+
+		D_word(inst);
 	}
 	else
 		return error(unsupport);
@@ -2378,7 +2488,7 @@ int m_pflush(WORD inst, WORD siz)
 
 
 //
-// pflushr (68551)
+// pflushr (68851)
 //
 int m_pflushr(WORD inst, WORD siz)
 {
@@ -2432,24 +2542,73 @@ int m_pflushr(WORD inst, WORD siz)
 //
 // ploadr, ploadw (68030)
 //
-int m_pload(WORD inst, WORD siz)
+int m_pload(WORD inst, WORD siz, WORD extension)
 {
+	// TODO: 68851 support is not added yet.
+	// None of the ST series of computers had a 68020 + 68851 socket and since
+	// this is an Atari targetted assembler...
 	CHECKNO30;
-	return error("Not implemented yet.");
+
+	inst |= am1;
+	D_word(inst);
+
+	switch (am0)
+	{
+	case CREG:
+		if (a0reg == KW_SFC - KW_SFC)
+			inst = 0;
+		else if (a0reg == KW_DFC - KW_SFC)
+			inst = 1;
+		else
+			return error("illegal control register specified");
+
+		break;
+	case DREG:
+		inst = (1 << 3) | a0reg;
+		break;
+	case IMMED:
+		if ((a0exattr & DEFINED) == 0)
+			return error("constant value must be defined");
+
+		inst = (2 << 3) | (uint16_t)a0exval;
+		break;
+	}
+
+	inst |= extension | (1 << 13);
+	D_word(inst);
+
+	ea1gen(siz);
+
+	return OK;
+}
+
+
+int m_ploadr(WORD inst, WORD siz)
+{
+	return m_pload(inst, siz, 1 << 9);
+}
+
+
+int m_ploadw(WORD inst, WORD siz)
+{
+	return m_pload(inst, siz, 0 << 9);
 }
 
 
 //
-// pmove (68030)
+// pmove (68030/68851)
 //
 int m_pmove(WORD inst, WORD siz)
 {
 	int inst2,reg;
 
+	// TODO: 68851 support is not added yet. None of the ST series of
+	// computers had a 68020 + 68851 socket and since this is an Atari
+	// targetted assembler.... (same for 68EC030)
 	CHECKNO30;
 
-	inst2 = inst & (1 << 8); //Copy the flush bit over to inst2 in case we're called from m_pmovefd
-	inst &= ~(1 << 8);		//And mask it out
+	inst2 = inst & (1 << 8);	// Copy the flush bit over to inst2 in case we're called from m_pmovefd
+	inst &= ~(1 << 8);			// And mask it out
 
 	if (am0 == CREG)
 	{
@@ -2464,6 +2623,12 @@ int m_pmove(WORD inst, WORD siz)
 	else
 		return error("pmove sez: Wut?");
 
+	// The instruction is a quad-word (8 byte) operation
+	// for the CPU root pointer and the supervisor root pointer.
+	// It is a long - word operation for the translation control register
+	// and the transparent translation registers(TT0 and TT1).
+	// It is a word operation for the MMU status register.
+
 	if (((reg == (KW_URP - KW_SFC)) || (reg == (KW_SRP - KW_SFC)))
 		&& ((siz != SIZD) && (siz != SIZN)))
 		return error(siz_error);
@@ -2475,41 +2640,47 @@ int m_pmove(WORD inst, WORD siz)
 	if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN)))
 		return error(siz_error);
 
-	WARNING(Not all addressing modes are legal here!)
-
 	if (am0 == CREG)
 	{
-		inst |= am1;
+		inst |= am1 | a1reg;
 		D_word(inst);
-		ea1gen(siz);
 	}
 	else if (am1 == CREG)
 	{
-		inst |= am0;
+    	inst |= am0 | a0reg;
 		D_word(inst);
-		ea0gen(siz);
 	}
 
-	switch (reg)
+	switch (reg + KW_SFC)
 	{
-	case (KW_URP - KW_SFC):
-		inst2 |= (3 << 10) + (2 << 13); break;
-	case (KW_SRP - KW_SFC):
-		inst2 |= (2 << 10) + (2 << 13); break;
-	case (KW_TC - KW_SFC):
-		inst2 |= (0 << 10) + (2 << 13); break;
-	case (KW_TT0 - KW_SFC):
+	case KW_TC:
+		inst2 |= (0 << 10) + (1 << 14); break;
+	case KW_SRP:
+		inst2 |= (2 << 10) + (1 << 14); break;
+	case KW_CRP:
+		inst2 |= (3 << 10) + (1 << 14); break;
+	case KW_TT0:
 		inst2 |= (2 << 10) + (0 << 13); break;
-	case (KW_TT1 - KW_SFC):
+	case KW_TT1:
 		inst2 |= (3 << 10) + (0 << 13); break;
-	case (KW_MMUSR - KW_SFC):
-		inst2 |= (3 << 10) + (3 << 13); break;
-	case (KW_CRP - KW_SFC) :	//68851 only
-		inst2 |= (3 << 10) + (2 << 13); break;
+	case KW_MMUSR:
+		if (am0 == CREG)
+			inst2 |= (1 << 9) + (3 << 13);
+		else
+			inst2 |= (0 << 9) + (3 << 13);
+		break;
+	default:
+		return error("unsupported register");
+		break;
 	}
 
 	D_word(inst2);
 
+	if (am0 == CREG)
+		ea1gen(siz);
+	else if (am1 == CREG)
+		ea0gen(siz);
+
 	return OK;
 }
 
@@ -2528,38 +2699,37 @@ int m_pmovefd(WORD inst, WORD siz)
 //
 // ptrapcc (68851)
 //
-int m_ptrapbs(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000000)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000000)); D_long(a0exval); } return OK; }
-int m_ptrapbc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000001)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000001)); D_long(a0exval); } return OK; }
-int m_ptrapls(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000010)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000010)); D_long(a0exval); } return OK; }
-int m_ptraplc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000011)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000011)); D_long(a0exval); } return OK; }
-int m_ptrapss(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000100)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000100)); D_long(a0exval); } return OK; }
-int m_ptrapsc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000101)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000101)); D_long(a0exval); } return OK; }
-int m_ptrapas(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000110)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000110)); D_long(a0exval); } return OK; }
-int m_ptrapac(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00000111)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00000111)); D_long(a0exval); } return OK; }
-int m_ptrapws(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001000)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001000)); D_long(a0exval); } return OK; }
-int m_ptrapwc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001001)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001001)); D_long(a0exval); } return OK; }
-int m_ptrapis(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001010)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001010)); D_long(a0exval); } return OK; }
-int m_ptrapic(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001011)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001011)); D_long(a0exval); } return OK; }
-int m_ptrapgc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001100)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001100)); D_long(a0exval); } return OK; }
-int m_ptrapgs(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001101)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001101)); D_long(a0exval); } return OK; }
-int m_ptrapcs(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001110)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001110)); D_long(a0exval); } return OK; }
-int m_ptrapcc(WORD inst, WORD siz) { CHECKNO20; if (siz == SIZW) { D_word(inst); D_word(B8(00001111)); D_word(a0exval); } else { inst |= 3; D_word(inst); D_word(B8(00001111)); D_long(a0exval); } return OK; }
-int m_ptrapbsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000000)); return OK; }
-int m_ptrapbcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000001)); return OK; }
-int m_ptraplsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000010)); return OK; }
-int m_ptraplcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000011)); return OK; }
-int m_ptrapssn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000100)); return OK; }
-int m_ptrapscn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000101)); return OK; }
-int m_ptrapasn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000110)); return OK; }
-int m_ptrapacn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00000111)); return OK; }
-int m_ptrapwsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001000)); return OK; }
-int m_ptrapwcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001001)); return OK; }
-int m_ptrapisn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001010)); return OK; }
-int m_ptrapicn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001011)); return OK; }
-int m_ptrapgsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001100)); return OK; }
-int m_ptrapgcn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001101)); return OK; }
-int m_ptrapcsn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001110)); return OK; }
-int m_ptrapccn(WORD inst, WORD siz) { CHECKNO20; D_word(inst); D_word(B8(00001111)); return OK; }
+int m_ptrapcc(WORD inst, WORD siz)
+{
+    CHECKNO20;
+	// We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4),
+	// so we need to extract them first and fill in the clobbered bits.
+	WORD opcode = inst & 0x1F;
+	inst = (inst & 0xFFE0) | (0x18);
+
+	if (siz == SIZW)
+	{
+		inst |= 2;
+		D_word(inst);
+		D_word(opcode);
+		D_word(a0exval);
+	}
+	else if (siz == SIZL)
+	{
+		inst |= 3;
+		D_word(inst);
+		D_word(opcode);
+		D_long(a0exval);
+	}
+	else if (siz == SIZN)
+	{
+		inst |= 4;
+		D_word(inst);
+		D_word(opcode);
+	}
+
+	return OK;
+}
 
 
 //
@@ -2602,7 +2772,7 @@ static inline int gen_fpu(WORD inst, WORD siz, WORD opmode, WORD emul)
 
 		switch (siz)
 		{
-		case SIZB: 	inst |= (6 << 10); break;
+		case SIZB:	inst |= (6 << 10); break;
 		case SIZW:	inst |= (4 << 10); break;
 		case SIZL:	inst |= (0 << 10); break;
 		case SIZN:
@@ -2628,7 +2798,7 @@ static inline int gen_fpu(WORD inst, WORD siz, WORD opmode, WORD emul)
 	}
 	else
 	{
-		inst |= (1 << 9);	//Bolt on FPU id
+		inst |= (1 << 9);	// Bolt on FPU id
 		D_word(inst);
 		inst = 0;
 		inst = a0reg << 10;
@@ -2657,8 +2827,8 @@ int m_fsabs(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01011000), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -2666,8 +2836,8 @@ int m_fdabs(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01011100), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -2693,8 +2863,8 @@ int m_fsadd(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01100010), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -2702,8 +2872,8 @@ int m_fdadd(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01100110), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -2766,7 +2936,7 @@ int m_fcosh(WORD inst, WORD siz)
 //
 int m_fdbcc(WORD inst, WORD siz)
 {
-	WORD opcode = inst & 0x3F;	//Grab conditional bitfield
+	WORD opcode = inst & 0x3F;	// Grab conditional bitfield
 
 	inst &= ~0x3F;
 	inst |= 1 << 3;
@@ -2781,7 +2951,7 @@ int m_fdbcc(WORD inst, WORD siz)
 		if ((a1exattr & TDB) != cursect)
 			return error(rel_error);
 
-		VALUE v = a1exval - sloc;
+		uint32_t v = (uint32_t)a1exval - sloc;
 
 		if ((v + 0x8000) > 0x10000)
 			return error(range_error);
@@ -2811,8 +2981,8 @@ int m_fsdiv(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01100000), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -2820,8 +2990,8 @@ int m_fddiv(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -2937,7 +3107,6 @@ int m_fmod(WORD inst, WORD siz)
 //
 int m_fmove(WORD inst, WORD siz)
 {
-
 	// EA to register
 	if ((am0 == FREG) && (am1 < AM_USP))
 	{
@@ -2949,36 +3118,40 @@ int m_fmove(WORD inst, WORD siz)
 		// R/M
 		inst = 3 << 13;
 
-		WARNING("K-factor logic is totally bogus - fix!")
-
 		// Source specifier
 		switch (siz)
 		{
-		case SIZB: 	inst |= (6 << 10); break;
+		case SIZB:	inst |= (6 << 10); break;
 		case SIZW:	inst |= (4 << 10); break;
 		case SIZL:	inst |= (0 << 10); break;
 		case SIZN:
 		case SIZS:	inst |= (1 << 10); break;
 		case SIZD:	inst |= (5 << 10); break;
 		case SIZX:	inst |= (2 << 10); break;
-		case SIZP:  inst |= (3 << 10);
+		case SIZP:	inst |= (3 << 10);
+			// In P size we have 2 cases: {#k} where k is immediate
+			// and {Dn} where Dn=Data register
 			if (bfparam1)
+			{
+				// Dn
 				inst |= 1 << 12;
+				inst |= bfval1 << 4;
+			}
+			else
+			{
+				// #k
+				if (bfval1 > 63 && bfval1 < -64)
+					return error("K-factor must be between -64 and 63");
+
+				inst |= bfval1 & 127;
+			}
 
-			inst |= (bfparam1 & 0x7FF) >> 2;
 			break;
 		default:
 			return error("Something bad happened, possibly.");
 			break;
 		}
 
-		// Immediate {} value
-		if (bf0exval >= (1 << 6))
-			return error("K-factor must be between 0 and 31");
-
-		if (!bfparam1 && (siz == SIZP))
-            inst |= bf0exval;
-
 		// Destination specifier
 		inst |= (a0reg << 7);
 
@@ -2990,7 +3163,7 @@ int m_fmove(WORD inst, WORD siz)
 	}
 	else if ((am0 < AM_USP) && (am1 == FREG))
 	{
-		//ea->fpx
+		// ea->fpx
 
 		// EA
 		inst |= am0 | a0reg;
@@ -3002,14 +3175,14 @@ int m_fmove(WORD inst, WORD siz)
 		// Source specifier
 		switch (siz)
 		{
-		case SIZB: 	inst |= (6 << 10); break;
+		case SIZB:	inst |= (6 << 10); break;
 		case SIZW:	inst |= (4 << 10); break;
 		case SIZL:	inst |= (0 << 10); break;
 		case SIZN:
 		case SIZS:	inst |= (1 << 10); break;
 		case SIZD:	inst |= (5 << 10); break;
 		case SIZX:	inst |= (2 << 10); break;
-		case SIZP:  inst |= (3 << 10); break;
+		case SIZP:	inst |= (3 << 10); break;
 		default:
 			return error("Something bad happened, possibly.");
 			break;
@@ -3081,10 +3254,9 @@ int m_fmovescr(WORD inst, WORD siz)
 		ea0gen(siz);
 		return OK;
 	}
-	else
-		return error("m_fmovescr says: wut?");
-}
 
+	return error("m_fmovescr says: wut?");
+}
 
 //
 // fsmove/fdmove (68040)
@@ -3141,7 +3313,7 @@ int m_fmovem(WORD inst, WORD siz)
 	WORD regmask;
 	WORD datareg;
 
-	if (siz == SIZX || siz==SIZN)
+	if (siz == SIZX || siz == SIZN)
 	{
 		if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
 		{
@@ -3309,7 +3481,7 @@ fmovem_loop_2:
 				goto fmovem_loop_2;
 			}
 
-			if (*tok!=EOL)
+			if (*tok != EOL)
 				return error("extra (unexpected) text found");
 
 			inst |= am0 | a0reg;
@@ -3374,8 +3546,8 @@ int m_fdneg(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01011110), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -3407,110 +3579,58 @@ int m_fscale(WORD inst, WORD siz)
 
 
 //
-// FScc (6888X, 68040)
-//
-int m_fseq  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000001)); return OK;}
-int m_fsne  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001110)); return OK;}
-int m_fsgt  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010010)); return OK;}
-int m_fsngt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011101)); return OK;}
-int m_fsge  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010011)); return OK;}
-int m_fsnge (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011100)); return OK;}
-int m_fslt  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010100)); return OK;}
-int m_fsnlt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011011)); return OK;}
-int m_fsle  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010101)); return OK;}
-int m_fsnle (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011010)); return OK;}
-int m_fsgl  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010110)); return OK;}
-int m_fsngl (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011001)); return OK;}
-int m_fsgle (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010111)); return OK;}
-int m_fsngle(WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011000)); return OK;}
-int m_fsogt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000010)); return OK;}
-int m_fsule (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001101)); return OK;}
-int m_fsoge (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000011)); return OK;}
-int m_fsult (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001100)); return OK;}
-int m_fsolt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000100)); return OK;}
-int m_fsuge (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001011)); return OK;}
-int m_fsole (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000101)); return OK;}
-int m_fsugt (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001010)); return OK;}
-int m_fsogl (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000110)); return OK;}
-int m_fsueq (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001001)); return OK;}
-int m_fsor  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000111)); return OK;}
-int m_fsun  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001000)); return OK;}
-int m_fsf   (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00000000)); return OK;}
-int m_fst   (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00001111)); return OK;}
-int m_fssf  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010000)); return OK;}
-int m_fsst  (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011111)); return OK;}
-int m_fsseq (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00010001)); return OK;}
-int m_fssne (WORD inst, WORD siz) { inst|=am0|a0reg; D_word(inst); ea0gen(siz); D_word(B8(00011110)); return OK;}
+// FScc (6888X, 68040), cpScc (68851, 68030), PScc (68851)
+// TODO: Add check for PScc to ensure 68020+68851 active
+// TODO: Add check for cpScc to ensure 68020+68851, 68030
+//
+int m_fscc(WORD inst, WORD siz)
+{
+	// We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0),
+	// so we need to extract them first and fill in the clobbered bits.
+	WORD opcode = inst & 0x1F;
+	inst &= 0xFFE0;
+	inst |= am0 | a0reg;
+	D_word(inst);
+	ea0gen(siz);
+	D_word(opcode);
+	return OK;
+}
 
 
 //
 // FTRAPcc (6888X, 68040)
 //
-int m_ftrapeq  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000001)); D_long(a0exval); } return OK;}
-int m_ftrapne  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001110)); D_long(a0exval); } return OK;}
-int m_ftrapgt  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010010)); D_long(a0exval); } return OK;}
-int m_ftrapngt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011101)); D_long(a0exval); } return OK;}
-int m_ftrapge  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010011)); D_long(a0exval); } return OK;}
-int m_ftrapnge (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011100)); D_long(a0exval); } return OK;}
-int m_ftraplt  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010100)); D_long(a0exval); } return OK;}
-int m_ftrapnlt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011011)); D_long(a0exval); } return OK;}
-int m_ftraple  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010101)); D_long(a0exval); } return OK;}
-int m_ftrapnle (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011010)); D_long(a0exval); } return OK;}
-int m_ftrapgl  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010110)); D_long(a0exval); } return OK;}
-int m_ftrapngl (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011001)); D_long(a0exval); } return OK;}
-int m_ftrapgle (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010111)); D_long(a0exval); } return OK;}
-int m_ftrapngle(WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011000)); D_long(a0exval); } return OK;}
-int m_ftrapogt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000010)); D_long(a0exval); } return OK;}
-int m_ftrapule (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001101)); D_long(a0exval); } return OK;}
-int m_ftrapoge (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000011)); D_long(a0exval); } return OK;}
-int m_ftrapult (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001100)); D_long(a0exval); } return OK;}
-int m_ftrapolt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000100)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000100)); D_long(a0exval); } return OK;}
-int m_ftrapuge (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001011)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001011)); D_long(a0exval); } return OK;}
-int m_ftrapole (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000101)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000101)); D_long(a0exval); } return OK;}
-int m_ftrapugt (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001010)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001010)); D_long(a0exval); } return OK;}
-int m_ftrapogl (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000110)); D_long(a0exval); } return OK;}
-int m_ftrapueq (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001001)); D_long(a0exval); } return OK;}
-int m_ftrapor  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000111)); D_long(a0exval); } return OK;}
-int m_ftrapun  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001000)); D_long(a0exval); } return OK;}
-int m_ftrapf   (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00000000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00000000)); D_long(a0exval); } return OK;}
-int m_ftrapt   (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00001111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00001111)); D_long(a0exval); } return OK;}
-int m_ftrapsf  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010000)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010000)); D_long(a0exval); } return OK;}
-int m_ftrapst  (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011111)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011111)); D_long(a0exval); } return OK;}
-int m_ftrapseq (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00010001)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00010001)); D_long(a0exval); } return OK;}
-int m_ftrapsne (WORD inst, WORD siz) { if (siz==SIZW) { D_word(inst); D_word(B8(00011110)); D_word(a0exval); } else { inst|=3; D_word(inst); D_word(B8(00011110)); D_long(a0exval); } return OK;}
-
-int m_ftrapeqn  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000001)); return OK;}
-int m_ftrapnen  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001110)); return OK;}
-int m_ftrapgtn  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010010)); return OK;}
-int m_ftrapngtn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011101)); return OK;}
-int m_ftrapgen  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010011)); return OK;}
-int m_ftrapngen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011100)); return OK;}
-int m_ftrapltn  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010100)); return OK;}
-int m_ftrapnltn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011011)); return OK;}
-int m_ftraplen  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010101)); return OK;}
-int m_ftrapnlen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011010)); return OK;}
-int m_ftrapgln  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010110)); return OK;}
-int m_ftrapngln (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011001)); return OK;}
-int m_ftrapglen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010111)); return OK;}
-int m_ftrapnglen(WORD inst, WORD siz) { D_word(inst); D_word(B8(00011000)); return OK;}
-int m_ftrapogtn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000010)); return OK;}
-int m_ftrapulen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001101)); return OK;}
-int m_ftrapogen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000011)); return OK;}
-int m_ftrapultn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001100)); return OK;}
-int m_ftrapoltn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000100)); return OK;}
-int m_ftrapugen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001011)); return OK;}
-int m_ftrapolen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000101)); return OK;}
-int m_ftrapugtn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001010)); return OK;}
-int m_ftrapogln (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000110)); return OK;}
-int m_ftrapueqn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001001)); return OK;}
-int m_ftraporn  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000111)); return OK;}
-int m_ftrapunn  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001000)); return OK;}
-int m_ftrapfn   (WORD inst, WORD siz) { D_word(inst); D_word(B8(00000000)); return OK;}
-int m_ftraptn   (WORD inst, WORD siz) { D_word(inst); D_word(B8(00001111)); return OK;}
-int m_ftrapsfn  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010000)); return OK;}
-int m_ftrapstn  (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011111)); return OK;}
-int m_ftrapseqn (WORD inst, WORD siz) { D_word(inst); D_word(B8(00010001)); return OK;}
-int m_ftrapsnen (WORD inst, WORD siz) { D_word(inst); D_word(B8(00011110)); return OK;}
+int m_ftrapcc(WORD inst, WORD siz)
+{
+	// We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7),
+	// so we need to extract them first and fill in the clobbered bits.
+	WORD opcode = (inst >> 3) & 0x1F;
+	inst = (inst & 0xFF07) | (0xF << 3);
+
+	if (siz == SIZW)
+	{
+		inst |= 2;
+		D_word(inst);
+		D_word(opcode);
+		D_word(a0exval);
+	}
+	else if (siz == SIZL)
+	{
+		inst |= 3;
+		D_word(inst);
+		D_word(opcode);
+		D_long(a0exval);
+	}
+	else if (siz = SIZN)
+	{
+		inst |= 4;
+		D_word(inst);
+		D_word(opcode);
+		return OK;
+	}
+
+	return OK;
+}
 
 
 //
@@ -3545,13 +3665,20 @@ int m_fsin(WORD inst, WORD siz)
 //
 int m_fsincos(WORD inst, WORD siz)
 {
+	// Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu
+	// generates
+	int temp;
+	temp = a2reg;
+	a2reg = a1reg;
+	a1reg = temp;
+
 	if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK)
 	{
 		chptr[-1] |= a2reg;
 		return OK;
 	}
-	else
-		return ERROR;
+
+	return ERROR;
 }
 
 
@@ -3586,8 +3713,8 @@ int m_fdfsqrt(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01000101), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -3604,8 +3731,8 @@ int m_fsfsub(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01101000), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }
 
 
@@ -3613,8 +3740,8 @@ int m_fdsub(WORD inst, WORD siz)
 {
 	if (activefpu == FPU_68040)
 		return gen_fpu(inst, siz, B8(01101100), FPU_P_EMUL);
-	else
-		return error("Unsupported in current FPU");
+
+	return error("Unsupported in current FPU");
 }