X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?p=rmac;a=blobdiff_plain;f=mach.c;h=22a27273d4d2d73a1a43617f836dabb6bc3086cc;hp=12abcc218ddcae1fe32d046989e6aadcdc349fd5;hb=1b98a8c971056b75728445e4ef7f2308e68d7495;hpb=03dd34951a331e0b8971195ccef1600fffaea2e6

diff --git a/mach.c b/mach.c
index 12abcc2..22a2727 100644
--- a/mach.c
+++ b/mach.c
@@ -13,7 +13,6 @@
 #include "error.h"
 #include "procln.h"
 #include "riscasm.h"
-//#include "rmac.h"
 #include "sect.h"
 #include "token.h"
 
@@ -469,7 +468,7 @@ int m_ea(WORD inst, WORD siz)
 //
 int m_lea(WORD inst, WORD siz)
 {
-	if (optim_flags[OPT_LEA_ADDQ]
+	if (CHECK_OPTS(OPT_LEA_ADDQ)
 		&& ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED))
 		&& ((a0exval > 0) && (a0exval <= 8)))
 	{
@@ -820,7 +819,7 @@ int m_move(WORD inst, WORD size)
 	int siz = (int)size;
 
 	// Try to optimize to MOVEQ
-	if (optim_flags[OPT_MOVEL_MOVEQ]
+	if (CHECK_OPTS(OPT_MOVEL_MOVEQ)
 		&& (siz == SIZL) && (am0 == IMMED) && (am1 == DREG)
 		&& ((a0exattr & (TDB | DEFINED)) == DEFINED)
 		&& (a0exval + 0x80 < 0x100))
@@ -981,7 +980,7 @@ int m_br(WORD inst, WORD siz)
 		// Optimize branch instr. size
 		if (siz == SIZN)
 		{
-			if (optim_flags[OPT_BSR_BCC_S] && (v != 0) && ((v + 0x80) < 0x100))
+			if (CHECK_OPTS(OPT_BSR_BCC_S) && (v != 0) && ((v + 0x80) < 0x100))
 			{
 				// Fits in .B
 				inst |= v & 0xFF;
@@ -1391,7 +1390,7 @@ int m_cas(WORD inst, WORD siz)
 	// Reject invalud ea modes
 	amsk = amsktab[am0];
 
-	if (amsk & (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE) == 0)
+	if ((amsk & (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE)) == 0)
 		return error("unsupported addressing mode");
 
 	inst |= am0 | a0reg;
@@ -1409,7 +1408,6 @@ int m_cas(WORD inst, WORD siz)
 int m_cas2(WORD inst, WORD siz)
 {
 	WORD inst2, inst3;
-	LONG amsk;
 
 	if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
 		return error(unsupport);
@@ -1614,7 +1612,6 @@ int m_cpbr(WORD inst, WORD siz)
 			{
 				inst |= (1 << 6);
 				D_word(inst);
-				WARNING(check what s "optional coprocessor-defined extension words!")
 				D_long(v);
 				return OK;
 			}
@@ -1625,7 +1622,6 @@ int m_cpbr(WORD inst, WORD siz)
 				return error(range_error);
 
 			D_word(inst);
-			WARNING(check what s "optional coprocessor-defined extension words!")
 			D_word(v);
 		}
 
@@ -1753,6 +1749,11 @@ int m_muls(WORD inst, WORD siz)
 		inst |= am1 | a1reg;			// Get ea1 into instr
 		D_word(inst);					// Deposit instr
 
+										// Extension word
+		inst = a1reg + (a2reg << 12) + (1 << 11);
+		inst |= mulmode;  // add size bit
+		D_word(inst);
+
 		// Generate ea0 if requested
 		if (flg & 2)
 			ea0gen(siz);
@@ -1764,6 +1765,11 @@ int m_muls(WORD inst, WORD siz)
 		// Use am0
 		inst |= am0 | a0reg;			// Get ea0 into instr
 		D_word(inst);					// Deposit instr
+										// Extension word
+		inst = a1reg + (a2reg << 12) + (1 << 11);
+		inst |= mulmode;  // add size bit
+		D_word(inst);
+
 		ea0gen(siz);					// Generate ea0
 
 		// Generate ea1 if requested
@@ -1771,9 +1777,8 @@ int m_muls(WORD inst, WORD siz)
 			ea1gen(siz);
 	}
 
-	inst = a1reg + (a2reg << 12) + (1 << 11);
-	inst |= mulmode;  // add size bit
-	D_word(inst);
+	//D_word(inst);
+	//ea0gen(siz);
 
 	return OK;
 }
@@ -2419,6 +2424,7 @@ int m_pflushr(WORD inst, WORD siz)
 	}
 
 	D_word(B16(10100000, 00000000));
+	return OK;
 }
 
 
@@ -2934,6 +2940,7 @@ int m_fmove(WORD inst, WORD siz)
 	// EA to register
 	if ((am0 == FREG) && (am1 < AM_USP))
 	{
+		//fpx->ea
 		// EA
 		inst |= am1 | a1reg;
 		D_word(inst);
@@ -2982,6 +2989,8 @@ int m_fmove(WORD inst, WORD siz)
 	}
 	else if ((am0 < AM_USP) && (am1 == FREG))
 	{
+		//ea->fpx
+
 		// EA
 		inst |= am0 | a0reg;
 		D_word(inst);
@@ -3016,6 +3025,9 @@ int m_fmove(WORD inst, WORD siz)
 	}
 	else if ((am0 == FREG) && (am1 == FREG))
 	{
+		// register-to-register
+		// Essentially ea to register with R/0=0
+
 		// EA
 		D_word(inst);
 
@@ -3128,11 +3140,11 @@ int m_fmovem(WORD inst, WORD siz)
 	WORD regmask;
 	WORD datareg;
 
-	if (siz == SIZX)
+	if (siz == SIZX || siz==SIZN)
 	{
 		if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
 		{
-			// fmovem.x <rlist>,ea
+			//fmovem.x <rlist>,ea
 			if (fpu_reglist_left(&regmask) < 0)
 				return OK;
 
@@ -3210,7 +3222,7 @@ int m_fmovem(WORD inst, WORD siz)
 			}
 		}
 	}
-	else if ((siz == SIZL) || (siz==SIZN))
+	else if (siz == SIZL)
 	{
 		if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR))
 		{