// RISCA.C - GPU/DSP Assembler
// Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
-// Source Utilised with the Kind Permission of Landon Dyer
+// Source utilised with the kind permission of Landon Dyer
//
#include "riscasm.h"
#include "mark.h"
#include "amode.h"
-#define DEF_MR // Declar keyword values
-#include "risckw.h" // Incl generated risc keywords
+#define DEF_MR // Declare keyword values
+#include "risckw.h" // Incl. generated risc keywords
#define DEF_KW // Declare keyword values
-#include "kwtab.h" // Incl generated keyword tables & defs
+#include "kwtab.h" // Incl. generated keyword tables & defs
unsigned altbankok = 0; // Ok to use alternate register bank
unsigned orgwarning = 0; // Has an ORG warning been issued
int lastOpcode = -1; // Last RISC opcode assembled
-char reg_err[] = "missing register R0...R31";
+const char reg_err[] = "missing register R0...R31";
// Jaguar Jump Condition Names
-char condname[MAXINTERNCC][5] = {
+const char condname[MAXINTERNCC][5] = {
"NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
"N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
"PL", "MI", "F"
};
// Jaguar Jump Condition Numbers
-char condnumber[] = {
+const char condnumber[] = {
1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
};
-struct opcoderecord roptbl[] = {
+const struct opcoderecord roptbl[] = {
{ MR_ADD, RI_TWO, 0 },
{ MR_ADDC, RI_TWO, 1 },
{ MR_ADDQ, RI_NUM_32, 2 },
//
-// Convert a String to Uppercase
+// Convert a string to uppercase
//
void strtoupper(char * s)
{
{
char buf[16];
sprintf(buf, "%02X", signal);
- errors("Malformed opcode [internal $%s]", buf);
- return ERROR;
+ return errors("Malformed opcode [internal $%s]", buf);
}
//
-// Build RISC Instruction Word
+// Build RISC instruction word
//
void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
{
// Check for absolute address setting
if (!orgwarning && !orgactive)
{
- warn("GPU/DSP code outside of absolute section");
+// warn("GPU/DSP code outside of absolute section");
+ warn("RISC code generated with no origin defined");
orgwarning = 1;
}
//
-// Get a RISC Register
+// Get a RISC register
//
int GetRegister(WORD rattr)
{
if (!(eattr & DEFINED))
{
- fixup((WORD)(FU_WORD | rattr), sloc, r_expr);
+ AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr);
return 0;
}
return eval;
// Otherwise, it's out of range & we flag an error
- error(reg_err);
- return ERROR;
+ return error(reg_err);
}
//
-// Do RISC Code Generation
+// Do RISC code generation
//
int GenerateRISCCode(int state)
{
// specific to only one of the RISC processors and ensure it is legal in
// the current code section. If not then show error and return.
if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
- {
- error("Opcode is not valid in this code section");
- return ERROR;
- }
+ return error("Opcode is not valid in this code section");
// Process RISC opcode
switch (type)
if (!(eattr & DEFINED))
{
- fixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
+ AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
reg1 = 0;
}
else
{
if ((int)eval < reg1 || (int)eval > reg2)
- {
- error("constant out of range");
- return ERROR;
- }
+ return error("constant out of range");
if (parm & SUB32)
reg1 = 32 - eval;
if (!(eattr & DEFINED))
{
- fixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
+ AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
eval = 0;
}
else
chcheck(4L);
if (!(eattr & DEFINED))
- {
- error("constant expected after '+'");
- return ERROR;
- }
+ return error("constant expected after '+'");
reg1 = eval;
else
{
if (reg1 < 1 || reg1 > 32)
- {
- error("constant in LOAD out of range");
- return ERROR;
- }
+ return error("constant in LOAD out of range");
if (reg1 == 32)
reg1 = 0;
if (*tok == SYMBOL)
{
-// sy = lookup((char *)tok[1], LABEL, 0);
sy = lookup(string[tok[1]], LABEL, 0);
if (!sy)
if (*tok == SYMBOL)
{
-// sy = lookup((char *)tok[1], LABEL, 0);
sy = lookup(string[tok[1]], LABEL, 0);
if (!sy)
if (!(eattr & DEFINED))
{
- fixup(FU_WORD | FU_REGTWO, sloc, r_expr);
+ AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
reg2 = 0;
}
else
else
{
if (reg2 < 1 || reg2 > 32)
- {
- error("constant in STORE out of range");
- return ERROR;
- }
+ return error("constant in STORE out of range");
if (reg2 == 32)
reg2 = 0;
val = ccsym->svalue;
}
else
- {
- error("unknown condition code");
- return ERROR;
- }
+ return error("unknown condition code");
}
tok += 2;
}
if (val < 0 || val > 31)
- {
- error("condition constant out of range");
- return ERROR;
- }
+ return error("condition constant out of range");
// Store condition code
reg1 = val;
if (!(eattr & DEFINED))
{
- fixup(FU_WORD | FU_JR, sloc, r_expr);
+ AddFixup(FU_WORD | FU_JR, sloc, r_expr);
reg2 = 0;
}
else
// Should never get here :-D
default:
- error("Unknown risc opcode type");
- return ERROR;
+ return error("Unknown RISC opcode type");
}
lastOpcode = type;
projects / rmac / blobdiff