Fix for bug #34 (equated reg in 1st operand of MOVEI).

[rmac] / riscasm.c

diff --git a/riscasm.c b/riscasm.c
index d2d594b31c5a0d0ae59c94dff306321e98db271b..23faaee7120df76cc71cc95dadce3de262f4cf1c 100644 (file)
--- a/riscasm.c
+++ b/riscasm.c
@@ -101,8 +101,8 @@ const struct opcoderecord roptbl[] = {
        { MR_NORMI,   RI_TWO,    56 },
        { MR_NOP,     RI_NONE,   57 },
        { MR_SAT24,   RI_ONE,    62 },
-       { MR_UNPACK,  RI_ONE,    63 + GPUONLY },
-       { MR_PACK,    RI_ONE,    63 + GPUONLY },
+       { MR_UNPACK,  RI_ONE,    63 + GPUONLY | (0 << 6) },
+       { MR_PACK,    RI_ONE,    63 + GPUONLY | (1 << 6) },
        { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
        { MR_MOVE,    RI_MOVE,   0 },
        { MR_LOAD,    RI_LOAD,   0 },
@@ -140,13 +140,13 @@ void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
        // Check for absolute address setting
        if (!orgwarning && !orgactive)
        {
-//             warn("GPU/DSP code outside of absolute section");
                warn("RISC code generated with no origin defined");
                orgwarning = 1;
        }
 
        int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
        D_word(value);
+//printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
 }
 
 
@@ -323,6 +323,15 @@ int GenerateRISCCode(int state)
                tok++;
                riscImmTokenSeen = 1;
 
+               // Check for equated register after # and return error if so
+               if (*tok == SYMBOL)
+               {
+                       sy = lookup(string[tok[1]], LABEL, 0);
+
+                       if (sy->sattre & EQUATEDREG)
+                               return error("equated register in 1st operand of MOVEI instruction");
+               }
+
                if (expr(r_expr, &eval, &eattr, &esym) != OK)
                        return MalformedOpcode(0x04);