//
// RMAC - Reboot's Macro Assembler for all Atari computers
// MACH.C - Code Generation
-// Copyright (C) 199x Landon Dyer, 2011-2018 Reboot and Friends
+// Copyright (C) 199x Landon Dyer, 2011-2020 Reboot and Friends
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
// Source utilised with the kind permission of Landon Dyer
//
int m_pload(WORD inst, WORD siz, WORD extension);
int m_pmove(WORD inst, WORD siz);
int m_pmovefd(WORD inst, WORD siz);
-int m_ptest(WORD inst, WORD siz);
+int m_ptest(WORD inst, WORD siz, WORD extension);
+int m_ptestr(WORD inste, WORD siz);
+int m_ptestw(WORD inste, WORD siz);
int m_ptrapcc(WORD inst, WORD siz);
int m_ploadr(WORD inst, WORD siz);
int m_ploadw(WORD inst, WORD siz);
{
inst = B16(01010000, 01001000) | (((uint16_t)a0exval & 7) << 9) | (a0reg);
D_word(inst);
- warn("lea size(An),An converted to addq #size,An");
+
+ if (optim_warn_flag)
+ warn("lea size(An),An converted to addq #size,An");
+
return OK;
}
//
int m_adda(WORD inst, WORD siz)
{
- if (a0exattr & DEFINED)
+ if ((a0exattr & DEFINED) && (am0 == IMMED))
{
- if (CHECK_OPTS(OPT_ADDA_ADDQ))
- if (a0exval > 1 && a0exval <= 8)
+ if (CHECK_OPTS(OPT_ADDA_ADDQ))
+ {
+ if ((a0exval > 1) && (a0exval <= 8))
+ {
// Immediate is between 1 and 8 so let's convert to addq
return m_addq(B16(01010000, 00000000), siz);
- if (CHECK_OPTS(OPT_ADDA_LEA))
- if (a0exval > 8)
- {
- // Immediate is larger than 8 so let's convert to lea
- am0 = ADISP; // Change addressing mode
- a0reg = a1reg; // In ADISP a0reg is used instead of a1reg!
- return m_lea(B16(01000001, 11011000), SIZW);
+
+ if (optim_warn_flag)
+ warn("adda/suba size(An),An converted to addq/subq #size,An");
+ }
+ }
+
+ if (CHECK_OPTS(OPT_ADDA_LEA))
+ {
+ if ((a0exval > 8) && ((a0exval + 0x8000) < 0x10000))
+ {
+ // Immediate is larger than 8 and word size so let's convert to lea
+ am0 = ADISP; // Change addressing mode
+ a0reg = a1reg; // In ADISP a0reg is used instead of a1reg!
+
+ if (!(inst & (1 << 14)))
+ {
+ // We have a suba #x,AREG so let's negate the value
+ a0exval = -a0exval;
+ }
+
+ // We're going to rely on +o4 for this, so let's ensure that
+ // it's on, even just for this instruction
+ int return_value;
+ int temp_flag = optim_flags[OPT_LEA_ADDQ];
+ optim_flags[OPT_LEA_ADDQ] = 1; // Temporarily save switch state
+ return_value = m_lea(B16(01000001, 11011000), SIZW);
+ optim_flags[OPT_LEA_ADDQ] = temp_flag; // Restore switch state
+ return return_value;
+ }
}
}
{
m_moveq((WORD)0x7000, (WORD)0);
- if (sbra_flag)
+ if (optim_warn_flag)
warn("move.l #size,dx converted to moveq");
}
else
int m_move30(WORD inst, WORD size)
{
int siz = (int)size;
- inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
+
+ if (am0 > ABASE)
+ inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
+ else
+ inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am1 - ABASE] << 3;
D_word(inst);
inst |= v & 0xFF;
D_word(inst);
- if (sbra_flag)
+ if (optim_warn_flag)
warn("Bcc.w/BSR.w converted to .s");
return OK;
{
// .B
AddFixup(FU_BBRA | FU_PCREL | FU_SEXT, sloc, a0expr);
- D_word(inst);
+ // So here we have a small issue: this bra.s could be zero offset, but
+ // we can never know. Because unless we know beforehand that the
+ // offset will be zero (i.e. "bra.s +0"), it's going to be a label
+ // below this instruction! We do have an optimisation flag that can
+ // check against this during fixups, but we cannot rely on the state
+ // of the flag after all the file(s) have been processed because its
+ // state might have changed multiple times during file parsing. (Yes,
+ // there's a very low chance that this will ever happen but it's not
+ // zero!). So, we can use the byte that is going to be filled during
+ // fixups to store the state of the optimisation flag and read it
+ // during that stage so each bra.s will have its state stored neatly.
+ // Sleazy? Eh, who cares, like this will ever happen ;)
+ // One final note: we'd better be damn sure that the flag's value is
+ // less than 256 or magical stuff will happen!
+ D_word(inst | optim_flags[OPT_NULL_BRA]);
return OK;
}
else
if ((a0exattr & DEFINED) == 0)
return error("constant value must be defined");
+ if (a0exval>7)
+ return error("constant value must be between 0 and 7");
+
inst = (2 << 3) | (uint16_t)a0exval;
break;
}
//
-// ptestr, ptestw (68030)
+// ptestr, ptestw (68030, 68040)
+// TODO See comment on m_pmove about 68851 support
+// TODO quite a good chunk of the 030 code is copied from m_pload, perhaps merge these somehow?
//
-int m_ptest(WORD inst, WORD siz)
+int m_ptest(WORD inst, WORD siz, WORD extension)
{
- CHECKNO30;
+ uint64_t eval;
+
+ if (activecpu != CPU_68030 && activecpu != CPU_68040)
+ return error(unsupport);
if (activecpu == CPU_68030)
- return error("Not implemented yet.");
- else if (activecpu == CPU_68040)
+ {
+ inst |= am1;
+ D_word(inst);
+
+ switch (am0)
+ {
+ case CREG:
+ if (a0reg == KW_SFC - KW_SFC)
+ extension |= 0;
+ else if (a0reg == KW_DFC - KW_SFC)
+ extension |= 1;
+ else
+ return error("illegal control register specified");
+ break;
+ case DREG:
+ extension |= (1 << 3) | a0reg;
+ break;
+ case IMMED:
+ if ((a0exattr & DEFINED) == 0)
+ return error("constant value must be defined");
+
+ if (a0exval > 7)
+ return error("constant value must be between 0 and 7");
+
+ extension |= (2 << 3) | (uint16_t)a0exval;
+ break;
+ }
+
+ // Operand 3 must be an immediate
+ CHECK_COMMA
+
+ if (*tok++ != '#')
+ return error("ptest level must be immediate");
+
+ // Let's be a bit inflexible here and demand that this
+ // is fully defined at this stage. Otherwise we'd have
+ // to arrange for a bitfield fixup, which would mean
+ // polluting the bitfields and codebase with special
+ // cases that might most likely never be used.
+ // So if anyone gets bit by this: sorry for being a butt!
+ if (abs_expr(&eval) != OK)
+ return OK; // We're returning OK because error() has already been called and error count has been increased
+
+ if (eval > 7)
+ return error("ptest level must be between 0 and 7");
+
+ extension |= eval << 10;
+
+ // Operand 4 is optional and must be an address register
+
+ if (*tok != EOL)
+ {
+ CHECK_COMMA
+
+ if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ {
+ extension |= (1 << 8) | ((*tok++ & 7) << 4);
+ }
+ else
+ {
+ return error("fourth parameter must be an address register");
+ }
+ }
+
+ ErrorIfNotAtEOL();
+
+ D_word(extension);
+ return OK;
+ }
+ else
return error("Not implemented yet.");
return ERROR;
}
+int m_ptestr(WORD inst, WORD siz)
+{
+ return m_ptest(inst, siz, (1 << 15) | (0 << 9));
+}
+
+int m_ptestw(WORD inst, WORD siz)
+{
+ return m_ptest(inst, siz, (1 << 15) | (1 << 9));
+}
+
//////////////////////////////////////////////////////////////////////////////
//
// 68020/30/40/60 instructions
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return error("Not implemented yet.");
-
-#if 0
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
-#endif
+ return gen_fpu(inst, siz, B8(01100100), FPU_FPSP);
}
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return error("Not implemented yet.");
-
-#if 0
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
-#endif
+ return gen_fpu(inst, siz, B8(01100100), FPU_FPSP);
}
projects / rmac / blobdiff