//
// RMAC - Reboot's Macro Assembler for all Atari computers
// MACH.C - Code Generation
-// Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
+// Copyright (C) 199x Landon Dyer, 2011-2020 Reboot and Friends
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
// Source utilised with the kind permission of Landon Dyer
//
int movep = 0; // Global flag to indicate we're generating a movep instruction
// Function prototypes
-int m_unimp(WORD, WORD), m_badmode(WORD, WORD), m_bad6mode(WORD, WORD), m_bad6inst(WORD, WORD);
+int m_unimp(WORD, WORD), m_badmode(WORD, WORD);
int m_self(WORD, WORD);
int m_abcd(WORD, WORD);
int m_reg(WORD, WORD);
int m_chk2(WORD inst, WORD siz);
int m_cmp2(WORD inst, WORD siz);
int m_bkpt(WORD inst, WORD siz);
-int m_cpbr(WORD inst, WORD siz);
+int m_cpbcc(WORD inst, WORD siz);
int m_cpdbr(WORD inst, WORD siz);
int m_muls(WORD inst, WORD siz);
int m_move16a(WORD inst, WORD siz);
int m_cprest(WORD inst, WORD siz);
int m_movec(WORD inst, WORD siz);
int m_moves(WORD inst, WORD siz);
+int m_lpstop(WORD inst, WORD siz);
+int m_plpa(WORD inst, WORD siz);
// PMMU
int m_pbcc(WORD inst, WORD siz);
int m_pflusha(WORD inst, WORD siz);
int m_pflush(WORD inst, WORD siz);
int m_pflushr(WORD inst, WORD siz);
+int m_pflushan(WORD inst, WORD siz);
int m_pload(WORD inst, WORD siz, WORD extension);
int m_pmove(WORD inst, WORD siz);
int m_pmovefd(WORD inst, WORD siz);
int m_ploadr(WORD inst, WORD siz);
int m_ploadw(WORD inst, WORD siz);
-//FPU
+// FPU
int m_fabs(WORD inst, WORD siz);
+int m_fbcc(WORD inst, WORD siz);
int m_facos(WORD inst, WORD siz);
int m_fadd(WORD inst, WORD siz);
int m_fasin(WORD inst, WORD siz);
int m_fneg(WORD inst, WORD siz);
int m_fnop(WORD inst, WORD siz);
int m_frem(WORD inst, WORD siz);
+int m_frestore(WORD inst, WORD siz);
int m_fsabs(WORD inst, WORD siz);
int m_fsadd(WORD inst, WORD siz);
int m_fscc(WORD inst, WORD siz);
// a corner case, so kludge it
a0reg = a0reg + 8;
else if (am0 == PCDISP)
- //Another corner case (possibly!), so kludge ahoy
+ // Another corner case (possibly!), so kludge ahoy
inst |= am0; // Get ea0 into instr
+ else if (am0 == IMMED && am1 == MEMPOST)
+ {
+ // Added for addi/andi/cmpi/eori/ori/subi #xx,(bd,An,Dm)
+ inst |= a1reg | AINDEXED;
+ }
else if (am0 == IMMED)
inst |= am0 | a0reg; // Get ea0 into instr
else if (am0 == AM_CCR)
if ((a1exattr & TDB) != cursect)
return error(rel_error);
- uint32_t v = a1exval - sloc;
+ uint32_t v = (uint32_t)a1exval - sloc;
if (v + 0x8000 > 0x10000)
return error(range_error);
WORD extra_addressing[16]=
{
- 0, // 0100 (bd,An,Xn)
- 0, // 0101 ([bd,An],Xn,od)
- 0x180, // 0102 ([bc,An,Xn],od) (111 110 110 111)
- 0, // 0103 (bd,PC,Xn)
- 0, // 0104 ([bd,PC],Xn,od)
- 0, // 0105 ([bc,PC,Xn],od)
+ 0x30, // 0100 (bd,An,Xn)
+ 0x30, // 0101 ([bd,An],Xn,od)
+ 0x30, // 0102 ([bc,An,Xn],od)
+ 0x30, // 0103 (bd,PC,Xn)
+ 0x30, // 0104 ([bd,PC],Xn,od)
+ 0x30, // 0105 ([bc,PC,Xn],od)
0, // 0106
0, // 0107
0, // 0110
//
// Handle MOVE <C_ALL030> <C_ALTDATA>
-// MOVE <C_ALL030> <M_AREG>
+// MOVE <C_ALL030> <M_AREG>
//
int m_move30(WORD inst, WORD size)
{
int siz = (int)size;
- // TODO: is extra_addressing necessary/correct?
- //inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
- inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg;
+ inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
D_word(inst);
rmask = 0;
for(i=0x8000; i; i>>=1, w>>=1)
- rmask = (WORD)((rmask << 1) | w & 1);
+ rmask = (WORD)((rmask << 1) | (w & 1));
}
}
else
else
bfparam1 = bfval1 << 12;
- D_word((inst | am0 | a0reg | am1 | a1reg));
+ //D_word((inst | am0 | a0reg | am1 | a1reg));
+ if (inst == B16(11101111, 11000000))
+ {
+ // bfins special case
+ D_word((inst | am1 | a1reg));
+ }
+ else
+ {
+ D_word((inst | am0 | a0reg));
+ }
+
ea0gen(siz); // Generate EA
// Second instruction word - Dest register (if exists), Do, Offset, Dw, Width
- inst = bfparam1 | bfparam2;
+ if (inst == B16(11101111, 11000000))
+ {
+ // bfins special case
+ inst = bfparam1 | bfparam2;
- if (am1 == DREG)
- inst |= a1reg << 0;
+ if (am1 == DREG)
+ inst |= a0reg << 12;
- if (am0 == DREG)
- inst |= a0reg << 12;
+ D_word(inst);
+ }
+ else
+ {
+ inst = bfparam1 | bfparam2;
- D_word(inst);
+ if (am1 == DREG)
+ inst |= a0reg << 0;
+
+ if (am0 == DREG)
+ inst |= a1reg << 12;
+
+ D_word(inst);
+ }
return OK;
}
//
-// cpbcc(68020, 68030)
+// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc)), pbcc (68851)
//
-int m_cpbr(WORD inst, WORD siz)
+int m_fpbr(WORD inst, WORD siz)
{
- if ((activecpu & (CPU_68020 | CPU_68030)) == 0)
- return error(unsupport);
if (a0exattr & DEFINED)
{
return OK;
}
}
- else // SIZW/SIZN
+ else // SIZW/SIZN
{
if ((v + 0x8000) >= 0x10000)
return error(range_error);
}
+//
+// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc))
+//
+int m_cpbcc(WORD inst, WORD siz)
+{
+ if (!(activecpu & (CPU_68020 | CPU_68030)))
+ return error(unsupport);
+
+ return m_fpbr(inst, siz);
+}
+
+
+//
+// fbcc(6808X, 68040, 68060)
+//
+int m_fbcc(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return m_fpbr(inst, siz);
+}
+
+
+//
+// pbcc(68851 but let's assume 68020 only)
+//
+int m_pbcc(WORD inst, WORD siz)
+{
+ CHECKNO20;
+ return m_fpbr(inst, siz);
+}
+
+
//
// cpdbcc(68020, 68030)
//
}
return OK;
+
}
if (flg & 16)
{
- // OR-in register number
+ // OR-in register number
if (flg & 8)
inst |= reg_9[a1reg]; // ea1reg in bits 9..11
else
D_word(inst);
- // Generate ea0 if requested
+ // Generate ea0 if requested
if (flg & 2)
ea0gen(siz);
return error("Wasn't this suppose to call m_move16a???");
else
{
- //move16 (ax)+,(xxx).L
+ // move16 (ax)+,(xxx).L
inst |= 0 << 3;
v = (int)a1exval;
}
{
if (am1 == AIND)
{
- //move16 (xxx).L,(ax)+
+ // move16 (xxx).L,(ax)+
inst |= 1 << 3;
v = (int)a0exval;
}
- else //APOSTINC
+ else // APOSTINC
{
- //move16 (xxx).L,(ax)
+ // move16 (xxx).L,(ax)
inst |= 3 << 3;
v = (int)a0exval;
}
}
else if (am0 == AIND)
{
- //move16 (ax),(xxx).L
+ // move16 (ax),(xxx).L
inst |= 2 << 3;
v = (int)a1exval;
}
//
-// cinvl/p/a (68040)
+// cinvl/p/a (68040/68060)
//
int m_cinv(WORD inst, WORD siz)
{
}
+int m_fpusavrest(WORD inst, WORD siz)
+{
+ inst |= am0 | a0reg;
+ D_word(inst);
+ ea0gen(siz);
+
+ return OK;
+}
+
+
//
-// cpRESTORE (68020, 68030)
+// cpSAVE/cpRESTORE (68020, 68030)
//
int m_cprest(WORD inst, WORD siz)
{
if (activecpu & !(CPU_68020 | CPU_68030))
return error(unsupport);
- inst |= am0 | a0reg;
- D_word(inst);
- ea0gen(siz);
+ return m_fpusavrest(inst, siz);
- return OK;
}
//
-// movec (68010, 68020, 68030, 68040, CPU32)
+// FSAVE/FRESTORE (68040, 68060)
+//
+int m_frestore(WORD inst, WORD siz)
+{
+ if ((!(activecpu & (CPU_68040 | CPU_68060))) ||
+ (activefpu&(FPU_68881 | FPU_68882)))
+ return error(unsupport);
+
+ return m_fpusavrest(inst, siz);
+}
+
+
+//
+// movec (68010, 68020, 68030, 68040, 68060, CPU32)
//
int m_movec(WORD inst, WORD siz)
{
}
-//
-// PBcc (MC68851)
-//
-int m_pbcc(WORD inst, WORD siz)
-{
- CHECKNO20;
- return error("Not implemented yet.");
-}
-
-
//
// pflusha (68030, 68040)
//
if ((a0exattr & DEFINED) == 0)
return error("function code immediate should be defined");
- if (a0exval > 7 && a0exval < 0)
+ if (a0exval > 7)
return error("function code out of range (0-7)");
fc = (uint16_t)a0exval;
if ((a0exattr & DEFINED) == 0)
return error("mask immediate value should be defined");
- if (a0exval > 7 && a0exval < 0)
+ if (a0exval > 7)
return error("function code out of range (0-7)");
mask = (uint16_t)a0exval << 5;
}
+//
+// pflushan (68040, 68060)
+//
+int m_pflushan(WORD inst, WORD siz)
+{
+ if (activecpu == CPU_68040 || activecpu == CPU_68060)
+ D_word(inst);
+
+ return OK;
+}
+
+
//
// pflushr (68851)
//
// The instruction is a quad-word (8 byte) operation
// for the CPU root pointer and the supervisor root pointer.
- // It is a long - word operation for the translation control register
+ // It is a long-word operation for the translation control register
// and the transparent translation registers(TT0 and TT1).
// It is a word operation for the MMU status register.
}
else if (am1 == CREG)
{
- inst |= am0 | a0reg;
+ inst |= am0 | a0reg;
D_word(inst);
}
//
int m_ptrapcc(WORD inst, WORD siz)
{
- CHECKNO20;
+ CHECKNO20;
// We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4),
// so we need to extract them first and fill in the clobbered bits.
WORD opcode = inst & 0x1F;
return ERROR;
}
+//////////////////////////////////////////////////////////////////////////////
+//
+// 68020/30/40/60 instructions
+// Note: the map of which instructions are allowed on which CPUs came from the
+// 68060 manual, section D-1 (page 392 of the PDF). The current implementation
+// is missing checks for the EC models which have a simplified FPU.
+//
+//////////////////////////////////////////////////////////////////////////////
+
#define FPU_NOWARN 0
-#define FPU_P_EMUL 1
-#define FPU_P2_EMU 2
-#define FPU_FPSP 4
+#define FPU_FPSP 1
//
inst |= (1 << 9); // Bolt on FPU id
inst |= am0;
- if (am0 == DREG)
- inst |= a0reg;
+ //if (am0 == DREG || am0 == AREG)
+ inst |= a0reg;
D_word(inst);
inst = 1 << 14; // R/M field (we have ea so have to set this to 1)
D_word(inst);
}
- if ((emul & FPU_FPSP) && (activefpu == FPU_68040))
- warn("Instruction is emulated in 68040");
+ if ((emul & FPU_FPSP) && (activefpu == (FPU_68040 | FPU_68060)))
+ warn("Instruction is emulated in 68040/060");
return OK;
}
//
-// fabs, fsabs, fdabs (6888X, 68040)
+// fabs (6888X, 68040FPSP, 68060FPSP)
//
int m_fabs(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00011000), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00011000), FPU_NOWARN);
}
+//
+// fsabs (68040, 68060)
+//
int m_fsabs(WORD inst, WORD siz)
{
+ CHECKNO40;
if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011000), FPU_P_EMUL);
+ return gen_fpu(inst, siz, B8(01011000), FPU_NOWARN);
return error("Unsupported in current FPU");
}
+//
+// fdabs (68040, 68060)
+//
int m_fdabs(WORD inst, WORD siz)
{
if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011100), FPU_P_EMUL);
+ return gen_fpu(inst, siz, B8(01011100), FPU_NOWARN);
return error("Unsupported in current FPU");
}
//
-// facos (6888X, 68040FPSP)
+// facos (6888X, 68040FPSP, 68060FPSP)
//
int m_facos(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00011100), FPU_FPSP);
}
//
-// fadd (6888X, 68040FPSP)
+// fadd (6888X, 68040, 68060)
//
int m_fadd(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00100010), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100010), FPU_NOWARN);
}
+//
+// fsadd (68040, 68060)
+//
int m_fsadd(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100010), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100010), FPU_NOWARN);
return error("Unsupported in current FPU");
}
+//
+// fxadd (68040)
+//
int m_fdadd(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100110), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100110), FPU_NOWARN);
return error("Unsupported in current FPU");
}
//
-// fasin (6888X, 68040FPSP)f
+// fasin (6888X, 68040FPSP, 68060FPSP)
//
int m_fasin(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00001100), FPU_FPSP);
}
//
-// fatan (6888X, 68040FPSP)
+// fatan (6888X, 68040FPSP, 68060FPSP)
//
int m_fatan(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00001010), FPU_FPSP);
}
//
-// fatanh (6888X, 68040FPSP)
+// fatanh (6888X, 68040FPSP, 68060FPSP)
//
int m_fatanh(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00001101), FPU_FPSP);
}
//
-// fcmp (6888X, 68040)
+// fcmp (6888X, 68040, 68060)
//
int m_fcmp(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00111000), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00111000), FPU_FPSP);
}
//
-// fcos (6888X, 68040FPSP)
+// fcos (6888X, 68040FPSP, 68060FPSP)
//
int m_fcos(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00011101), FPU_FPSP);
}
//
-// fcosh (6888X, 68040FPSP)
+// fcosh (6888X, 68040FPSP, 68060FPSP)
//
int m_fcosh(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00011001), FPU_FPSP);
}
//
-// fdbcc (6888X, 68040)
+// fdbcc (6888X, 68040, 68060FPSP)
//
int m_fdbcc(WORD inst, WORD siz)
{
+ CHECKNOFPU;
WORD opcode = inst & 0x3F; // Grab conditional bitfield
inst &= ~0x3F;
D_word(0);
}
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
return OK;
}
//
-// fdiv (6888X, 68040)
+// fdiv (6888X, 68040, 68060)
//
int m_fdiv(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00100000), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100000), FPU_NOWARN);
}
+//
+// fsdiv (68040, 68060)
+//
int m_fsdiv(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100000), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100000), FPU_NOWARN);
return error("Unsupported in current FPU");
}
+//
+// fddiv (68040, 68060)
+//
int m_fddiv(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100100), FPU_NOWARN);
return error("Unsupported in current FPU");
}
//
-// fetox (6888X, 68040FPSP)
+// fetox (6888X, 68040FPSP, 68060FPSP)
//
int m_fetox(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00010000), FPU_FPSP);
}
//
-// fetoxm1 (6888X, 68040FPSP)
+// fetoxm1 (6888X, 68040FPSP, 68060FPSP)
//
int m_fetoxm1(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00001000), FPU_FPSP);
}
//
-// fgetexp (6888X, 68040FPSP)
+// fgetexp (6888X, 68040FPSP, 68060FPSP)
//
int m_fgetexp(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00011110), FPU_FPSP);
}
//
-// fgetman (6888X, 68040FPSP)
+// fgetman (6888X, 68040FPSP, 68060FPSP)
//
int m_fgetman(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00011111), FPU_FPSP);
}
//
-// fint (6888X, 68040FPSP)
+// fint (6888X, 68040FPSP, 68060)
//
int m_fint(WORD inst, WORD siz)
{
// special case - fint fpx = fint fpx,fpx
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(00000001), FPU_FPSP);
+ if (activefpu == FPU_68040)
+ warn("Instruction is emulated in 68040");
+
+ return gen_fpu(inst, siz, B8(00000001), FPU_NOWARN);
}
//
-// fintrz (6888X, 68040FPSP)
+// fintrz (6888X, 68040FPSP, 68060)
//
int m_fintrz(WORD inst, WORD siz)
{
// special case - fintrz fpx = fintrz fpx,fpx
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(00000011), FPU_FPSP);
+ if (activefpu == FPU_68040)
+ warn("Instruction is emulated in 68040");
+
+ return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN);
}
//
-// flog10 (6888X, 68040FPSP)
+// flog10 (6888X, 68040FPSP, 68060FPSP)
//
int m_flog10(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00010101), FPU_FPSP);
}
//
-// flog2 (6888X, 68040FPSP)
+// flog2 (6888X, 68040FPSP, 68060FPSP)
//
int m_flog2(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00010110), FPU_FPSP);
}
//
-// flogn (6888X, 68040FPSP)
+// flogn (6888X, 68040FPSP, 68060FPSP)
//
int m_flogn(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00010100), FPU_FPSP);
}
//
-// flognp1 (6888X, 68040FPSP)
+// flognp1 (6888X, 68040FPSP, 68060FPSP)
//
int m_flognp1(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00000110), FPU_FPSP);
}
//
-// fmod (6888X, 68040FPSP)
+// fmod (6888X, 68040FPSP, 68060FPSP)
//
int m_fmod(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00100001), FPU_FPSP);
}
//
-// fmove (6888X, 68040)
+// fmove (6888X, 68040, 68060)
//
int m_fmove(WORD inst, WORD siz)
{
+ CHECKNOFPU;
+
// EA to register
if ((am0 == FREG) && (am1 < AM_USP))
{
- //fpx->ea
+ // fpx->ea
// EA
inst |= am1 | a1reg;
D_word(inst);
inst = 0 << 14;
// Source specifier
- if (siz != SIZX)
+ if (siz != SIZX && siz != SIZN)
return error("Invalid size");
// Source register
inst |= (a0reg << 10);
- // Destination register
+ // Destination register
inst |= (a1reg << 7);
D_word(inst);
//
-// fmove (6888X, 68040)
+// fmove (6888X, 68040, 68060)
//
int m_fmovescr(WORD inst, WORD siz)
{
+ CHECKNOFPU;
+
// Move Floating-Point System Control Register (FPCR)
// ea
// dr
}
//
-// fsmove/fdmove (68040)
+// fsmove/fdmove (68040, 68060)
//
int m_fsmove(WORD inst, WORD siz)
{
+ if (!(activefpu & (FPU_68040 | FPU_68060)))
+ return error("Unsupported in current FPU");
+
return error("Not implemented yet.");
#if 0
int m_fdmove(WORD inst, WORD siz)
{
+ if (!(activefpu & (FPU_68040 | FPU_68060)))
+ return error("Unsupported in current FPU");
+
return error("Not implemented yet.");
#if 0
//
-// fmovecr (6888X, 68040FPSP)
+// fmovecr (6888X, 68040FPSP, 68060FPSP)
//
int m_fmovecr(WORD inst, WORD siz)
{
+ CHECKNOFPU;
+
D_word(inst);
inst = 0x5c00;
inst |= a1reg << 7;
D_word(inst);
if (activefpu == FPU_68040)
- warn("Instruction is emulated in 68040");
+ warn("Instruction is emulated in 68040/060");
return OK;
}
//
-// fmovem (6888X, 68040)
+// fmovem (6888X, 68040, 68060FPSP)
//
int m_fmovem(WORD inst, WORD siz)
{
+ CHECKNOFPU;
+
WORD regmask;
WORD datareg;
{
if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
{
- //fmovem.x <rlist>,ea
+ // fmovem.x <rlist>,ea
if (fpu_reglist_left(®mask) < 0)
return OK;
if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC)))
return error("invalid addressing mode");
+ // Quote from the 060 manual:
+ // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list."
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
D_word(inst);
inst = (1 << 15) | (1 << 14) | (1 << 13) | (1 << 11) | (datareg << 4);
D_word(inst);
if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
{
- //fmovem.x ea,<rlist>
+ // fmovem.x ea,<rlist>
if (fpu_reglist_right(®mask) < 0)
return OK;
{
// fmovem.x ea,Dn
datareg = (*tok++ & 7) << 10;
+
+ // Quote from the 060 manual:
+ // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list."
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
D_word(inst);
inst = (1 << 15) | (1 << 14) | (0 << 13) | (3 << 11) | (datareg << 4);
D_word(inst);
{
if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR))
{
- //fmovem.l <rlist>,ea
+ // fmovem.l <rlist>,ea
regmask = (1 << 15) | (1 << 13);
+ int no_control_regs = 0;
+
fmovem_loop_1:
if (*tok == KW_FPCR)
{
regmask |= (1 << 12);
tok++;
+ no_control_regs++;
goto fmovem_loop_1;
}
{
regmask |= (1 << 11);
tok++;
+ no_control_regs++;
goto fmovem_loop_1;
}
{
regmask |= (1 << 10);
tok++;
+ no_control_regs++;
goto fmovem_loop_1;
}
if (amode(0) < 0)
return OK;
+ // Quote from the 060 manual:
+ // "[..] when the processor attempts to execute an FMOVEM.L instruction with
+ // an immediate addressing mode to more than one floating - point
+ // control register (FPCR, FPSR, FPIAR)[..]"
+ if (activefpu == FPU_68060)
+ if (no_control_regs > 1 && am0 == IMMED)
+ warn("Instruction is emulated in 68060");
+
inst |= am0 | a0reg;
D_word(inst);
D_word(regmask);
}
else
{
- //fmovem.l ea,<rlist>
+ // fmovem.l ea,<rlist>
if (amode(0) < 0)
return OK;
//
-// fmul (6888X, 68040)
+// fmul (6888X, 68040, 68060)
//
int m_fmul(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00100011), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100011), FPU_NOWARN);
}
+//
+// fsmul (68040, 68060)
+//
int m_fsmul(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100011), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
}
+//
+// fdmul (68040)
+//
int m_fdmul(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100111), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100111), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
}
//
-// fneg (6888X, 68040)
+// fneg (6888X, 68040, 68060)
//
int m_fneg(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00011010), FPU_P_EMUL);
+ CHECKNOFPU;
+
+ if (am1 == AM_NONE)
+ {
+ a1reg = a0reg;
+ return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
+ }
+
+ return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
}
+//
+// fsneg (68040, 68060)
+//
int m_fsneg(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011010), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+ if (activefpu & (FPU_68040 | FPU_68060))
+ {
+ if (am1 == AM_NONE)
+ {
+ a1reg = a0reg;
+ return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+ }
+
+ return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+ }
+
+ return error("Unsupported in current FPU");
}
+//
+// fdneg (68040, 68060)
+//
int m_fdneg(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011110), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ {
+ if (am1 == AM_NONE)
+ {
+ a1reg = a0reg;
+ return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ }
+
+ return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ }
return error("Unsupported in current FPU");
}
//
-// fnop (6888X, 68040)
+// fnop (6888X, 68040, 68060)
//
int m_fnop(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00000000), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00000000), FPU_NOWARN);
}
//
-// frem (6888X, 68040FPSP)
+// frem (6888X, 68040FPSP, 68060FPSP)
//
int m_frem(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00100101), FPU_FPSP);
}
//
-// fscale (6888X, 68040FPSP)
+// fscale (6888X, 68040FPSP, 68060FPSP)
//
int m_fscale(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00100110), FPU_FPSP);
}
//
-// FScc (6888X, 68040), cpScc (68851, 68030), PScc (68851)
+// FScc (6888X, 68040, 68060), cpScc (68851, 68030), PScc (68851)
// TODO: Add check for PScc to ensure 68020+68851 active
// TODO: Add check for cpScc to ensure 68020+68851, 68030
//
int m_fscc(WORD inst, WORD siz)
{
+ CHECKNOFPU;
+
// We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0),
// so we need to extract them first and fill in the clobbered bits.
WORD opcode = inst & 0x1F;
D_word(inst);
ea0gen(siz);
D_word(opcode);
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
return OK;
}
//
-// FTRAPcc (6888X, 68040)
-//
-int m_ftrapcc(WORD inst, WORD siz)
-{
- // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7),
- // so we need to extract them first and fill in the clobbered bits.
- WORD opcode = (inst >> 3) & 0x1F;
- inst = (inst & 0xFF07) | (0xF << 3);
-
- if (siz == SIZW)
- {
- inst |= 2;
- D_word(inst);
- D_word(opcode);
- D_word(a0exval);
- }
- else if (siz == SIZL)
- {
- inst |= 3;
- D_word(inst);
- D_word(opcode);
- D_long(a0exval);
- }
- else if (siz = SIZN)
- {
- inst |= 4;
- D_word(inst);
- D_word(opcode);
- return OK;
- }
-
- return OK;
-}
-
-
-//
-// fsgldiv (6888X, 68040)
+// fsgldiv (6888X, 68040FPSP, 68060FPSP)
//
int m_fsgldiv(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00100100), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100100), FPU_FPSP);
}
//
-// fsglmul (6888X, 68040)
+// fsglmul (6888X, 68040, 68060FPSP)
//
int m_fsglmul(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00100111), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100111), FPU_FPSP);
}
//
-// fsin (6888X, 68040FPSP)
+// fsin (6888X, 68040FPSP, 68060FPSP)
//
int m_fsin(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00001110), FPU_FPSP);
}
//
-// fsincos (6888X, 68040FPSP)
+// fsincos (6888X, 68040FPSP, 68060FPSP)
//
int m_fsincos(WORD inst, WORD siz)
{
+ CHECKNOFPU;
+
// Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu
// generates
int temp;
//
-// fsin (6888X, 68040FPSP)
+// fsinh (6888X, 68040FPSP, 68060FPSP)
//
int m_fsinh(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00000010), FPU_FPSP);
}
//
-// fsqrt (6888X, 68040)
+// fsqrt (6888X, 68040, 68060)
//
int m_fsqrt(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00000100), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00000100), FPU_NOWARN);
}
+//
+// fsfsqrt (68040, 68060)
+//
int m_fsfsqrt(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01000001), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
}
+//
+// fdfsqrt (68040, 68060)
+//
int m_fdfsqrt(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01000101), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01000101), FPU_NOWARN);
return error("Unsupported in current FPU");
}
//
-// fsub (6888X, 68040)
+// fsub (6888X, 68040, 68060)
//
int m_fsub(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00101000), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00101000), FPU_NOWARN);
}
+//
+// fsfsub (68040, 68060)
+//
int m_fsfsub(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01101000), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01101000), FPU_NOWARN);
return error("Unsupported in current FPU");
}
+//
+// fdfsub (68040, 68060)
+//
int m_fdsub(WORD inst, WORD siz)
{
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01101100), FPU_P_EMUL);
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01101100), FPU_NOWARN);
return error("Unsupported in current FPU");
}
//
-// ftan (6888X, 68040FPSP)
+// ftan (6888X, 68040FPSP, 68060FPSP)
//
int m_ftan(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00001111), FPU_FPSP);
}
//
-// ftanh (6888X, 68040FPSP)
+// ftanh (6888X, 68040FPSP, 68060FPSP)
//
int m_ftanh(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00001001), FPU_FPSP);
}
//
-// ftentox (6888X, 68040FPSP)
+// ftentox (6888X, 68040FPSP, 68060FPSP)
//
int m_ftentox(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00010010), FPU_FPSP);
}
//
-// ftst (6888X, 68040)
+// FTRAPcc (6888X, 68040, 68060FPSP)
+//
+int m_ftrapcc(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7),
+ // so we need to extract them first and fill in the clobbered bits.
+ WORD opcode = (inst >> 3) & 0x1F;
+ inst = (inst & 0xFF07) | (0xF << 3);
+
+ if (siz == SIZW)
+ {
+ inst |= 2;
+ D_word(inst);
+ D_word(opcode);
+ D_word(a0exval);
+ }
+ else if (siz == SIZL)
+ {
+ inst |= 3;
+ D_word(inst);
+ D_word(opcode);
+ D_long(a0exval);
+ }
+ else if (siz == SIZN)
+ {
+ inst |= 4;
+ D_word(inst);
+ D_word(opcode);
+ return OK;
+ }
+
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
+ return OK;
+}
+
+
+//
+// ftst (6888X, 68040, 68060)
//
int m_ftst(WORD inst, WORD siz)
{
- return gen_fpu(inst, siz, B8(00111010), FPU_P_EMUL);
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00111010), FPU_NOWARN);
}
//
-// ftwotox (6888X, 68040FPSP)
+// ftwotox (6888X, 68040FPSP, 68060FPSP)
//
int m_ftwotox(WORD inst, WORD siz)
{
+ CHECKNOFPU;
return gen_fpu(inst, siz, B8(00010001), FPU_FPSP);
}
+
+/////////////////////////////////
+// //
+// 68060 specific instructions //
+// //
+/////////////////////////////////
+
+
+//
+// lpstop (68060)
+//
+int m_lpstop(WORD inst, WORD siz)
+{
+ CHECKNO60;
+ D_word(B16(00000001, 11000000));
+
+ if (a0exattr & DEFINED)
+ {
+ D_word(a0exval);
+ }
+ else
+ {
+ AddFixup(FU_WORD, sloc, a0expr);
+ D_word(0);
+ }
+
+ return OK;
+}
+
+
+//
+// plpa (68060)
+//
+int m_plpa(WORD inst, WORD siz)
+{
+ CHECKNO60;
+ inst |= a0reg; // Install register
+ D_word(inst);
+
+ return OK;
+}
+
projects / rmac / blobdiff