&& ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED))
&& ((a0exval > 0) && (a0exval <= 8)))
{
&& ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED))
&& ((a0exval > 0) && (a0exval <= 8)))
{
&& (siz == SIZL) && (am0 == IMMED) && (am1 == DREG)
&& ((a0exattr & (TDB | DEFINED)) == DEFINED)
&& (a0exval + 0x80 < 0x100))
&& (siz == SIZL) && (am0 == IMMED) && (am1 == DREG)
&& ((a0exattr & (TDB | DEFINED)) == DEFINED)
&& (a0exval + 0x80 < 0x100))