//
-// RMAC - Reboot's Macro Assembler for all Atari computers
+// RMAC - Renamed Macro Assembler for all Atari computers
// MACH.C - Code Generation
-// Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
+// Copyright (C) 199x Landon Dyer, 2011-2021 Reboot and Friends
// RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
// Source utilised with the kind permission of Landon Dyer
//
#include "sect.h"
#include "token.h"
-#define DEF_KW
-#include "kwtab.h"
+#define DEF_REG68
+#include "68kregs.h"
// Exported variables
int movep = 0; // Global flag to indicate we're generating a movep instruction
int m_chk2(WORD inst, WORD siz);
int m_cmp2(WORD inst, WORD siz);
int m_bkpt(WORD inst, WORD siz);
-int m_cpbr(WORD inst, WORD siz);
+int m_cpbcc(WORD inst, WORD siz);
int m_cpdbr(WORD inst, WORD siz);
int m_muls(WORD inst, WORD siz);
int m_move16a(WORD inst, WORD siz);
int m_pload(WORD inst, WORD siz, WORD extension);
int m_pmove(WORD inst, WORD siz);
int m_pmovefd(WORD inst, WORD siz);
-int m_ptest(WORD inst, WORD siz);
+int m_ptest(WORD inst, WORD siz, WORD extension);
+int m_ptestr(WORD inste, WORD siz);
+int m_ptestw(WORD inste, WORD siz);
int m_ptrapcc(WORD inst, WORD siz);
int m_ploadr(WORD inst, WORD siz);
int m_ploadw(WORD inst, WORD siz);
// FPU
int m_fabs(WORD inst, WORD siz);
+int m_fbcc(WORD inst, WORD siz);
int m_facos(WORD inst, WORD siz);
int m_fadd(WORD inst, WORD siz);
int m_fasin(WORD inst, WORD siz);
&& ((am0 == ADISP) && (a0reg == a1reg) && (a0exattr & DEFINED))
&& ((a0exval > 0) && (a0exval <= 8)))
{
- inst = B16(01010000, 01001000) | (((uint16_t)a0exval & 7) << 9) | (a0reg);
+ inst = 0b0101000001001000 | (((uint16_t)a0exval & 7) << 9) | (a0reg);
D_word(inst);
- warn("lea size(An),An converted to addq #size,An");
+
+ if (optim_warn_flag)
+ warn("o4: lea size(An),An converted to addq #size,An");
+
return OK;
}
//
int m_adda(WORD inst, WORD siz)
{
- if (a0exattr & DEFINED)
+ if ((a0exattr & DEFINED) && (am0 == IMMED))
{
- if (CHECK_OPTS(OPT_ADDA_ADDQ))
- if (a0exval > 1 && a0exval <= 8)
+ if (CHECK_OPTS(OPT_ADDA_ADDQ))
+ {
+ if ((a0exval > 1) && (a0exval <= 8))
+ {
// Immediate is between 1 and 8 so let's convert to addq
- return m_addq(B16(01010000, 00000000), siz);
- if (CHECK_OPTS(OPT_ADDA_LEA))
- if (a0exval > 8)
- {
- // Immediate is larger than 8 so let's convert to lea
- am0 = ADISP; // Change addressing mode
- a0reg = a1reg; // In ADISP a0reg is used instead of a1reg!
- return m_lea(B16(01000001, 11011000), SIZW);
+ return m_addq(0b0101000000000000, siz);
+
+ if (optim_warn_flag)
+ warn("o8: adda/suba size(An),An converted to addq/subq #size,An");
+ }
+ }
+
+ if (CHECK_OPTS(OPT_ADDA_LEA))
+ {
+ if ((a0exval > 8) && ((a0exval + 0x8000) < 0x10000))
+ {
+ // Immediate is larger than 8 and word size so let's convert to lea
+ am0 = ADISP; // Change addressing mode
+ a0reg = a1reg; // In ADISP a0reg is used instead of a1reg!
+
+ if (!(inst & (1 << 14)))
+ {
+ // We have a suba #x,AREG so let's negate the value
+ a0exval = -a0exval;
+ }
+
+ // We're going to rely on +o4 for this, so let's ensure that
+ // it's on, even just for this instruction
+ int return_value;
+ int temp_flag = optim_flags[OPT_LEA_ADDQ];
+ optim_flags[OPT_LEA_ADDQ] = 1; // Temporarily save switch state
+ return_value = m_lea(0b0100000111011000, SIZW);
+ optim_flags[OPT_LEA_ADDQ] = temp_flag; // Restore switch state
+ if (optim_warn_flag)
+ warn("o9: adda.w/l #x,Ay converted to lea x(Dy),Ay");
+ return return_value;
+ }
}
}
{
m_moveq((WORD)0x7000, (WORD)0);
- if (sbra_flag)
- warn("move.l #size,dx converted to moveq");
+ if (optim_warn_flag)
+ warn("o1: move.l #size,dx converted to moveq");
}
else
{
int m_move30(WORD inst, WORD size)
{
int siz = (int)size;
- inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
+
+ if (am0 > ABASE)
+ inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am0 - ABASE];
+ else
+ inst |= siz_12[siz] | reg_9[a1reg & 7] | a0reg | extra_addressing[am1 - ABASE] << 3;
D_word(inst);
inst |= v & 0xFF;
D_word(inst);
- if (sbra_flag)
- warn("Bcc.w/BSR.w converted to .s");
+ if (optim_warn_flag)
+ warn("o2: Bcc.w/BSR.w converted to .s");
return OK;
}
{
// .B
AddFixup(FU_BBRA | FU_PCREL | FU_SEXT, sloc, a0expr);
- D_word(inst);
+ // So here we have a small issue: this bra.s could be zero offset, but
+ // we can never know. Because unless we know beforehand that the
+ // offset will be zero (i.e. "bra.s +0"), it's going to be a label
+ // below this instruction! We do have an optimisation flag that can
+ // check against this during fixups, but we cannot rely on the state
+ // of the flag after all the file(s) have been processed because its
+ // state might have changed multiple times during file parsing. (Yes,
+ // there's a very low chance that this will ever happen but it's not
+ // zero!). So, we can use the byte that is going to be filled during
+ // fixups to store the state of the optimisation flag and read it
+ // during that stage so each bra.s will have its state stored neatly.
+ // Sleazy? Eh, who cares, like this will ever happen ;)
+ // One final note: we'd better be damn sure that the flag's value is
+ // less than 256 or magical stuff will happen!
+ D_word(inst | optim_flags[OPT_NULL_BRA]);
return OK;
}
else
goto immed1;
}
- if ((*tok >= KW_D0) && (*tok <= KW_A7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_A7))
{
// <rlist>, ea
if (reglist(&rmask) < 0)
if (!CHECK_OPTS(OPT_CLR_DX))
inst |= a0reg;
else
- inst = (a0reg << 9) | B16(01110000, 00000000);
+ {
+ inst = (a0reg << 9) | 0b0111000000000000;
+ if (optim_warn_flag)
+ warn("o7: clr.l Dx converted to moveq #0,Dx");
+ }
D_word(inst);
bfparam1 = bfval1 << 12;
//D_word((inst | am0 | a0reg | am1 | a1reg));
- if (inst == B16(11101111, 11000000))
+ if (inst == 0b1110111111000000)
+ {
// bfins special case
D_word((inst | am1 | a1reg));
+ }
else
+ {
D_word((inst | am0 | a0reg));
+ }
ea0gen(siz); // Generate EA
// Second instruction word - Dest register (if exists), Do, Offset, Dw, Width
- if (inst == B16(11101111, 11000000))
+ if (inst == 0b1110111111000000)
{
// bfins special case
inst = bfparam1 | bfparam2;
}
// Dc
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS accepts only data registers");
inst2 = (*tok++) & 7;
return error("missing comma");
// Du
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS accepts only data registers");
inst2 |= ((*tok++) & 7) << 6;
}
// Dc1
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst2 = (*tok++) & 7;
return error("missing colon");
// Dc2
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst3 = (*tok++) & 7;
return error("missing comma");
// Du1
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst2 |= ((*tok++) & 7) << 6;
return error("missing colon");
// Du2
- if ((*tok < KW_D0) && (*tok > KW_D7))
+ if ((*tok < REG68_D0) && (*tok > REG68_D7))
return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
inst3 |= ((*tok++) & 7) << 6;
// Rn1
if (*tok++ != '(')
return error("missing (");
- if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
inst2 |= (((*tok++) & 7) << 12) | (0 << 15);
- else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
inst2 |= (((*tok++) & 7) << 12) | (1 << 15);
else
return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
// Rn2
if (*tok++ != '(')
return error("missing (");
- if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
inst3 |= (((*tok++) & 7) << 12) | (0 << 15);
- else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ else if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
inst3 |= (((*tok++) & 7) << 12) | (1 << 15);
else
return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
//
-// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc))
-// TODO: Better checks for different instructions?
+// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc)), pbcc (68851)
//
-int m_cpbr(WORD inst, WORD siz)
+int m_fpbr(WORD inst, WORD siz)
{
- if ((activecpu & (CPU_68020 | CPU_68030)) && (!activefpu == 0))
- return error(unsupport);
if (a0exattr & DEFINED)
{
}
+//
+// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc))
+//
+int m_cpbcc(WORD inst, WORD siz)
+{
+ if (!(activecpu & (CPU_68020 | CPU_68030)))
+ return error(unsupport);
+
+ return m_fpbr(inst, siz);
+}
+
+
+//
+// fbcc(6808X, 68040, 68060)
+//
+int m_fbcc(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return m_fpbr(inst, siz);
+}
+
+
+//
+// pbcc(68851 but let's assume 68020 only)
+//
+int m_pbcc(WORD inst, WORD siz)
+{
+ CHECKNO20;
+ return m_fpbr(inst, siz);
+}
+
+
//
// cpdbcc(68020, 68030)
//
if (flg & 16)
{
- // OR-in register number
+ // OR-in register number
if (flg & 8)
inst |= reg_9[a1reg]; // ea1reg in bits 9..11
else
D_word(inst);
- // Generate ea0 if requested
+ // Generate ea0 if requested
if (flg & 2)
ea0gen(siz);
if (siz != SIZN)
return error("bad size suffix");
- if (*tok >= KW_D0 && *tok <= KW_D7)
+ if (*tok >= REG68_D0 && *tok <= REG68_D7)
{
// Dx,Dy,#<adjustment>
inst |= (0 << 3); // R/M
if (*tok != ',' && tok[2] != ',')
return error("missing comma");
- if (tok[1] < KW_D0 && tok[1] > KW_D7)
+ if (tok[1] < REG68_D0 && tok[1] > REG68_D7)
return error(syntax_error);
inst |= ((tok[1] & 7)<<9);
if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ','))
return error(syntax_error);
- if (tok[1] < KW_A0 && tok[1] > KW_A7)
+ if (tok[1] < REG68_A0 && tok[1] > REG68_A7)
return error(syntax_error);
- if (tok[5] < KW_A0 && tok[6] > KW_A7)
+ if (tok[5] < REG68_A0 && tok[6] > REG68_A7)
return error(syntax_error);
inst |= ((tok[1] & 7) << 0);
inst |= (0 << 6) | (a1reg);
switch (a0reg)
{
- case 0: // KW_IC40
+ case 0: // REG68_IC40
inst |= (2 << 6) | (a1reg);
break;
- case 1: // KW_DC40
+ case 1: // REG68_DC40
inst |= (1 << 6) | (a1reg);
break;
- case 2: // KW_BC40
+ case 2: // REG68_BC40
inst |= (3 << 6) | (a1reg);
break;
}
}
-//
-// PBcc (MC68851)
-//
-int m_pbcc(WORD inst, WORD siz)
-{
- CHECKNO20;
- return error("Not implemented yet.");
-}
-
-
//
// pflusha (68030, 68040)
//
}
else if (activecpu == CPU_68040)
{
- inst = B16(11110101, 00011000);
+ inst = 0b1111010100011000;
D_word(inst);
return OK;
}
fc = (uint16_t)a0exval;
break;
- case KW_D0:
- case KW_D1:
- case KW_D2:
- case KW_D3:
- case KW_D4:
- case KW_D5:
- case KW_D6:
- case KW_D7:
+ case REG68_D0:
+ case REG68_D1:
+ case REG68_D2:
+ case REG68_D3:
+ case REG68_D4:
+ case REG68_D5:
+ case REG68_D6:
+ case REG68_D7:
fc = (1 << 4) | (*tok++ & 7);
break;
- case KW_SFC:
+ case REG68_SFC:
fc = 0;
tok++;
break;
- case KW_DFC:
+ case REG68_DFC:
fc = 1;
tok++;
break;
if (*tok != '(' && tok[2] != ')')
return error(syntax_error);
- if (tok[1] < KW_A0 && tok[1] > KW_A7)
+ if (tok[1] < REG68_A0 && tok[1] > REG68_A7)
return error("expected (An)");
if ((inst & 7) == 7)
ea1gen(siz);
}
- D_word(B16(10100000, 00000000));
+ D_word(0b1010000000000000);
return OK;
}
switch (am0)
{
case CREG:
- if (a0reg == KW_SFC - KW_SFC)
+ if (a0reg == REG68_SFC - REG68_SFC)
inst = 0;
- else if (a0reg == KW_DFC - KW_SFC)
+ else if (a0reg == REG68_DFC - REG68_SFC)
inst = 1;
else
return error("illegal control register specified");
-
break;
case DREG:
inst = (1 << 3) | a0reg;
if ((a0exattr & DEFINED) == 0)
return error("constant value must be defined");
+ if (a0exval>7)
+ return error("constant value must be between 0 and 7");
+
inst = (2 << 3) | (uint16_t)a0exval;
break;
}
// and the transparent translation registers(TT0 and TT1).
// It is a word operation for the MMU status register.
- if (((reg == (KW_URP - KW_SFC)) || (reg == (KW_SRP - KW_SFC)))
+ if (((reg == (REG68_URP - REG68_SFC)) || (reg == (REG68_SRP - REG68_SFC)))
&& ((siz != SIZD) && (siz != SIZN)))
return error(siz_error);
- if (((reg == (KW_TC - KW_SFC)) || (reg == (KW_TT0 - KW_SFC)) || (reg == (KW_TT1 - KW_SFC)))
+ if (((reg == (REG68_TC - REG68_SFC)) || (reg == (REG68_TT0 - REG68_SFC)) || (reg == (REG68_TT1 - REG68_SFC)))
&& ((siz != SIZL) && (siz != SIZN)))
return error(siz_error);
- if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN)))
+ if ((reg == (REG68_MMUSR - REG68_SFC)) && ((siz != SIZW) && (siz != SIZN)))
return error(siz_error);
if (am0 == CREG)
D_word(inst);
}
- switch (reg + KW_SFC)
+ switch (reg + REG68_SFC)
{
- case KW_TC:
+ case REG68_TC:
inst2 |= (0 << 10) + (1 << 14); break;
- case KW_SRP:
+ case REG68_SRP:
inst2 |= (2 << 10) + (1 << 14); break;
- case KW_CRP:
+ case REG68_CRP:
inst2 |= (3 << 10) + (1 << 14); break;
- case KW_TT0:
+ case REG68_TT0:
inst2 |= (2 << 10) + (0 << 13); break;
- case KW_TT1:
+ case REG68_TT1:
inst2 |= (3 << 10) + (0 << 13); break;
- case KW_MMUSR:
+ case REG68_MMUSR:
if (am0 == CREG)
inst2 |= (1 << 9) + (3 << 13);
else
//
-// ptestr, ptestw (68030)
+// ptestr, ptestw (68030, 68040)
+// TODO See comment on m_pmove about 68851 support
+// TODO quite a good chunk of the 030 code is copied from m_pload, perhaps merge these somehow?
//
-int m_ptest(WORD inst, WORD siz)
+int m_ptest(WORD inst, WORD siz, WORD extension)
{
- CHECKNO30;
+ uint64_t eval;
+
+ if (activecpu != CPU_68030 && activecpu != CPU_68040)
+ return error(unsupport);
if (activecpu == CPU_68030)
- return error("Not implemented yet.");
- else if (activecpu == CPU_68040)
+ {
+ inst |= am1;
+ D_word(inst);
+
+ switch (am0)
+ {
+ case CREG:
+ if (a0reg == REG68_SFC - REG68_SFC)
+ extension |= 0;
+ else if (a0reg == REG68_DFC - REG68_SFC)
+ extension |= 1;
+ else
+ return error("illegal control register specified");
+ break;
+ case DREG:
+ extension |= (1 << 3) | a0reg;
+ break;
+ case IMMED:
+ if ((a0exattr & DEFINED) == 0)
+ return error("constant value must be defined");
+
+ if (a0exval > 7)
+ return error("constant value must be between 0 and 7");
+
+ extension |= (2 << 3) | (uint16_t)a0exval;
+ break;
+ }
+
+ // Operand 3 must be an immediate
+ CHECK_COMMA
+
+ if (*tok++ != '#')
+ return error("ptest level must be immediate");
+
+ // Let's be a bit inflexible here and demand that this
+ // is fully defined at this stage. Otherwise we'd have
+ // to arrange for a bitfield fixup, which would mean
+ // polluting the bitfields and codebase with special
+ // cases that might most likely never be used.
+ // So if anyone gets bit by this: sorry for being a butt!
+ if (abs_expr(&eval) != OK)
+ return OK; // We're returning OK because error() has already been called and error count has been increased
+
+ if (eval > 7)
+ return error("ptest level must be between 0 and 7");
+
+ extension |= eval << 10;
+
+ // Operand 4 is optional and must be an address register
+
+ if (*tok != EOL)
+ {
+ CHECK_COMMA
+
+ if ((*tok >= REG68_A0) && (*tok <= REG68_A7))
+ {
+ extension |= (1 << 8) | ((*tok++ & 7) << 4);
+ }
+ else
+ {
+ return error("fourth parameter must be an address register");
+ }
+ }
+
+ ErrorIfNotAtEOL();
+
+ D_word(extension);
+ return OK;
+ }
+ else
return error("Not implemented yet.");
return ERROR;
}
+int m_ptestr(WORD inst, WORD siz)
+{
+ return m_ptest(inst, siz, (1 << 15) | (0 << 9));
+}
+
+int m_ptestw(WORD inst, WORD siz)
+{
+ return m_ptest(inst, siz, (1 << 15) | (1 << 9));
+}
+
//////////////////////////////////////////////////////////////////////////////
//
// 68020/30/40/60 instructions
int m_fabs(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00011000, FPU_NOWARN);
}
{
CHECKNO40;
if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011000, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdabs(WORD inst, WORD siz)
{
if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01011100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011100, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_facos(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011100, FPU_FPSP);
}
int m_fadd(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00100010, FPU_NOWARN);
}
int m_fsadd(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100010, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdadd(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100110), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100110, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fasin(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001100, FPU_FPSP);
}
int m_fatan(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001010), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001010, FPU_FPSP);
}
int m_fatanh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001101, FPU_FPSP);
}
int m_fcmp(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00111000), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00111000, FPU_FPSP);
}
int m_fcos(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011101, FPU_FPSP);
}
int m_fcosh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011001, FPU_FPSP);
}
int m_fdiv(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00100000, FPU_NOWARN);
}
int m_fsdiv(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100000, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fddiv(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100100, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fetox(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010000), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010000, FPU_FPSP);
}
int m_fetoxm1(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001000), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001000, FPU_FPSP);
}
int m_fgetexp(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011110, FPU_FPSP);
}
int m_fgetman(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00011111), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00011111, FPU_FPSP);
}
if (activefpu == FPU_68040)
warn("Instruction is emulated in 68040");
- return gen_fpu(inst, siz, B8(00000001), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00000001, FPU_NOWARN);
}
if (activefpu == FPU_68040)
warn("Instruction is emulated in 68040");
-
- return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN);
+
+ return gen_fpu(inst, siz, 0b00000011, FPU_NOWARN);
}
int m_flog10(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010101, FPU_FPSP);
}
int m_flog2(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010110, FPU_FPSP);
}
int m_flogn(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010100, FPU_FPSP);
}
//
-// flognp1 (68040FPSP, 68060FPSP)
+// flognp1 (6888X, 68040FPSP, 68060FPSP)
//
int m_flognp1(WORD inst, WORD siz)
{
- if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(00000110), FPU_FPSP);
-
- return error("Unsupported in current FPU");
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, 0b00000110, FPU_FPSP);
}
int m_fmod(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100001, FPU_FPSP);
}
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return error("Not implemented yet.");
-
-#if 0
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
-#endif
+ return gen_fpu(inst, siz, 0b01100100, FPU_FPSP);
}
if (!(activefpu & (FPU_68040 | FPU_68060)))
return error("Unsupported in current FPU");
- return error("Not implemented yet.");
-
-#if 0
- if (activefpu == FPU_68040)
- return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
- else
- return error("Unsupported in current FPU");
-#endif
+ return gen_fpu(inst, siz, 0b01100100, FPU_FPSP);
}
if (siz == SIZX || siz == SIZN)
{
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
{
// fmovem.x <rlist>,ea
if (fpu_reglist_left(®mask) < 0)
ea0gen(siz);
return OK;
}
- else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ else if ((*tok >= REG68_D0) && (*tok <= REG68_D7))
{
// fmovem.x Dn,ea
datareg = (*tok++ & 7) << 10;
if (*tok++ != ',')
return error("missing comma");
- if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ if ((*tok >= REG68_FP0) && (*tok <= REG68_FP7))
{
// fmovem.x ea,<rlist>
if (fpu_reglist_right(®mask) < 0)
}
else if (siz == SIZL)
{
- if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR))
+ if ((*tok == REG68_FPCR) || (*tok == REG68_FPSR) || (*tok == REG68_FPIAR))
{
// fmovem.l <rlist>,ea
regmask = (1 << 15) | (1 << 13);
int no_control_regs = 0;
fmovem_loop_1:
- if (*tok == KW_FPCR)
+ if (*tok == REG68_FPCR)
{
regmask |= (1 << 12);
tok++;
goto fmovem_loop_1;
}
- if (*tok == KW_FPSR)
+ if (*tok == REG68_FPSR)
{
regmask |= (1 << 11);
tok++;
goto fmovem_loop_1;
}
- if (*tok == KW_FPIAR)
+ if (*tok == REG68_FPIAR)
{
regmask |= (1 << 10);
tok++;
regmask = (1 << 15) | (0 << 13);
fmovem_loop_2:
- if (*tok == KW_FPCR)
+ if (*tok == REG68_FPCR)
{
regmask |= (1 << 12);
tok++;
goto fmovem_loop_2;
}
- if (*tok == KW_FPSR)
+ if (*tok == REG68_FPSR)
{
regmask |= (1 << 11);
tok++;
goto fmovem_loop_2;
}
- if (*tok == KW_FPIAR)
+ if (*tok == REG68_FPIAR)
{
regmask |= (1 << 10);
tok++;
int m_fmul(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100011), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00100011, FPU_NOWARN);
}
int m_fsmul(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN);
-
+ return gen_fpu(inst, siz, 0b01100011, FPU_NOWARN);
+
return error("Unsupported in current FPU");
}
int m_fdmul(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01100111), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01100111, FPU_NOWARN);
return error("Unsupported in current FPU");
}
if (am1 == AM_NONE)
{
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00011010, FPU_NOWARN);
}
-
- return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
+
+ return gen_fpu(inst, siz, 0b00011010, FPU_NOWARN);
}
if (am1 == AM_NONE)
{
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011010, FPU_NOWARN);
}
-
- return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+
+ return gen_fpu(inst, siz, 0b01011010, FPU_NOWARN);
}
return error("Unsupported in current FPU");
if (am1 == AM_NONE)
{
a1reg = a0reg;
- return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011110, FPU_NOWARN);
}
- return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01011110, FPU_NOWARN);
}
return error("Unsupported in current FPU");
int m_fnop(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00000000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00000000, FPU_NOWARN);
}
int m_frem(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100101), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100101, FPU_FPSP);
}
int m_fscale(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100110, FPU_FPSP);
}
int m_fsgldiv(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100100), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100100, FPU_FPSP);
}
int m_fsglmul(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00100111), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00100111, FPU_FPSP);
}
int m_fsin(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001110), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001110, FPU_FPSP);
}
a2reg = a1reg;
a1reg = temp;
- if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK)
+ if (gen_fpu(inst, siz, 0b00110000, FPU_FPSP) == OK)
{
chptr[-1] |= a2reg;
return OK;
int m_fsinh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00000010), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00000010, FPU_FPSP);
}
int m_fsqrt(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00000100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00000100, FPU_NOWARN);
}
int m_fsfsqrt(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN);
-
+ return gen_fpu(inst, siz, 0b01000001, FPU_NOWARN);
+
return error("Unsupported in current FPU");
}
int m_fdfsqrt(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01000101), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01000101, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fsub(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00101000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00101000, FPU_NOWARN);
}
int m_fsfsub(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01101000), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01101000, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_fdsub(WORD inst, WORD siz)
{
if (activefpu & (FPU_68040 | FPU_68060))
- return gen_fpu(inst, siz, B8(01101100), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b01101100, FPU_NOWARN);
return error("Unsupported in current FPU");
}
int m_ftan(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001111), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001111, FPU_FPSP);
}
int m_ftanh(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00001001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00001001, FPU_FPSP);
}
int m_ftentox(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010010), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010010, FPU_FPSP);
}
int m_ftst(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00111010), FPU_NOWARN);
+ return gen_fpu(inst, siz, 0b00111010, FPU_NOWARN);
}
int m_ftwotox(WORD inst, WORD siz)
{
CHECKNOFPU;
- return gen_fpu(inst, siz, B8(00010001), FPU_FPSP);
+ return gen_fpu(inst, siz, 0b00010001, FPU_FPSP);
}
int m_lpstop(WORD inst, WORD siz)
{
CHECKNO60;
- D_word(B16(00000001, 11000000));
+ D_word(0b0000000111000000);
- if (a0exattr&DEFINED)
+ if (a0exattr & DEFINED)
+ {
D_word(a0exval);
+ }
else
{
AddFixup(FU_WORD, sloc, a0expr);
projects / rmac / blobdiff