+
+
+//
+// cas (68020, 68030, 68040)
+//
+int m_cas(WORD inst, WORD siz)
+{
+ WORD inst2;
+ LONG amsk;
+ int modes;
+
+ if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
+ return error(unsupport);
+
+ switch (siz)
+ {
+ case SIZB:
+ inst |= 1 << 9;
+ break;
+ case SIZW:
+ case SIZN:
+ inst |= 2 << 9;
+ break;
+ case SIZL:
+ inst |= 3 << 9;
+ break;
+ default:
+ return error("bad size suffix");
+ break;
+ }
+
+ // Dc
+ if ((*tok < KW_D0) && (*tok > KW_D7))
+ return error("CAS accepts only data registers");
+
+ inst2 = (*tok++) & 7;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ // Du
+ if ((*tok < KW_D0) && (*tok > KW_D7))
+ return error("CAS accepts only data registers");
+
+ inst2 |= ((*tok++) & 7) << 6;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ // ea
+ if ((modes = amode(1)) < 0)
+ return OK;
+
+ if (modes > 1)
+ return error("too many ea fields");
+
+ if (*tok != EOL)
+ return error("extra (unexpected) text found");
+
+ // Reject invalid ea modes
+ amsk = amsktab[am0];
+
+ if ((amsk & (M_AIND | M_APOSTINC | M_APREDEC | M_ADISP | M_AINDEXED | M_ABSW | M_ABSL | M_ABASE | M_MEMPOST | M_MEMPRE)) == 0)
+ return error("unsupported addressing mode");
+
+ inst |= am0 | a0reg;
+ D_word(inst);
+ D_word(inst2);
+ ea0gen(siz);
+
+ return OK;
+}
+
+
+//
+// cas2 (68020, 68030, 68040)
+//
+int m_cas2(WORD inst, WORD siz)
+{
+ WORD inst2, inst3;
+
+ if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
+ return error(unsupport);
+
+ switch (siz)
+ {
+ case SIZB:
+ inst |= 1 << 9;
+ break;
+ case SIZW:
+ case SIZN:
+ inst |= 2 << 9;
+ break;
+ case SIZL:
+ inst |= 3 << 9;
+ break;
+ default:
+ return error("bad size suffix");
+ break;
+ }
+
+ // Dc1
+ if ((*tok < KW_D0) && (*tok > KW_D7))
+ return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
+
+ inst2 = (*tok++) & 7;
+
+ if (*tok++ != ':')
+ return error("missing colon");
+
+ // Dc2
+ if ((*tok < KW_D0) && (*tok > KW_D7))
+ return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
+
+ inst3 = (*tok++) & 7;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ // Du1
+ if ((*tok < KW_D0) && (*tok > KW_D7))
+ return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
+
+ inst2 |= ((*tok++) & 7) << 6;
+
+ if (*tok++ != ':')
+ return error("missing colon");
+
+ // Du2
+ if ((*tok < KW_D0) && (*tok > KW_D7))
+ return error("CAS2 accepts only data registers for Dx1:Dx2 pairs");
+
+ inst3 |= ((*tok++) & 7) << 6;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ // Rn1
+ if (*tok++ != '(')
+ return error("missing (");
+ if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ inst2 |= (((*tok++) & 7) << 12) | (0 << 15);
+ else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ inst2 |= (((*tok++) & 7) << 12) | (1 << 15);
+ else
+ return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
+
+ if (*tok++ != ')')
+ return error("missing (");
+
+ if (*tok++ != ':')
+ return error("missing colon");
+
+ // Rn2
+ if (*tok++ != '(')
+ return error("missing (");
+ if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ inst3 |= (((*tok++) & 7) << 12) | (0 << 15);
+ else if ((*tok >= KW_A0) && (*tok <= KW_A7))
+ inst3 |= (((*tok++) & 7) << 12) | (1 << 15);
+ else
+ return error("CAS accepts either data or address registers for Rn1:Rn2 pair");
+
+ if (*tok++ != ')')
+ return error("missing (");
+
+ if (*tok != EOL)
+ return error("extra (unexpected) text found");
+
+ D_word(inst);
+ D_word(inst2);
+ D_word(inst3);
+
+ return OK;
+}
+
+
+//
+// cmp2 (68020, 68030, 68040, CPU32)
+//
+int m_cmp2(WORD inst, WORD siz)
+{
+ if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
+ return error(unsupport);
+
+ switch (siz & 0x000F)
+ {
+ case SIZW:
+ case SIZN:
+ inst |= 1 << 9;
+ break;
+ case SIZL:
+ inst |= 2 << 9;
+ break;
+ default:
+ // SIZB
+ break;
+ }
+
+ WORD flg = inst; // Save flag bits
+ inst &= ~0x3F; // Clobber flag bits in instr
+
+ // Install "standard" instr size bits
+ if (flg & 4)
+ inst |= siz_6[siz];
+
+ if (flg & 16)
+ {
+ // OR-in register number
+ if (flg & 8)
+ inst |= reg_9[a1reg]; // ea1reg in bits 9..11
+ else
+ inst |= reg_9[a0reg]; // ea0reg in bits 9..11
+ }
+
+ if (flg & 1)
+ {
+ // Use am1
+ inst |= am1 | a1reg; // Get ea1 into instr
+ D_word(inst); // Deposit instr
+
+ // Generate ea0 if requested
+ if (flg & 2)
+ ea0gen(siz);
+
+ ea1gen(siz); // Generate ea1
+ }
+ else
+ {
+ // Use am0
+ inst |= am0 | a0reg; // Get ea0 into instr
+ D_word(inst); // Deposit instr
+ ea0gen(siz); // Generate ea0
+
+ // Generate ea1 if requested
+ if (flg & 2)
+ ea1gen(siz);
+ }
+
+ // If we're called from chk2 then bit 11 of size will be set. This is just
+ // a dumb mechanism to pass this, required by the extension word. (You might
+ // have noticed the siz & 15 thing above!)
+ inst = (a1reg << 12) | (siz & (1 << 11));
+
+ if (am1 == AREG)
+ inst |= 1 << 15;
+
+ D_word(inst);
+
+ return OK;
+}
+
+
+//
+// chk2 (68020, 68030, 68040, CPU32)
+//
+int m_chk2(WORD inst, WORD siz)
+{
+ return m_cmp2(inst, siz | (1 << 11));
+}
+
+
+//
+// cpbcc(68020, 68030, 68040 (FBcc), 68060 (FBcc))
+// TODO: Better checks for different instructions?
+//
+int m_cpbr(WORD inst, WORD siz)
+{
+ if ((activecpu & (CPU_68020 | CPU_68030)) && (!activefpu == 0))
+ return error(unsupport);
+
+ if (a0exattr & DEFINED)
+ {
+ if ((a0exattr & TDB) != cursect)
+ return error(rel_error);
+
+ uint32_t v = (uint32_t)a0exval - (sloc + 2);
+
+ // Optimize branch instr. size
+ if (siz == SIZL)
+ {
+ if ((v != 0) && ((v + 0x8000) < 0x10000))
+ {
+ inst |= (1 << 6);
+ D_word(inst);
+ D_long(v);
+ return OK;
+ }
+ }
+ else // SIZW/SIZN
+ {
+ if ((v + 0x8000) >= 0x10000)
+ return error(range_error);
+
+ D_word(inst);
+ D_word(v);
+ }
+
+ return OK;
+ }
+ else if (siz == SIZN)
+ siz = SIZW;
+
+ if (siz == SIZL)
+ {
+ // .L
+ D_word(inst);
+ AddFixup(FU_LONG | FU_PCREL | FU_SEXT, sloc, a0expr);
+ D_long(0);
+ return OK;
+ }
+ else
+ {
+ // .W
+ D_word(inst);
+ AddFixup(FU_WORD | FU_PCREL | FU_SEXT, sloc, a0expr);
+ D_word(0);
+ }
+
+ return OK;
+}
+
+
+//
+// cpdbcc(68020, 68030)
+//
+int m_cpdbr(WORD inst, WORD siz)
+{
+ CHECK00;
+
+ uint32_t v;
+ WORD condition = inst & 0x1F; // Grab condition sneakily placed in the lower 5 bits of inst
+ inst &= 0xFFE0; // And then mask them out - you ain't seen me, roit?
+
+ inst |= (1 << 9); // Bolt on FPU id
+ inst |= a0reg;
+
+ D_word(inst);
+
+ D_word(condition);
+
+ if (a1exattr & DEFINED)
+ {
+ if ((a1exattr & TDB) != cursect)
+ return error(rel_error);
+
+ v = (uint32_t)a1exval - sloc;
+
+ if (v + 0x8000 > 0x10000)
+ return error(range_error);
+
+ D_word(v);
+ }
+ else
+ {
+ AddFixup(FU_WORD | FU_PCREL | FU_ISBRA, sloc, a1expr);
+ D_word(0);
+ }
+
+ return OK;
+
+}
+
+
+//
+// muls.l / divs.l / divu.l / mulu.l (68020+)
+//
+int m_muls(WORD inst, WORD siz)
+{
+ if ((activecpu & (CPU_68020 | CPU_68030 | CPU_68040)) == 0)
+ return error(unsupport);
+
+ WORD flg = inst; // Save flag bits
+ inst &= ~0x33F; // Clobber flag and extension bits in instr
+
+ // Install "standard" instr size bits
+ if (flg & 4)
+ inst |= siz_6[siz];
+
+ if (flg & 16)
+ {
+ // OR-in register number
+ if (flg & 8)
+ inst |= reg_9[a1reg]; // ea1reg in bits 9..11
+ else
+ inst |= reg_9[a0reg]; // ea0reg in bits 9..11
+ }
+
+ // Regarding extension word: bit 11 is signed/unsigned selector
+ // bit 10 is 32/64 bit selector
+ // Both of these are packed in bits 9 and 8 of the instruction
+ // field in 68ktab. Extra compilcations arise from the fact we
+ // have to distinguish between divu/s.l Dn,Dm (which is encoded
+ // as divu/s.l Dn,Dm:Dm) and divu/s.l Dn,Dm:Dx - the first is
+ // 32 bit while the second 64 bit
+
+ if (flg & 1)
+ {
+ // Use am1
+ inst |= am1 | a1reg; // Get ea1 into instr
+ D_word(inst); // Deposit instr
+
+ // Extension word
+ if (a1reg == a2reg)
+ inst = a1reg + (a2reg << 12) + ((flg & 0x200) << 2);
+ else
+ inst = a1reg + (a2reg << 12) + ((flg & 0x300) << 2);
+
+ D_word(inst);
+
+ // Generate ea0 if requested
+ if (flg & 2)
+ ea0gen(siz);
+
+ ea1gen(siz); // Generate ea1
+
+ return OK;
+ }
+ else
+ {
+ // Use am0
+ inst |= am0 | a0reg; // Get ea0 into instr
+ D_word(inst); // Deposit instr
+
+ // Extension word
+ if (a1reg == a2reg)
+ inst = a1reg + (a2reg << 12) + ((flg & 0x200) << 2);
+ else
+ inst = a1reg + (a2reg << 12) + ((flg & 0x300) << 2);
+
+ D_word(inst);
+
+ ea0gen(siz); // Generate ea0
+
+ // Generate ea1 if requested
+ if (flg & 2)
+ ea1gen(siz);
+
+ return OK;
+ }
+}
+
+
+//
+// move16 (ax)+,(ay)+
+//
+int m_move16a(WORD inst, WORD siz)
+{
+ if ((activecpu & (CPU_68040 | CPU_68060)) == 0)
+ return error(unsupport);
+
+ inst |= a0reg;
+ D_word(inst);
+ inst = (1 << 15) + (a1reg << 12);
+ D_word(inst);
+
+ return OK;
+}
+
+
+//
+// move16 with absolute address
+//
+int m_move16b(WORD inst, WORD siz)
+{
+ if ((activecpu & (CPU_68040 | CPU_68060)) == 0)
+ return error(unsupport);
+
+ int v;
+ inst |= a1reg;
+ D_word(inst);
+
+ if (am0 == APOSTINC)
+ {
+ if (am1 == AIND)
+ return error("Wasn't this suppose to call m_move16a???");
+ else
+ {
+ // move16 (ax)+,(xxx).L
+ inst |= 0 << 3;
+ v = (int)a1exval;
+ }
+ }
+ else if (am0 == ABSL)
+ {
+ if (am1 == AIND)
+ {
+ // move16 (xxx).L,(ax)+
+ inst |= 1 << 3;
+ v = (int)a0exval;
+ }
+ else // APOSTINC
+ {
+ // move16 (xxx).L,(ax)
+ inst |= 3 << 3;
+ v = (int)a0exval;
+ }
+ }
+ else if (am0 == AIND)
+ {
+ // move16 (ax),(xxx).L
+ inst |= 2 << 3;
+ v = (int)a1exval;
+ }
+
+ D_word(inst);
+ D_long(v);
+
+ return OK;
+}
+
+
+//
+// pack/unpack (68020/68030/68040)
+//
+int m_pack(WORD inst, WORD siz)
+{
+ CHECK00;
+
+ if (siz != SIZN)
+ return error("bad size suffix");
+
+ if (*tok >= KW_D0 && *tok <= KW_D7)
+ {
+ // Dx,Dy,#<adjustment>
+ inst |= (0 << 3); // R/M
+ inst |= (*tok++ & 7);
+
+ if (*tok != ',' && tok[2] != ',')
+ return error("missing comma");
+
+ if (tok[1] < KW_D0 && tok[1] > KW_D7)
+ return error(syntax_error);
+
+ inst |= ((tok[1] & 7)<<9);
+ tok = tok + 3;
+ D_word(inst);
+ // Fall through for adjustment (common in both valid cases)
+ }
+ else if (*tok == '-')
+ {
+ // -(Ax),-(Ay),#<adjustment>
+ inst |= (1 << 3); // R/M
+ tok++; // eat the minus
+
+ if ((*tok != '(') && (tok[2]!=')') && (tok[3]!=',') && (tok[4] != '-') && (tok[5] != '(') && (tok[7] != ')') && (tok[8] != ','))
+ return error(syntax_error);
+
+ if (tok[1] < KW_A0 && tok[1] > KW_A7)
+ return error(syntax_error);
+
+ if (tok[5] < KW_A0 && tok[6] > KW_A7)
+ return error(syntax_error);
+
+ inst |= ((tok[1] & 7) << 0);
+ inst |= ((tok[6] & 7) << 9);
+ tok = tok + 9;
+ D_word(inst);
+ // Fall through for adjustment (common in both valid cases)
+ }
+ else
+ return error("invalid syntax");
+
+ if ((*tok != CONST) && (*tok != SYMBOL) && (*tok != '-'))
+ return error(syntax_error);
+
+ if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR)
+ return ERROR;
+
+ if ((a0exattr & DEFINED) == 0)
+ return error(undef_error);
+
+ if (a0exval + 0x8000 > 0x10000)
+ return error("");
+
+ if (*tok != EOL)
+ return error(extra_stuff);
+
+ D_word((a0exval & 0xFFFF));
+
+ return OK;
+}
+
+
+//
+// rtm Rn
+//
+int m_rtm(WORD inst, WORD siz)
+{
+ CHECKNO20;
+
+ if (am0 == DREG)
+ {
+ inst |= a0reg;
+ }
+ else if (am0 == AREG)
+ {
+ inst |= (1 << 3) + a0reg;
+ }
+ else
+ return error("rtm only allows data or address registers.");
+
+ D_word(inst);
+
+ return OK;
+}
+
+
+//
+// rtd #n
+//
+int m_rtd(WORD inst, WORD siz)
+{
+ CHECK00;
+
+ if (a0exattr & DEFINED)
+ {
+ if (a0exattr & TDB)
+ return error(abs_error);
+
+ if ((a0exval + 0x8000) <= 0x7FFF)
+ return error(range_error);
+
+ D_word(inst);
+ D_word(a0exval);
+ }
+ else
+ return error(undef_error);
+
+ return OK;
+}
+
+
+//
+// trapcc
+//
+int m_trapcc(WORD inst, WORD siz)
+{
+ CHECK00;
+
+ if (am0 == AM_NONE)
+ {
+ D_word(inst);
+ }
+ else if (am0 == IMMED)
+ {
+ if (siz == SIZW)
+ {
+ if (a0exval < 0x10000)
+ {
+ inst |= 2;
+ D_word(inst);
+ D_word(a0exval);
+ }
+ else
+ return error("Immediate value too big");
+ }
+ else //DOTL
+ {
+ inst |= 3;
+ D_word(inst);
+ D_long(a0exval);
+ }
+ }
+ else
+ return error("Invalid parameter for trapcc");
+
+ return OK;
+}
+
+
+//
+// cinvl/p/a (68040/68060)
+//
+int m_cinv(WORD inst, WORD siz)
+{
+ CHECKNO40;
+
+ if (am1 == AM_NONE)
+ inst |= (0 << 6) | (a1reg);
+ switch (a0reg)
+ {
+ case 0: // KW_IC40
+ inst |= (2 << 6) | (a1reg);
+ break;
+ case 1: // KW_DC40
+ inst |= (1 << 6) | (a1reg);
+ break;
+ case 2: // KW_BC40
+ inst |= (3 << 6) | (a1reg);
+ break;
+ }
+
+ D_word(inst);
+ return OK;
+}
+
+
+int m_fpusavrest(WORD inst, WORD siz)
+{
+ inst |= am0 | a0reg;
+ D_word(inst);
+ ea0gen(siz);
+
+ return OK;
+}
+
+
+//
+// cpSAVE/cpRESTORE (68020, 68030)
+//
+int m_cprest(WORD inst, WORD siz)
+{
+ if (activecpu & !(CPU_68020 | CPU_68030))
+ return error(unsupport);
+
+ return m_fpusavrest(inst, siz);
+
+}
+
+
+//
+// FSAVE/FRESTORE (68040, 68060)
+//
+int m_frestore(WORD inst, WORD siz)
+{
+ if ((!(activecpu & (CPU_68040 | CPU_68060))) ||
+ (activefpu&(FPU_68881 | FPU_68882)))
+ return error(unsupport);
+
+ return m_fpusavrest(inst, siz);
+}
+
+
+//
+// movec (68010, 68020, 68030, 68040, 68060, CPU32)
+//
+int m_movec(WORD inst, WORD siz)
+{
+ CHECK00;
+
+ if (am0 == DREG || am0 == AREG)
+ {
+ // movec Rn,Rc
+ inst |= 1;
+ D_word(inst);
+
+ if (am0 == DREG)
+ {
+ inst = (0 << 15) + (a0reg << 12) + CREGlut[a1reg];
+ D_word(inst);
+ }
+ else
+ {
+ inst = (1 << 15) + (a0reg << 12) + CREGlut[a1reg];
+ D_word(inst);
+ }
+ }
+ else
+ {
+ // movec Rc,Rn
+ D_word(inst);
+
+ if (am1 == DREG)
+ {
+ inst = (0 << 15) + (a1reg << 12) + CREGlut[a0reg];
+ D_word(inst);
+ }
+ else
+ {
+ inst = (1 << 15) + (a1reg << 12) + CREGlut[a0reg];
+ D_word(inst);
+ }
+ }
+
+ return OK;
+}
+
+
+//
+// moves (68010, 68020, 68030, 68040, CPU32)
+//
+int m_moves(WORD inst, WORD siz)
+{
+ if (activecpu & !(CPU_68020 | CPU_68030 | CPU_68040))
+ return error(unsupport);
+
+ if (siz == SIZB)
+ inst |= 0 << 6;
+ else if (siz == SIZL)
+ inst |= 2 << 6;
+ else // SIZW/SIZN
+ inst |= 1 << 6;
+
+ if (am0 == DREG)
+ {
+ inst |= am1 | a1reg;
+ D_word(inst);
+ inst = (a0reg << 12) | (1 << 11) | (0 << 15);
+ D_word(inst);
+ }
+ else if (am0 == AREG)
+ {
+ inst |= am1 | a1reg;
+ D_word(inst);
+ inst = (a0reg << 12) | (1 << 11) | (1 << 15);
+ D_word(inst);
+ }
+ else
+ {
+ if (am1 == DREG)
+ {
+ inst |= am0 | a0reg;
+ D_word(inst);
+ inst = (a1reg << 12) | (0 << 11) | (0 << 15);
+ D_word(inst);
+ }
+ else
+ {
+ inst |= am0 | a0reg;
+ D_word(inst);
+ inst = (a1reg << 12) | (0 << 11) | (1 << 15);
+ D_word(inst);
+ }
+ }
+
+ return OK;
+}
+
+
+//
+// PBcc (MC68851)
+//
+int m_pbcc(WORD inst, WORD siz)
+{
+ CHECKNO20;
+ return error("Not implemented yet.");
+}
+
+
+//
+// pflusha (68030, 68040)
+//
+int m_pflusha(WORD inst, WORD siz)
+{
+ if (activecpu == CPU_68030)
+ {
+ D_word(inst);
+ inst = (1 << 13) | (1 << 10) | (0 << 5) | 0;
+ D_word(inst);
+ return OK;
+ }
+ else if (activecpu == CPU_68040)
+ {
+ inst = B16(11110101, 00011000);
+ D_word(inst);
+ return OK;
+ }
+ else
+ return error(unsupport);
+
+ return OK;
+}
+
+
+//
+// pflush (68030, 68040, 68060)
+//
+int m_pflush(WORD inst, WORD siz)
+{
+ if (activecpu == CPU_68030)
+ {
+ // PFLUSH FC, MASK
+ // PFLUSH FC, MASK, < ea >
+ WORD mask, fc;
+
+ switch ((int)*tok)
+ {
+ case '#':
+ tok++;
+
+ if (*tok != CONST && *tok != SYMBOL)
+ return error("function code should be an expression");
+
+ if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR)
+ return ERROR;
+
+ if ((a0exattr & DEFINED) == 0)
+ return error("function code immediate should be defined");
+
+ if (a0exval > 7)
+ return error("function code out of range (0-7)");
+
+ fc = (uint16_t)a0exval;
+ break;
+ case KW_D0:
+ case KW_D1:
+ case KW_D2:
+ case KW_D3:
+ case KW_D4:
+ case KW_D5:
+ case KW_D6:
+ case KW_D7:
+ fc = (1 << 4) | (*tok++ & 7);
+ break;
+ case KW_SFC:
+ fc = 0;
+ tok++;
+ break;
+ case KW_DFC:
+ fc = 1;
+ tok++;
+ break;
+ default:
+ return error(syntax_error);
+ }
+
+ if (*tok++ != ',')
+ return error("comma exptected");
+
+ if (*tok++ != '#')
+ return error("mask should be an immediate value");
+
+ if (*tok != CONST && *tok != SYMBOL)
+ return error("mask is supposed to be immediate");
+
+ if (expr(a0expr, &a0exval, &a0exattr, &a0esym) == ERROR)
+ return ERROR;
+
+ if ((a0exattr & DEFINED) == 0)
+ return error("mask immediate value should be defined");
+
+ if (a0exval > 7)
+ return error("function code out of range (0-7)");
+
+ mask = (uint16_t)a0exval << 5;
+
+ if (*tok == EOL)
+ {
+ // PFLUSH FC, MASK
+ D_word(inst);
+ inst = (1 << 13) | fc | mask | (4 << 10);
+ D_word(inst);
+ return OK;
+ }
+ else if (*tok == ',')
+ {
+ // PFLUSH FC, MASK, < ea >
+ tok++;
+
+ if (amode(0) == ERROR)
+ return ERROR;
+
+ if (*tok != EOL)
+ return error(extra_stuff);
+
+ if (am0 == AIND || am0 == ABSW || am0 == ABSL || am0 == ADISP || am0 == ADISP || am0 == AINDEXED || am0 == ABASE || am0 == MEMPOST || am0 == MEMPRE)
+ {
+ inst |= am0 | a0reg;
+ D_word(inst);
+ inst = (1 << 13) | fc | mask | (6 << 10);
+ D_word(inst);
+ ea0gen(siz);
+ return OK;
+ }
+ else
+ return error("unsupported addressing mode");
+
+ }
+ else
+ return error(syntax_error);
+
+ return OK;
+ }
+ else if (activecpu == CPU_68040 || activecpu == CPU_68060)
+ {
+ // PFLUSH(An)
+ // PFLUSHN(An)
+ if (*tok != '(' && tok[2] != ')')
+ return error(syntax_error);
+
+ if (tok[1] < KW_A0 && tok[1] > KW_A7)
+ return error("expected (An)");
+
+ if ((inst & 7) == 7)
+ // With pflushn/pflush there's no easy way to distinguish between
+ // the two in 68040 mode. Ideally the opcode bitfields would have
+ // been hardcoded in 68ktab but there is aliasing between 68030
+ // and 68040 opcode. So we just set the 3 lower bits to 1 in
+ // pflushn inside 68ktab and detect it here.
+ inst = (inst & 0xff8) | 8;
+
+ inst |= (tok[1] & 7) | (5 << 8);
+
+ if (tok[3] != EOL)
+ return error(extra_stuff);
+
+ D_word(inst);
+ }
+ else
+ return error(unsupport);
+
+ return OK;
+}
+
+
+//
+// pflushan (68040, 68060)
+//
+int m_pflushan(WORD inst, WORD siz)
+{
+ if (activecpu == CPU_68040 || activecpu == CPU_68060)
+ D_word(inst);
+
+ return OK;
+}
+
+
+//
+// pflushr (68851)
+//
+int m_pflushr(WORD inst, WORD siz)
+{
+ CHECKNO20;
+
+ WORD flg = inst; // Save flag bits
+ inst &= ~0x3F; // Clobber flag bits in instr
+
+ // Install "standard" instr size bits
+ if (flg & 4)
+ inst |= siz_6[siz];
+
+ if (flg & 16)
+ {
+ // OR-in register number
+ if (flg & 8)
+ inst |= reg_9[a1reg]; // ea1reg in bits 9..11
+ else
+ inst |= reg_9[a0reg]; // ea0reg in bits 9..11
+ }
+
+ if (flg & 1)
+ {
+ // Use am1
+ inst |= am1 | a1reg; // Get ea1 into instr
+ D_word(inst); // Deposit instr
+
+ // Generate ea0 if requested
+ if (flg & 2)
+ ea0gen(siz);
+
+ ea1gen(siz); // Generate ea1
+ }
+ else
+ {
+ // Use am0
+ inst |= am0 | a0reg; // Get ea0 into instr
+ D_word(inst); // Deposit instr
+ ea0gen(siz); // Generate ea0
+
+ // Generate ea1 if requested
+ if (flg & 2)
+ ea1gen(siz);
+ }
+
+ D_word(B16(10100000, 00000000));
+ return OK;
+}
+
+
+//
+// ploadr, ploadw (68030)
+//
+int m_pload(WORD inst, WORD siz, WORD extension)
+{
+ // TODO: 68851 support is not added yet.
+ // None of the ST series of computers had a 68020 + 68851 socket and since
+ // this is an Atari targetted assembler...
+ CHECKNO30;
+
+ inst |= am1;
+ D_word(inst);
+
+ switch (am0)
+ {
+ case CREG:
+ if (a0reg == KW_SFC - KW_SFC)
+ inst = 0;
+ else if (a0reg == KW_DFC - KW_SFC)
+ inst = 1;
+ else
+ return error("illegal control register specified");
+
+ break;
+ case DREG:
+ inst = (1 << 3) | a0reg;
+ break;
+ case IMMED:
+ if ((a0exattr & DEFINED) == 0)
+ return error("constant value must be defined");
+
+ inst = (2 << 3) | (uint16_t)a0exval;
+ break;
+ }
+
+ inst |= extension | (1 << 13);
+ D_word(inst);
+
+ ea1gen(siz);
+
+ return OK;
+}
+
+
+int m_ploadr(WORD inst, WORD siz)
+{
+ return m_pload(inst, siz, 1 << 9);
+}
+
+
+int m_ploadw(WORD inst, WORD siz)
+{
+ return m_pload(inst, siz, 0 << 9);
+}
+
+
+//
+// pmove (68030/68851)
+//
+int m_pmove(WORD inst, WORD siz)
+{
+ int inst2,reg;
+
+ // TODO: 68851 support is not added yet. None of the ST series of
+ // computers had a 68020 + 68851 socket and since this is an Atari
+ // targetted assembler.... (same for 68EC030)
+ CHECKNO30;
+
+ inst2 = inst & (1 << 8); // Copy the flush bit over to inst2 in case we're called from m_pmovefd
+ inst &= ~(1 << 8); // And mask it out
+
+ if (am0 == CREG)
+ {
+ reg = a0reg;
+ inst2 |= (1 << 9);
+ }
+ else if (am1 == CREG)
+ {
+ reg = a1reg;
+ inst2 |= 0;
+ }
+ else
+ return error("pmove sez: Wut?");
+
+ // The instruction is a quad-word (8 byte) operation
+ // for the CPU root pointer and the supervisor root pointer.
+ // It is a long-word operation for the translation control register
+ // and the transparent translation registers(TT0 and TT1).
+ // It is a word operation for the MMU status register.
+
+ if (((reg == (KW_URP - KW_SFC)) || (reg == (KW_SRP - KW_SFC)))
+ && ((siz != SIZD) && (siz != SIZN)))
+ return error(siz_error);
+
+ if (((reg == (KW_TC - KW_SFC)) || (reg == (KW_TT0 - KW_SFC)) || (reg == (KW_TT1 - KW_SFC)))
+ && ((siz != SIZL) && (siz != SIZN)))
+ return error(siz_error);
+
+ if ((reg == (KW_MMUSR - KW_SFC)) && ((siz != SIZW) && (siz != SIZN)))
+ return error(siz_error);
+
+ if (am0 == CREG)
+ {
+ inst |= am1 | a1reg;
+ D_word(inst);
+ }
+ else if (am1 == CREG)
+ {
+ inst |= am0 | a0reg;
+ D_word(inst);
+ }
+
+ switch (reg + KW_SFC)
+ {
+ case KW_TC:
+ inst2 |= (0 << 10) + (1 << 14); break;
+ case KW_SRP:
+ inst2 |= (2 << 10) + (1 << 14); break;
+ case KW_CRP:
+ inst2 |= (3 << 10) + (1 << 14); break;
+ case KW_TT0:
+ inst2 |= (2 << 10) + (0 << 13); break;
+ case KW_TT1:
+ inst2 |= (3 << 10) + (0 << 13); break;
+ case KW_MMUSR:
+ if (am0 == CREG)
+ inst2 |= (1 << 9) + (3 << 13);
+ else
+ inst2 |= (0 << 9) + (3 << 13);
+ break;
+ default:
+ return error("unsupported register");
+ break;
+ }
+
+ D_word(inst2);
+
+ if (am0 == CREG)
+ ea1gen(siz);
+ else if (am1 == CREG)
+ ea0gen(siz);
+
+ return OK;
+}
+
+
+//
+// pmovefd (68030)
+//
+int m_pmovefd(WORD inst, WORD siz)
+{
+ CHECKNO30;
+
+ return m_pmove(inst | (1 << 8), siz);
+}
+
+
+//
+// ptrapcc (68851)
+//
+int m_ptrapcc(WORD inst, WORD siz)
+{
+ CHECKNO20;
+ // We stash the 5 condition bits inside the opcode in 68ktab (bits 0-4),
+ // so we need to extract them first and fill in the clobbered bits.
+ WORD opcode = inst & 0x1F;
+ inst = (inst & 0xFFE0) | (0x18);
+
+ if (siz == SIZW)
+ {
+ inst |= 2;
+ D_word(inst);
+ D_word(opcode);
+ D_word(a0exval);
+ }
+ else if (siz == SIZL)
+ {
+ inst |= 3;
+ D_word(inst);
+ D_word(opcode);
+ D_long(a0exval);
+ }
+ else if (siz == SIZN)
+ {
+ inst |= 4;
+ D_word(inst);
+ D_word(opcode);
+ }
+
+ return OK;
+}
+
+
+//
+// ptestr, ptestw (68030)
+//
+int m_ptest(WORD inst, WORD siz)
+{
+ CHECKNO30;
+
+ if (activecpu == CPU_68030)
+ return error("Not implemented yet.");
+ else if (activecpu == CPU_68040)
+ return error("Not implemented yet.");
+
+ return ERROR;
+}
+
+//////////////////////////////////////////////////////////////////////////////
+//
+// 68020/30/40/60 instructions
+// Note: the map of which instructions are allowed on which CPUs came from the
+// 68060 manual, section D-1 (page 392 of the PDF). The current implementation
+// is missing checks for the EC models which have a simplified FPU.
+//
+//////////////////////////////////////////////////////////////////////////////
+
+
+#define FPU_NOWARN 0
+#define FPU_FPSP 1
+
+
+//
+// Generate a FPU opcode
+//
+static inline int gen_fpu(WORD inst, WORD siz, WORD opmode, WORD emul)
+{
+ if (am0 < AM_NONE) // Check first operand for ea or fp - is this right?
+ {
+ inst |= (1 << 9); // Bolt on FPU id
+ inst |= am0;
+
+ //if (am0 == DREG || am0 == AREG)
+ inst |= a0reg;
+
+ D_word(inst);
+ inst = 1 << 14; // R/M field (we have ea so have to set this to 1)
+
+ switch (siz)
+ {
+ case SIZB: inst |= (6 << 10); break;
+ case SIZW: inst |= (4 << 10); break;
+ case SIZL: inst |= (0 << 10); break;
+ case SIZN:
+ case SIZS: inst |= (1 << 10); break;
+ case SIZD: inst |= (5 << 10); break;
+ case SIZX: inst |= (2 << 10); break;
+ case SIZP:
+ inst |= (3 << 10);
+
+ if (emul)
+ warn("This encoding will cause an unimplemented data type exception in the MC68040 to allow emulation in software.");
+
+ break;
+ default:
+ return error("Something bad happened, possibly, in gen_fpu.");
+ break;
+ }
+
+ inst |= (a1reg << 7);
+ inst |= opmode;
+ D_word(inst);
+ ea0gen(siz);
+ }
+ else
+ {
+ inst |= (1 << 9); // Bolt on FPU id
+ D_word(inst);
+ inst = 0;
+ inst = a0reg << 10;
+ inst |= (a1reg << 7);
+ inst |= opmode;
+ D_word(inst);
+ }
+
+ if ((emul & FPU_FPSP) && (activefpu == (FPU_68040 | FPU_68060)))
+ warn("Instruction is emulated in 68040/060");
+
+ return OK;
+}
+
+
+//
+// fabs (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fabs(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00011000), FPU_NOWARN);
+}
+
+
+//
+// fsabs (68040, 68060)
+//
+int m_fsabs(WORD inst, WORD siz)
+{
+ CHECKNO40;
+ if (activefpu == FPU_68040)
+ return gen_fpu(inst, siz, B8(01011000), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fdabs (68040, 68060)
+//
+int m_fdabs(WORD inst, WORD siz)
+{
+ if (activefpu == FPU_68040)
+ return gen_fpu(inst, siz, B8(01011100), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// facos (6888X, 68040FPSP, 68060FPSP)
+//
+int m_facos(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00011100), FPU_FPSP);
+}
+
+
+//
+// fadd (6888X, 68040, 68060)
+//
+int m_fadd(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100010), FPU_NOWARN);
+}
+
+
+//
+// fsadd (68040, 68060)
+//
+int m_fsadd(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100010), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fxadd (68040)
+//
+int m_fdadd(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100110), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fasin (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fasin(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00001100), FPU_FPSP);
+}
+
+
+//
+// fatan (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fatan(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00001010), FPU_FPSP);
+}
+
+
+//
+// fatanh (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fatanh(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00001101), FPU_FPSP);
+}
+
+
+//
+// fcmp (6888X, 68040, 68060)
+//
+int m_fcmp(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00111000), FPU_FPSP);
+}
+
+
+//
+// fcos (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fcos(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00011101), FPU_FPSP);
+}
+
+
+//
+// fcosh (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fcosh(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00011001), FPU_FPSP);
+}
+
+
+//
+// fdbcc (6888X, 68040, 68060FPSP)
+//
+int m_fdbcc(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ WORD opcode = inst & 0x3F; // Grab conditional bitfield
+
+ inst &= ~0x3F;
+ inst |= 1 << 3;
+
+ siz = siz;
+ inst |= a0reg;
+ D_word(inst);
+ D_word(opcode);
+
+ if (a1exattr & DEFINED)
+ {
+ if ((a1exattr & TDB) != cursect)
+ return error(rel_error);
+
+ uint32_t v = (uint32_t)a1exval - sloc;
+
+ if ((v + 0x8000) > 0x10000)
+ return error(range_error);
+
+ D_word(v);
+ }
+ else
+ {
+ AddFixup(FU_WORD | FU_PCREL | FU_ISBRA, sloc, a1expr);
+ D_word(0);
+ }
+
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
+ return OK;
+}
+
+
+//
+// fdiv (6888X, 68040, 68060)
+//
+int m_fdiv(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100000), FPU_NOWARN);
+}
+
+
+//
+// fsdiv (68040, 68060)
+//
+int m_fsdiv(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100000), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fddiv (68040, 68060)
+//
+int m_fddiv(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100100), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fetox (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fetox(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00010000), FPU_FPSP);
+}
+
+
+//
+// fetoxm1 (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fetoxm1(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00001000), FPU_FPSP);
+}
+
+
+//
+// fgetexp (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fgetexp(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00011110), FPU_FPSP);
+}
+
+
+//
+// fgetman (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fgetman(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00011111), FPU_FPSP);
+}
+
+
+//
+// fint (6888X, 68040FPSP, 68060)
+//
+int m_fint(WORD inst, WORD siz)
+{
+ if (am1 == AM_NONE)
+ // special case - fint fpx = fint fpx,fpx
+ a1reg = a0reg;
+
+ if (activefpu == FPU_68040)
+ warn("Instruction is emulated in 68040");
+
+ return gen_fpu(inst, siz, B8(00000001), FPU_NOWARN);
+}
+
+
+//
+// fintrz (6888X, 68040FPSP, 68060)
+//
+int m_fintrz(WORD inst, WORD siz)
+{
+ if (am1 == AM_NONE)
+ // special case - fintrz fpx = fintrz fpx,fpx
+ a1reg = a0reg;
+
+ if (activefpu == FPU_68040)
+ warn("Instruction is emulated in 68040");
+
+ return gen_fpu(inst, siz, B8(00000011), FPU_NOWARN);
+}
+
+
+//
+// flog10 (6888X, 68040FPSP, 68060FPSP)
+//
+int m_flog10(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00010101), FPU_FPSP);
+}
+
+
+//
+// flog2 (6888X, 68040FPSP, 68060FPSP)
+//
+int m_flog2(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00010110), FPU_FPSP);
+}
+
+
+//
+// flogn (6888X, 68040FPSP, 68060FPSP)
+//
+int m_flogn(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00010100), FPU_FPSP);
+}
+
+
+//
+// flognp1 (68040FPSP, 68060FPSP)
+//
+int m_flognp1(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(00000110), FPU_FPSP);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fmod (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fmod(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100001), FPU_FPSP);
+}
+
+
+//
+// fmove (6888X, 68040, 68060)
+//
+int m_fmove(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ // EA to register
+ if ((am0 == FREG) && (am1 < AM_USP))
+ {
+ // fpx->ea
+ // EA
+ inst |= am1 | a1reg;
+ D_word(inst);
+
+ // R/M
+ inst = 3 << 13;
+
+ // Source specifier
+ switch (siz)
+ {
+ case SIZB: inst |= (6 << 10); break;
+ case SIZW: inst |= (4 << 10); break;
+ case SIZL: inst |= (0 << 10); break;
+ case SIZN:
+ case SIZS: inst |= (1 << 10); break;
+ case SIZD: inst |= (5 << 10); break;
+ case SIZX: inst |= (2 << 10); break;
+ case SIZP: inst |= (3 << 10);
+ // In P size we have 2 cases: {#k} where k is immediate
+ // and {Dn} where Dn=Data register
+ if (bfparam1)
+ {
+ // Dn
+ inst |= 1 << 12;
+ inst |= bfval1 << 4;
+ }
+ else
+ {
+ // #k
+ if (bfval1 > 63 && bfval1 < -64)
+ return error("K-factor must be between -64 and 63");
+
+ inst |= bfval1 & 127;
+ }
+
+ break;
+ default:
+ return error("Something bad happened, possibly.");
+ break;
+ }
+
+ // Destination specifier
+ inst |= (a0reg << 7);
+
+ // Opmode
+ inst |= 0;
+
+ D_word(inst);
+ ea1gen(siz);
+ }
+ else if ((am0 < AM_USP) && (am1 == FREG))
+ {
+ // ea->fpx
+
+ // EA
+ inst |= am0 | a0reg;
+ D_word(inst);
+
+ // R/M
+ inst = 1 << 14;
+
+ // Source specifier
+ switch (siz)
+ {
+ case SIZB: inst |= (6 << 10); break;
+ case SIZW: inst |= (4 << 10); break;
+ case SIZL: inst |= (0 << 10); break;
+ case SIZN:
+ case SIZS: inst |= (1 << 10); break;
+ case SIZD: inst |= (5 << 10); break;
+ case SIZX: inst |= (2 << 10); break;
+ case SIZP: inst |= (3 << 10); break;
+ default:
+ return error("Something bad happened, possibly.");
+ break;
+ }
+
+ // Destination specifier
+ inst |= (a1reg << 7);
+
+ // Opmode
+ inst |= 0;
+
+ D_word(inst);
+ ea0gen(siz);
+ }
+ else if ((am0 == FREG) && (am1 == FREG))
+ {
+ // register-to-register
+ // Essentially ea to register with R/0=0
+
+ // EA
+ D_word(inst);
+
+ // R/M
+ inst = 0 << 14;
+
+ // Source specifier
+ if (siz != SIZX && siz != SIZN)
+ return error("Invalid size");
+
+ // Source register
+ inst |= (a0reg << 10);
+
+ // Destination register
+ inst |= (a1reg << 7);
+
+ D_word(inst);
+ }
+
+ return OK;
+}
+
+
+//
+// fmove (6888X, 68040, 68060)
+//
+int m_fmovescr(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ // Move Floating-Point System Control Register (FPCR)
+ // ea
+ // dr
+ // Register select
+ if ((am0 == FPSCR) && (am1 < AM_USP))
+ {
+ inst |= am1 | a1reg;
+ D_word(inst);
+ inst = (1 << 13) + (1 << 15);
+ inst |= a0reg;
+ D_word(inst);
+ ea1gen(siz);
+ return OK;
+ }
+ else if ((am1 == FPSCR) && (am0 < AM_USP))
+ {
+ inst |= am0 | a0reg;
+ D_word(inst);
+ inst = (0 << 13) + (1 << 15);
+ inst |= a1reg;
+ D_word(inst);
+ ea0gen(siz);
+ return OK;
+ }
+
+ return error("m_fmovescr says: wut?");
+}
+
+//
+// fsmove/fdmove (68040, 68060)
+//
+int m_fsmove(WORD inst, WORD siz)
+{
+ if (!(activefpu & (FPU_68040 | FPU_68060)))
+ return error("Unsupported in current FPU");
+
+ return error("Not implemented yet.");
+
+#if 0
+ if (activefpu == FPU_68040)
+ return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
+ else
+ return error("Unsupported in current FPU");
+#endif
+}
+
+
+int m_fdmove(WORD inst, WORD siz)
+{
+ if (!(activefpu & (FPU_68040 | FPU_68060)))
+ return error("Unsupported in current FPU");
+
+ return error("Not implemented yet.");
+
+#if 0
+ if (activefpu == FPU_68040)
+ return gen_fpu(inst, siz, B8(01100100), FPU_P_EMUL);
+ else
+ return error("Unsupported in current FPU");
+#endif
+}
+
+
+//
+// fmovecr (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fmovecr(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ D_word(inst);
+ inst = 0x5c00;
+ inst |= a1reg << 7;
+ inst |= a0exval;
+ D_word(inst);
+
+ if (activefpu == FPU_68040)
+ warn("Instruction is emulated in 68040/060");
+
+ return OK;
+}
+
+
+//
+// fmovem (6888X, 68040, 68060FPSP)
+//
+int m_fmovem(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ WORD regmask;
+ WORD datareg;
+
+ if (siz == SIZX || siz == SIZN)
+ {
+ if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ {
+ // fmovem.x <rlist>,ea
+ if (fpu_reglist_left(®mask) < 0)
+ return OK;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ if (amode(0) < 0)
+ return OK;
+
+ inst |= am0 | a0reg;
+
+ if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC)))
+ return error("invalid addressing mode");
+
+ D_word(inst);
+ inst = (1 << 15) | (1 << 14) | (1 << 13) | (0 << 11) | regmask;
+ D_word(inst);
+ ea0gen(siz);
+ return OK;
+ }
+ else if ((*tok >= KW_D0) && (*tok <= KW_D7))
+ {
+ // fmovem.x Dn,ea
+ datareg = (*tok++ & 7) << 10;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ if (amode(0) < 0)
+ return OK;
+
+ inst |= am0 | a0reg;
+
+ if (!(amsktab[am0] & (C_ALTCTRL | M_APREDEC)))
+ return error("invalid addressing mode");
+
+ // Quote from the 060 manual:
+ // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list."
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
+ D_word(inst);
+ inst = (1 << 15) | (1 << 14) | (1 << 13) | (1 << 11) | (datareg << 4);
+ D_word(inst);
+ ea0gen(siz);
+ return OK;
+ }
+ else
+ {
+ // fmovem.x ea,...
+ if (amode(0) < 0)
+ return OK;
+
+ inst |= am0 | a0reg;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ if ((*tok >= KW_FP0) && (*tok <= KW_FP7))
+ {
+ // fmovem.x ea,<rlist>
+ if (fpu_reglist_right(®mask) < 0)
+ return OK;
+
+ D_word(inst);
+ inst = (1 << 15) | (1 << 14) | (0 << 13) | (2 << 11) | regmask;
+ D_word(inst);
+ ea0gen(siz);
+ return OK;
+ }
+ else
+ {
+ // fmovem.x ea,Dn
+ datareg = (*tok++ & 7) << 10;
+
+ // Quote from the 060 manual:
+ // "[..] when the processor attempts an FMOVEM.X instruction using a dynamic register list."
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
+ D_word(inst);
+ inst = (1 << 15) | (1 << 14) | (0 << 13) | (3 << 11) | (datareg << 4);
+ D_word(inst);
+ ea0gen(siz);
+ return OK;
+ }
+ }
+ }
+ else if (siz == SIZL)
+ {
+ if ((*tok == KW_FPCR) || (*tok == KW_FPSR) || (*tok == KW_FPIAR))
+ {
+ // fmovem.l <rlist>,ea
+ regmask = (1 << 15) | (1 << 13);
+ int no_control_regs = 0;
+
+fmovem_loop_1:
+ if (*tok == KW_FPCR)
+ {
+ regmask |= (1 << 12);
+ tok++;
+ no_control_regs++;
+ goto fmovem_loop_1;
+ }
+
+ if (*tok == KW_FPSR)
+ {
+ regmask |= (1 << 11);
+ tok++;
+ no_control_regs++;
+ goto fmovem_loop_1;
+ }
+
+ if (*tok == KW_FPIAR)
+ {
+ regmask |= (1 << 10);
+ tok++;
+ no_control_regs++;
+ goto fmovem_loop_1;
+ }
+
+ if ((*tok == '/') || (*tok == '-'))
+ {
+ tok++;
+ goto fmovem_loop_1;
+ }
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ if (amode(0) < 0)
+ return OK;
+
+ // Quote from the 060 manual:
+ // "[..] when the processor attempts to execute an FMOVEM.L instruction with
+ // an immediate addressing mode to more than one floating - point
+ // control register (FPCR, FPSR, FPIAR)[..]"
+ if (activefpu == FPU_68060)
+ if (no_control_regs > 1 && am0 == IMMED)
+ warn("Instruction is emulated in 68060");
+
+ inst |= am0 | a0reg;
+ D_word(inst);
+ D_word(regmask);
+ ea0gen(siz);
+ }
+ else
+ {
+ // fmovem.l ea,<rlist>
+ if (amode(0) < 0)
+ return OK;
+
+ inst |= am0 | a0reg;
+
+ if (*tok++ != ',')
+ return error("missing comma");
+
+ regmask = (1 << 15) | (0 << 13);
+
+fmovem_loop_2:
+ if (*tok == KW_FPCR)
+ {
+ regmask |= (1 << 12);
+ tok++;
+ goto fmovem_loop_2;
+ }
+
+ if (*tok == KW_FPSR)
+ {
+ regmask |= (1 << 11);
+ tok++;
+ goto fmovem_loop_2;
+ }
+
+ if (*tok == KW_FPIAR)
+ {
+ regmask |= (1 << 10);
+ tok++;
+ goto fmovem_loop_2;
+ }
+
+ if ((*tok == '/') || (*tok == '-'))
+ {
+ tok++;
+ goto fmovem_loop_2;
+ }
+
+ if (*tok != EOL)
+ return error("extra (unexpected) text found");
+
+ inst |= am0 | a0reg;
+ D_word(inst);
+ D_word(regmask);
+ ea0gen(siz);
+ }
+ }
+ else
+ return error("bad size suffix");
+
+ return OK;
+}
+
+
+//
+// fmul (6888X, 68040, 68060)
+//
+int m_fmul(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100011), FPU_NOWARN);
+}
+
+
+//
+// fsmul (68040, 68060)
+//
+int m_fsmul(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100011), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fdmul (68040)
+//
+int m_fdmul(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01100111), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fneg (6888X, 68040, 68060)
+//
+int m_fneg(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ if (am1 == AM_NONE)
+ {
+ a1reg = a0reg;
+ return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
+ }
+
+ return gen_fpu(inst, siz, B8(00011010), FPU_NOWARN);
+}
+
+
+//
+// fsneg (68040, 68060)
+//
+int m_fsneg(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ {
+ if (am1 == AM_NONE)
+ {
+ a1reg = a0reg;
+ return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+ }
+
+ return gen_fpu(inst, siz, B8(01011010), FPU_NOWARN);
+ }
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fdneg (68040, 68060)
+//
+int m_fdneg(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ {
+ if (am1 == AM_NONE)
+ {
+ a1reg = a0reg;
+ return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ }
+
+ return gen_fpu(inst, siz, B8(01011110), FPU_NOWARN);
+ }
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fnop (6888X, 68040, 68060)
+//
+int m_fnop(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00000000), FPU_NOWARN);
+}
+
+
+//
+// frem (6888X, 68040FPSP, 68060FPSP)
+//
+int m_frem(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100101), FPU_FPSP);
+}
+
+
+//
+// fscale (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fscale(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100110), FPU_FPSP);
+}
+
+
+//
+// FScc (6888X, 68040, 68060), cpScc (68851, 68030), PScc (68851)
+// TODO: Add check for PScc to ensure 68020+68851 active
+// TODO: Add check for cpScc to ensure 68020+68851, 68030
+//
+int m_fscc(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ // We stash the 5 condition bits inside the opcode in 68ktab (bits 4-0),
+ // so we need to extract them first and fill in the clobbered bits.
+ WORD opcode = inst & 0x1F;
+ inst &= 0xFFE0;
+ inst |= am0 | a0reg;
+ D_word(inst);
+ ea0gen(siz);
+ D_word(opcode);
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+ return OK;
+}
+
+
+//
+// fsgldiv (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fsgldiv(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100100), FPU_FPSP);
+}
+
+
+//
+// fsglmul (6888X, 68040, 68060FPSP)
+//
+int m_fsglmul(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00100111), FPU_FPSP);
+}
+
+
+//
+// fsin (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fsin(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00001110), FPU_FPSP);
+}
+
+
+//
+// fsincos (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fsincos(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ // Swap a1reg, a2reg as a2reg should be stored in the bitfield gen_fpu
+ // generates
+ int temp;
+ temp = a2reg;
+ a2reg = a1reg;
+ a1reg = temp;
+
+ if (gen_fpu(inst, siz, B8(00110000), FPU_FPSP) == OK)
+ {
+ chptr[-1] |= a2reg;
+ return OK;
+ }
+
+ return ERROR;
+}
+
+
+//
+// fsinh (6888X, 68040FPSP, 68060FPSP)
+//
+int m_fsinh(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00000010), FPU_FPSP);
+}
+
+
+//
+// fsqrt (6888X, 68040, 68060)
+//
+int m_fsqrt(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00000100), FPU_NOWARN);
+}
+
+
+//
+// fsfsqrt (68040, 68060)
+//
+int m_fsfsqrt(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01000001), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fdfsqrt (68040, 68060)
+//
+int m_fdfsqrt(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01000101), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fsub (6888X, 68040, 68060)
+//
+int m_fsub(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00101000), FPU_NOWARN);
+}
+
+
+//
+// fsfsub (68040, 68060)
+//
+int m_fsfsub(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01101000), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// fdfsub (68040, 68060)
+//
+int m_fdsub(WORD inst, WORD siz)
+{
+ if (activefpu & (FPU_68040 | FPU_68060))
+ return gen_fpu(inst, siz, B8(01101100), FPU_NOWARN);
+
+ return error("Unsupported in current FPU");
+}
+
+
+//
+// ftan (6888X, 68040FPSP, 68060FPSP)
+//
+int m_ftan(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00001111), FPU_FPSP);
+}
+
+
+//
+// ftanh (6888X, 68040FPSP, 68060FPSP)
+//
+int m_ftanh(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00001001), FPU_FPSP);
+}
+
+
+//
+// ftentox (6888X, 68040FPSP, 68060FPSP)
+//
+int m_ftentox(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00010010), FPU_FPSP);
+}
+
+
+//
+// FTRAPcc (6888X, 68040, 68060FPSP)
+//
+int m_ftrapcc(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+
+ // We stash the 5 condition bits inside the opcode in 68ktab (bits 3-7),
+ // so we need to extract them first and fill in the clobbered bits.
+ WORD opcode = (inst >> 3) & 0x1F;
+ inst = (inst & 0xFF07) | (0xF << 3);
+
+ if (siz == SIZW)
+ {
+ inst |= 2;
+ D_word(inst);
+ D_word(opcode);
+ D_word(a0exval);
+ }
+ else if (siz == SIZL)
+ {
+ inst |= 3;
+ D_word(inst);
+ D_word(opcode);
+ D_long(a0exval);
+ }
+ else if (siz == SIZN)
+ {
+ inst |= 4;
+ D_word(inst);
+ D_word(opcode);
+ return OK;
+ }
+
+ if (activefpu == FPU_68060)
+ warn("Instruction is emulated in 68060");
+
+ return OK;
+}
+
+
+//
+// ftst (6888X, 68040, 68060)
+//
+int m_ftst(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00111010), FPU_NOWARN);
+}
+
+
+//
+// ftwotox (6888X, 68040FPSP, 68060FPSP)
+//
+int m_ftwotox(WORD inst, WORD siz)
+{
+ CHECKNOFPU;
+ return gen_fpu(inst, siz, B8(00010001), FPU_FPSP);
+}
+
+
+/////////////////////////////////
+// //
+// 68060 specific instructions //
+// //
+/////////////////////////////////
+
+
+//
+// lpstop (68060)
+//
+int m_lpstop(WORD inst, WORD siz)
+{
+ CHECKNO60;
+ D_word(B16(00000001, 11000000));
+
+ if (a0exattr & DEFINED)
+ {
+ D_word(a0exval);
+ }
+ else
+ {
+ AddFixup(FU_WORD, sloc, a0expr);
+ D_word(0);
+ }
+
+ return OK;
+}
+
+
+//
+// plpa (68060)
+//
+int m_plpa(WORD inst, WORD siz)
+{
+ CHECKNO60;
+ inst |= a0reg; // Install register
+ D_word(inst);
+
+ return OK;
+}
+
projects / rmac / blobdiff