Removed -w flag, added +o[n], ~o[n] switches to control individual optimisations...

[rmac] / eagen0.c

diff --git a/eagen0.c b/eagen0.c
index c69ac886efe96673908a6a77547f9cc31961f4d1..7ec6ccb0fcf28cdbca6156b8982e802bd0cc1f41 100644 (file)
--- a/eagen0.c
+++ b/eagen0.c
@@ -4,7 +4,7 @@
 //            Generated Code for eaN (Included twice by "eagen.c")
 // Copyright (C) 199x Landon Dyer, 2011 Reboot and Friends
 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
-// Source Utilised with the Kind Permission of Landon Dyer
+// Source utilised with the kind permission of Landon Dyer
 //
 
 int eaNgen(WORD siz)
@@ -19,7 +19,8 @@ int eaNgen(WORD siz)
 
        switch (amN)
        {
-       case DREG:                                            // "Do nothing" - they're in the opword
+       // "Do nothing" - they're in the opword
+       case DREG:
        case AREG:
        case AIND:
        case APOSTINC:
@@ -28,28 +29,62 @@ int eaNgen(WORD siz)
        case AM_CCR:
        case AM_SR:
        case AM_NONE:
-               break;                                             // This is a performance hit, though
-       case ADISP:                                           // expr(An)
+               // This is a performance hit, though
+               break;
+       case ADISP:
+               // expr(An)
                if (w)
-               {                                            // Just deposit it 
+               {
+                       // Just deposit it 
                        if (tdb)
                                rmark(cursect, sloc, tdb, MWORD, NULL);
 
+                       if ((v == 0) && optim_flags[OPT_INDIRECT_DISP])
+                       {
+                               // If expr is 0, size optimise the opcode.
+                               // Generally the lower 6 bits of the opcode
+                               // for expr(ax) are 101rrr where rrr=the
+                               // number of the register, then followed by
+                               // a word containing 'expr'. We need to change
+                               // that to 010rrr.
+                               if ((siz & 0x8000) == 0)
+                               {
+                                       chptr_opcode[0] &= ((0xFFC7 >> 8) & 255); // mask off bits
+                                       chptr_opcode[1] &= 0xFFC7 & 255;          // mask off bits
+                                       chptr_opcode[0] |= ((0x0010 >> 8) & 255); // slap in 010 bits
+                                       chptr_opcode[1] |= 0x0010 & 255;          // slap in 010 bits
+                               }
+                               else
+                               {
+                                       // Special case for move ea,ea:
+                                       // there are two ea fields there and
+                                       // we get a signal if it's the second ea field
+                                       // from m_ea - siz's 16th bit is set
+                                       chptr_opcode[0] &= ((0xFE3F >> 8) & 255); // mask off bits
+                                       chptr_opcode[1] &= 0xFE3F & 255;          // mask off bits
+                                       chptr_opcode[0] |= ((0x0080 >> 8) & 255); // slap in 010 bits
+                                       chptr_opcode[1] |= 0x0080 & 255;          // slap in 010 bits
+                               }
+                               return OK;
+                       }
+
                        if (v + 0x8000 >= 0x18000)
                                return error(range_error);
 
                        D_word(v);
                }
                else
-               {                                           // Arrange for fixup later on 
-                       fixup(FU_WORD|FU_SEXT, sloc, aNexpr);
+               {
+                       // Arrange for fixup later on 
+                       AddFixup(FU_WORD|FU_SEXT, sloc, aNexpr);
                        D_word(0);
                }
 
                break;
        case PCDISP:
                if (w)
-               {                                            // Just deposit it 
+               {
+                       // Just deposit it 
                        if ((aNexattr & TDB) == cursect)
                                v -= (VALUE)sloc;
                        else if ((aNexattr & TDB) != ABS)
@@ -61,19 +96,23 @@ int eaNgen(WORD siz)
                        D_word(v);
                }
                else
-               {                                           // Arrange for fixup later on 
-                       fixup(FU_WORD|FU_SEXT|FU_PCREL, sloc, aNexpr);
+               {
+                       // Arrange for fixup later on 
+                       AddFixup(FU_WORD|FU_SEXT|FU_PCREL, sloc, aNexpr);
                        D_word(0);
                }
 
                break;
        case AINDEXED:
-               w = (WORD)((aNixreg << 12) | aNixsiz);             // Compute ixreg and size+scale
+               // Compute ixreg and size+scale
+               w = (WORD)((aNixreg << 12) | aNixsiz);
 
                if (aNexattr & DEFINED)
-               {                           // Deposit a byte... 
+               {
+                       // Deposit a byte... 
                        if (tdb)
-                               return error(abs_error);                    // Can't mark bytes 
+                               // Can't mark bytes 
+                               return error(abs_error);
 
                        if (v + 0x80 >= 0x180)
                                return error(range_error);
@@ -82,17 +121,20 @@ int eaNgen(WORD siz)
                        D_word(w);
                }
                else
-               {                                           // Fixup the byte later
-                       fixup(FU_BYTE|FU_SEXT, sloc+1, aNexpr);
+               {
+                       // Fixup the byte later
+                       AddFixup(FU_BYTE|FU_SEXT, sloc+1, aNexpr);
                        D_word(w);
                }
 
                break;
        case PCINDEXED:
-               w = (WORD)((aNixreg << 12) | aNixsiz);             // Compute ixreg and size+scale
+               // Compute ixreg and size+scale
+               w = (WORD)((aNixreg << 12) | aNixsiz);
 
                if (aNexattr & DEFINED)
-               {                           // Deposit a byte... 
+               {
+                       // Deposit a byte... 
                        if ((aNexattr & TDB) == cursect) 
                                v -= (VALUE)sloc;
                        else if ((aNexattr & TDB) != ABS)
@@ -101,12 +143,13 @@ int eaNgen(WORD siz)
                        if (v + 0x80 >= 0x100)
                                return error(range_error);
 
-                       w |= v & 0xff;
+                       w |= v & 0xFF;
                        D_word(w);
                }
                else
-               {                                           // Fixup the byte later 
-                       fixup(FU_WBYTE|FU_SEXT|FU_PCREL, sloc, aNexpr);
+               {
+                       // Fixup the byte later 
+                       AddFixup(FU_WBYTE|FU_SEXT|FU_PCREL, sloc, aNexpr);
                        D_word(w);
                }
 
@@ -127,7 +170,7 @@ int eaNgen(WORD siz)
                        }
                        else
                        {
-                               fixup(FU_BYTE|FU_SEXT, sloc+1, aNexpr);
+                               AddFixup(FU_BYTE|FU_SEXT, sloc+1, aNexpr);
                                D_word(0);
                        }
 
@@ -146,7 +189,7 @@ int eaNgen(WORD siz)
                        }
                        else
                        {
-                               fixup(FU_WORD|FU_SEXT, sloc, aNexpr);
+                               AddFixup(FU_WORD|FU_SEXT, sloc, aNexpr);
                                D_word(0);
                        }
 
@@ -161,13 +204,14 @@ int eaNgen(WORD siz)
                        }
                        else
                        {
-                               fixup(FU_LONG, sloc, aNexpr);
+                               AddFixup(FU_LONG, sloc, aNexpr);
                                D_long(0);
                        }
 
                        break;
                default:
-                       interror(1);                                 // IMMED size problem
+                       // IMMED size problem
+                       interror(1);
                }
 
                break;
@@ -184,7 +228,7 @@ int eaNgen(WORD siz)
                }
                else
                {
-                       fixup(FU_WORD|FU_SEXT, sloc, aNexpr);
+                       AddFixup(FU_WORD|FU_SEXT, sloc, aNexpr);
                        D_word(0);
                }
 
@@ -199,7 +243,7 @@ int eaNgen(WORD siz)
                }
                else
                {
-                       fixup(FU_LONG, sloc, aNexpr);
+                       AddFixup(FU_LONG, sloc, aNexpr);
                        D_long(0);
                }
 
@@ -212,7 +256,8 @@ int eaNgen(WORD siz)
        case PCMPRE:
                return error("unsupported 68020 addressing mode");
        default:
-               interror(3);                                       // Bad addressing mode in ea gen 
+               // Bad addressing mode in ea gen 
+               interror(3);
        }
 
        return OK;
@@ -226,3 +271,4 @@ int eaNgen(WORD siz)
 #undef aNexpr
 #undef aNixreg
 #undef aNixsiz
+