2 // RMAC - Reboot's Macro Assembler for all Atari computers
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011-2018 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
19 #define DEF_MR // Declare keyword values
20 #include "risckw.h" // Incl. generated risc keywords
22 #define DEF_KW // Declare keyword values
23 #include "kwtab.h" // Incl. generated keyword tables & defs
25 #define MAXINTERNCC 26 // Maximum internal condition codes
28 unsigned altbankok = 0; // Ok to use alternate register bank
29 unsigned orgactive = 0; // RISC/6502 org directive active
30 unsigned orgaddr = 0; // Org'd address
31 unsigned orgwarning = 0; // Has an ORG warning been issued
32 int lastOpcode = -1; // Last RISC opcode assembled
33 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
35 static const char reg_err[] = "missing register R0...R31";
37 // Jaguar jump condition names
38 static const char condname[MAXINTERNCC][5] = {
39 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
40 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
44 // Jaguar jump condition numbers
45 static const char condnumber[] = {
46 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
47 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
50 // Opcode Specific Data
52 uint16_t state; // Opcode Name (unused)
53 uint16_t type; // Opcode Type
54 uint16_t param; // Opcode Parameter
57 static const struct opcoderecord roptbl[] = {
58 { MR_ADD, RI_TWO, 0 },
59 { MR_ADDC, RI_TWO, 1 },
60 { MR_ADDQ, RI_NUM_32, 2 },
61 { MR_ADDQT, RI_NUM_32, 3 },
62 { MR_SUB, RI_TWO, 4 },
63 { MR_SUBC, RI_TWO, 5 },
64 { MR_SUBQ, RI_NUM_32, 6 },
65 { MR_SUBQT, RI_NUM_32, 7 },
66 { MR_NEG, RI_ONE, 8 },
67 { MR_AND, RI_TWO, 9 },
68 { MR_OR, RI_TWO, 10 },
69 { MR_XOR, RI_TWO, 11 },
70 { MR_NOT, RI_ONE, 12 },
71 { MR_BTST, RI_NUM_31, 13 },
72 { MR_BSET, RI_NUM_31, 14 },
73 { MR_BCLR, RI_NUM_31, 15 },
74 { MR_MULT, RI_TWO, 16 },
75 { MR_IMULT, RI_TWO, 17 },
76 { MR_IMULTN, RI_TWO, 18 },
77 { MR_RESMAC, RI_ONE, 19 },
78 { MR_IMACN, RI_TWO, 20 },
79 { MR_DIV, RI_TWO, 21 },
80 { MR_ABS, RI_ONE, 22 },
81 { MR_SH, RI_TWO, 23 },
82 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
83 { MR_SHRQ, RI_NUM_32, 25 },
84 { MR_SHA, RI_TWO, 26 },
85 { MR_SHARQ, RI_NUM_32, 27 },
86 { MR_ROR, RI_TWO, 28 },
87 { MR_RORQ, RI_NUM_32, 29 },
88 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
89 { MR_CMP, RI_TWO, 30 },
90 { MR_CMPQ, RI_NUM_15, 31 },
91 { MR_SAT8, RI_ONE, 32 + GPUONLY },
92 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
93 { MR_SAT16, RI_ONE, 33 + GPUONLY },
94 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
95 { MR_MOVEQ, RI_NUM_31, 35 },
96 { MR_MOVETA, RI_TWO, 36 },
97 { MR_MOVEFA, RI_TWO, 37 },
98 { MR_MOVEI, RI_MOVEI, 38 },
99 { MR_LOADB, RI_LOADN, 39 },
100 { MR_LOADW, RI_LOADN, 40 },
101 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
102 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
103 { MR_STOREB, RI_STOREN, 45 },
104 { MR_STOREW, RI_STOREN, 46 },
105 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
106 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
107 { MR_JUMP, RI_JUMP, 52 },
108 { MR_JR, RI_JR, 53 },
109 { MR_MMULT, RI_TWO, 54 },
110 { MR_MTOI, RI_TWO, 55 },
111 { MR_NORMI, RI_TWO, 56 },
112 { MR_NOP, RI_NONE, 57 },
113 { MR_SAT24, RI_ONE, 62 },
114 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
115 { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
116 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
117 { MR_MOVE, RI_MOVE, 0 },
118 { MR_LOAD, RI_LOAD, 0 },
119 { MR_STORE, RI_STORE, 0 }
124 #define MALF_LPAREN 2
125 #define MALF_RPAREN 3
127 static const char malform1[] = "missing '#'";
128 static const char malform2[] = "bad expression";
129 static const char malform3[] = "missing ')'";
130 static const char malform4[] = "missing '('";
132 static const char * malformErr[] = {
133 malform1, malform2, malform3, malform4
138 // Convert a string to uppercase
140 static void strtoupper(char * s)
148 // Function to return "malformed expression" error
149 // This is done mainly to remove a bunch of GOTO statements in the parser
151 static inline int MalformedOpcode(int signal)
153 return error("Malformed opcode, %s", malformErr[signal]);
158 // Function to return "Illegal Indexed Register" error
159 // Anyone trying to index something other than R14 or R15
161 static inline int IllegalIndexedRegister(int reg)
163 return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0);
168 // Function to return "Illegal Indexed Register" error for EQUR scenarios
169 // Trying to use register value within EQUR that isn't 14 or 15
171 static inline int IllegalIndexedRegisterEqur(SYM * sy)
173 return error("Attempted index reference with non-indexable register within EQUR (%s = r%d)", sy->sname, sy->svalue);
178 // Build up & deposit RISC instruction word
180 static void DepositRISCInstructionWord(uint16_t opcode, int reg1, int reg2)
182 // Check for absolute address setting
183 if (!orgwarning && !orgactive)
185 warn("RISC code generated with no origin defined");
189 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
195 // Evaluate the RISC register from the token stream. Passed in value is the
196 // FIXUP attribute to use if the expression comes back as undefined.
198 static int EvaluateRegisterFromTokenStream(uint32_t attr)
200 uint64_t eval; // Expression value
201 WORD eattr; // Expression attributes
202 SYM * esym; // External symbol involved in expr.
203 TOKEN r_expr[EXPRSIZE]; // Expression token list
205 // Evaluate what's in the global "tok" buffer
206 if (expr(r_expr, &eval, &eattr, &esym) != OK)
209 if (!(eattr & DEFINED))
211 AddFixup(FU_WORD | attr, sloc, r_expr);
215 // If we got a register in range (0-31), return it
219 // Otherwise, it's out of range & we flag an error
220 return error(reg_err);
225 // Do RISC code generation
227 int GenerateRISCCode(int state)
229 int reg1; // Register 1
230 int reg2; // Register 2
231 int val = 0; // Constructed value
238 int indexed; // Indexed register flag
240 uint64_t eval; // Expression value
241 uint16_t eattr; // Expression attributes
242 SYM * esym; // External symbol involved in expr.
243 TOKEN r_expr[EXPRSIZE]; // Expression token list
245 // Get opcode parameter and type
246 uint16_t parm = roptbl[state - 3000].param;
247 uint16_t type = roptbl[state - 3000].type;
248 riscImmTokenSeen = 0; // Set to "token not seen yet"
250 // Detect whether the opcode parmeter passed determines that the opcode is
251 // specific to only one of the RISC processors and ensure it is legal in
252 // the current code section. If not then show error and return.
253 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
254 return error("Opcode is not valid in this code section");
256 // Process RISC opcode
259 // No operand instructions
262 DepositRISCInstructionWord(parm, 0, 0);
265 // Single operand instructions (Rd)
266 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
269 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
271 DepositRISCInstructionWord(parm, parm >> 6, reg2);
274 // Two operand instructions (Rs,Rd)
275 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
276 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
279 altbankok = 1; // MOVEFA
281 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
285 altbankok = 1; // MOVETA
287 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
289 DepositRISCInstructionWord(parm, reg1, reg2);
292 // Numeric operand (n,Rd) where n = -16..+15
296 // Numeric operand (n,Rd) where n = 0..31
297 // BCLR, BSET, BTST, MOVEQ
300 // Numeric operand (n,Rd) where n = 1..32
301 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
307 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
311 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
314 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
322 return MalformedOpcode(MALF_NUM);
325 riscImmTokenSeen = 1;
327 if (expr(r_expr, &eval, &eattr, &esym) != OK)
328 return MalformedOpcode(MALF_EXPR);
330 if (!(eattr & DEFINED))
332 AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
337 if (((int)eval < reg1) || ((int)eval > reg2))
338 return error("constant out of range (%d to %d", reg1, reg2);
341 reg1 = 32 - (int)eval;
342 else if (type == RI_NUM_32)
343 reg1 = (reg1 == 32 ? 0 : (int)eval);
349 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
351 DepositRISCInstructionWord(parm, reg1, reg2);
354 // Move Immediate--n,Rn--n in Second Word
357 return MalformedOpcode(MALF_NUM);
360 riscImmTokenSeen = 1;
362 // Check for equated register after # and return error if so
365 sy = lookup(string[tok[1]], LABEL, 0);
367 if (sy && (sy->sattre & EQUATEDREG))
368 return error("equated register in 1st operand of MOVEI instruction");
371 if (expr(r_expr, &eval, &eattr, &esym) != OK)
372 return MalformedOpcode(MALF_EXPR);
374 if ((lastOpcode == RI_JUMP) || (lastOpcode == RI_JR))
378 // User doesn't care, emit a NOP to fix
379 DepositRISCInstructionWord(57, 0, 0);
380 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
383 warn("MOVEI immediately follows JUMP");
386 if (!(eattr & DEFINED))
388 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
394 MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
398 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
401 DepositRISCInstructionWord(parm, 0, reg2);
402 val = WORDSWAP32(eval);
417 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
421 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
423 DepositRISCInstructionWord(parm, reg1, reg2);
426 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
432 return MalformedOpcode(MALF_LPAREN);
436 if ((tok[1] == '+') || (tok[1] == '-'))
438 // Trying to make indexed call
439 if ((*tok == KW_R14) || (*tok == KW_R15))
440 indexed = (*tok - KW_R0);
442 return IllegalIndexedRegister(*tok);
447 sy = lookup(string[tok[1]], LABEL, 0);
455 if (sy->sattre & EQUATEDREG)
457 if ((tok[2] == '+') || (tok[2] == '-'))
459 if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) {
460 indexed = (sy->svalue & 0x1F);
464 return IllegalIndexedRegisterEqur(sy);
471 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
481 parm = (WORD)(reg1 - 14 + 58);
484 if ((*tok >= KW_R0) && (*tok <= KW_R31))
489 sy = lookup(string[tok[1]], LABEL, 0);
497 if (sy->sattre & EQUATEDREG)
503 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
507 if (expr(r_expr, &eval, &eattr, &esym) != OK)
508 return MalformedOpcode(MALF_EXPR);
510 if (!(eattr & DEFINED))
511 return error("constant expected after '+'");
517 reg1 = 14 + (parm - 58);
519 warn("NULL offset in LOAD ignored");
523 if ((reg1 < 1) || (reg1 > 32))
524 return error("constant in LOAD out of range (1-32)");
529 parm = (WORD)(parm - 58 + 43);
535 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
540 return MalformedOpcode(MALF_RPAREN);
544 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
546 DepositRISCInstructionWord(parm, reg1, reg2);
549 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
552 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
556 return MalformedOpcode(MALF_LPAREN);
561 if (((*tok == KW_R14) || (*tok == KW_R15)) && (tok[1] != ')'))
562 indexed = *tok - KW_R0;
566 sy = lookup(string[tok[1]], LABEL, 0);
574 if (sy->sattre & EQUATEDREG)
576 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
579 indexed = (sy->svalue & 0x1F);
587 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
597 parm = (WORD)(reg2 - 14 + 60);
600 if ((*tok >= KW_R0) && (*tok <= KW_R31))
605 sy = lookup(string[tok[1]], LABEL, 0);
613 if (sy->sattre & EQUATEDREG)
619 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
623 if (expr(r_expr, &eval, &eattr, &esym) != OK)
624 return MalformedOpcode(MALF_EXPR);
626 if (!(eattr & DEFINED))
628 AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
637 reg2 = 14 + (parm - 60);
639 warn("NULL offset in STORE ignored");
643 if ((reg2 < 1) || (reg2 > 32))
644 return error("constant in STORE out of range (1-32)");
649 parm = (WORD)(parm - 60 + 49);
656 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
661 return MalformedOpcode(MALF_RPAREN);
665 DepositRISCInstructionWord(parm, reg2, reg1);
668 // LOADB/LOADP/LOADW (Rn),Rn
671 return MalformedOpcode(MALF_LPAREN);
674 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
677 return MalformedOpcode(MALF_RPAREN);
681 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
683 DepositRISCInstructionWord(parm, reg1, reg2);
686 // STOREB/STOREP/STOREW Rn,(Rn)
688 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
692 return MalformedOpcode(MALF_LPAREN);
695 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
698 return MalformedOpcode(MALF_RPAREN);
702 DepositRISCInstructionWord(parm, reg2, reg1);
705 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
708 // Jump Absolute - cc,(Rs) - reg2=cc
710 // Check to see if there is a comma in the token string. If not then
711 // the JR or JUMP should default to 0, Jump Always
714 for(t=tok; *t!=EOL; t++)
727 // CC using a constant number (O_o)
734 else if (*tok == SYMBOL)
737 strcpy(scratch, string[tok[1]]);
740 for(i=0; i<MAXINTERNCC; i++)
742 // Look for the condition code & break if found
743 if (strcmp(condname[i], scratch) == 0)
750 // Standard CC was not found, look for an equated one
753 ccsym = lookup(string[tok[1]], LABEL, 0);
755 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
756 val = (int)ccsym->svalue;
758 return error("unknown condition code");
764 else if (*tok == '(')
766 // Set CC to "Jump Always"
772 // Set CC to "Jump Always"
776 if ((val < 0) || (val > 31))
777 return error("condition constant out of range");
779 // Store condition code
785 if (expr(r_expr, &eval, &eattr, &esym) != OK)
786 return MalformedOpcode(MALF_EXPR);
788 if (!(eattr & DEFINED))
790 AddFixup(FU_WORD | FU_JR, sloc, r_expr);
795 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
797 if ((reg2 < -16) || (reg2 > 15))
798 error("PC relative overflow in JR (outside of -16 to 15)");
805 return MalformedOpcode(MALF_LPAREN);
808 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
811 return MalformedOpcode(MALF_RPAREN);
817 DepositRISCInstructionWord(parm, reg2, reg1);
820 // We should never get here. If we do, somebody done fucked up. :-D
822 return error("Unknown RISC opcode type");