2 // RMAC - Reboot's Macro Assembler for all Atari computers
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011-2017 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
19 #define DEF_MR // Declare keyword values
20 #include "risckw.h" // Incl. generated risc keywords
22 #define DEF_KW // Declare keyword values
23 #include "kwtab.h" // Incl. generated keyword tables & defs
26 unsigned altbankok = 0; // Ok to use alternate register bank
27 unsigned orgactive = 0; // RISC/6502 org directive active
28 unsigned orgaddr = 0; // Org'd address
29 unsigned orgwarning = 0; // Has an ORG warning been issued
30 int lastOpcode = -1; // Last RISC opcode assembled
31 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
33 const char reg_err[] = "missing register R0...R31";
35 // Jaguar jump condition names
36 const char condname[MAXINTERNCC][5] = {
37 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
38 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
42 // Jaguar jump condition numbers
43 const char condnumber[] = {
44 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
45 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
48 const struct opcoderecord roptbl[] = {
49 { MR_ADD, RI_TWO, 0 },
50 { MR_ADDC, RI_TWO, 1 },
51 { MR_ADDQ, RI_NUM_32, 2 },
52 { MR_ADDQT, RI_NUM_32, 3 },
53 { MR_SUB, RI_TWO, 4 },
54 { MR_SUBC, RI_TWO, 5 },
55 { MR_SUBQ, RI_NUM_32, 6 },
56 { MR_SUBQT, RI_NUM_32, 7 },
57 { MR_NEG, RI_ONE, 8 },
58 { MR_AND, RI_TWO, 9 },
59 { MR_OR, RI_TWO, 10 },
60 { MR_XOR, RI_TWO, 11 },
61 { MR_NOT, RI_ONE, 12 },
62 { MR_BTST, RI_NUM_31, 13 },
63 { MR_BSET, RI_NUM_31, 14 },
64 { MR_BCLR, RI_NUM_31, 15 },
65 { MR_MULT, RI_TWO, 16 },
66 { MR_IMULT, RI_TWO, 17 },
67 { MR_IMULTN, RI_TWO, 18 },
68 { MR_RESMAC, RI_ONE, 19 },
69 { MR_IMACN, RI_TWO, 20 },
70 { MR_DIV, RI_TWO, 21 },
71 { MR_ABS, RI_ONE, 22 },
72 { MR_SH, RI_TWO, 23 },
73 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
74 { MR_SHRQ, RI_NUM_32, 25 },
75 { MR_SHA, RI_TWO, 26 },
76 { MR_SHARQ, RI_NUM_32, 27 },
77 { MR_ROR, RI_TWO, 28 },
78 { MR_RORQ, RI_NUM_32, 29 },
79 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
80 { MR_CMP, RI_TWO, 30 },
81 { MR_CMPQ, RI_NUM_15, 31 },
82 { MR_SAT8, RI_ONE, 32 + GPUONLY },
83 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
84 { MR_SAT16, RI_ONE, 33 + GPUONLY },
85 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
86 { MR_MOVEQ, RI_NUM_31, 35 },
87 { MR_MOVETA, RI_TWO, 36 },
88 { MR_MOVEFA, RI_TWO, 37 },
89 { MR_MOVEI, RI_MOVEI, 38 },
90 { MR_LOADB, RI_LOADN, 39 },
91 { MR_LOADW, RI_LOADN, 40 },
92 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
93 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
94 { MR_STOREB, RI_STOREN, 45 },
95 { MR_STOREW, RI_STOREN, 46 },
96 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
97 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
98 { MR_JUMP, RI_JUMP, 52 },
100 { MR_MMULT, RI_TWO, 54 },
101 { MR_MTOI, RI_TWO, 55 },
102 { MR_NORMI, RI_TWO, 56 },
103 { MR_NOP, RI_NONE, 57 },
104 { MR_SAT24, RI_ONE, 62 },
105 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
106 { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
107 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
108 { MR_MOVE, RI_MOVE, 0 },
109 { MR_LOAD, RI_LOAD, 0 },
110 { MR_STORE, RI_STORE, 0 }
115 // Convert a string to uppercase
117 void strtoupper(char * s)
125 // Function to return "malformed expression" error
126 // This is done mainly to remove a bunch of GOTO statements in the parser
128 static inline int MalformedOpcode(int signal)
130 return error("Malformed opcode [internal $%02X]", signal);
135 // Function to return "Illegal Indexed Register" error
136 // Anyone trying to index something other than R14 or R15
138 static inline int IllegalIndexedRegister(int reg)
140 return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0);
145 // Function to return "Illegal Indexed Register" error for EQUR scenarios
146 // Trying to use register value within EQUR that isn't 14 or 15
148 static inline int IllegalIndexedRegisterEqur(SYM * sy)
150 return error("Attempted index reference with non-indexable register within EQUR (%s = r%d)", sy->sname, sy->svalue);
155 // Build RISC instruction word
157 void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
159 // Check for absolute address setting
160 if (!orgwarning && !orgactive)
162 warn("RISC code generated with no origin defined");
166 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
168 //printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
173 // Get a RISC register
175 int GetRegister(WORD rattr)
177 uint64_t eval; // Expression value
178 WORD eattr; // Expression attributes
179 SYM * esym; // External symbol involved in expr.
180 TOKEN r_expr[EXPRSIZE]; // Expression token list
182 // Evaluate what's in the global "tok" buffer
183 if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK)
186 if ((challoc - ch_size) < 4)
189 if (!(eattr & DEFINED))
191 AddFixup((WORD)(FU_WORD | rattr), sloc, (TOKENPTR)r_expr);
195 // If we got a register in range (0-31), return it
196 if ((eval >= 0) && (eval <= 31))
199 // Otherwise, it's out of range & we flag an error
200 return error(reg_err);
205 // Do RISC code generation
207 int GenerateRISCCode(int state)
209 int reg1; // Register 1
210 int reg2; // Register 2
211 int val = 0; // Constructed value
218 int indexed; // Indexed register flag
220 uint64_t eval; // Expression value
221 WORD eattr; // Expression attributes
222 SYM * esym; // External symbol involved in expr.
223 TOKEN r_expr[EXPRSIZE]; // Expression token list
225 // Get opcode parameter and type
226 unsigned short parm = (WORD)(roptbl[state - 3000].parm);
227 unsigned type = roptbl[state - 3000].typ;
228 riscImmTokenSeen = 0; // Set to "token not seen yet"
230 // Detect whether the opcode parmeter passed determines that the opcode is
231 // specific to only one of the RISC processors and ensure it is legal in
232 // the current code section. If not then show error and return.
233 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
234 return error("Opcode is not valid in this code section");
236 // Process RISC opcode
239 // No operand instructions
242 BuildRISCIntructionWord(parm, 0, 0);
245 // Single operand instructions (Rd)
246 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
249 reg2 = GetRegister(FU_REGTWO);
251 BuildRISCIntructionWord(parm, parm >> 6, reg2);
254 // Two operand instructions (Rs,Rd)
255 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
256 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
259 altbankok = 1; // MOVEFA
261 reg1 = GetRegister(FU_REGONE);
265 altbankok = 1; // MOVETA
267 reg2 = GetRegister(FU_REGTWO);
269 BuildRISCIntructionWord(parm, reg1, reg2);
272 // Numeric operand (n,Rd) where n = -16..+15
276 // Numeric operand (n,Rd) where n = 0..31
277 // BCLR, BSET, BTST, MOVEQ
280 // Numeric operand (n,Rd) where n = 1..32
281 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
287 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
291 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
294 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
302 return MalformedOpcode(0x01);
305 riscImmTokenSeen = 1;
307 if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK)
308 return MalformedOpcode(0x02);
310 if ((challoc - ch_size) < 4)
313 if (!(eattr & DEFINED))
315 AddFixup((WORD)(FU_WORD | attrflg), sloc, (TOKENPTR)r_expr);
320 if ((int)eval < reg1 || (int)eval > reg2)
321 return error("constant out of range");
324 reg1 = 32 - (int)eval;
325 else if (type == RI_NUM_32)
326 reg1 = (reg1 == 32 ? 0 : (int)eval);
332 reg2 = GetRegister(FU_REGTWO);
334 BuildRISCIntructionWord(parm, reg1, reg2);
337 // Move Immediate--n,Rn--n in Second Word
340 return MalformedOpcode(0x03);
343 riscImmTokenSeen = 1;
345 // Check for equated register after # and return error if so
346 if (*tok.u32 == SYMBOL)
348 sy = lookup(string[tok.u32[1]], LABEL, 0);
350 if (sy && (sy->sattre & EQUATEDREG))
351 return error("equated register in 1st operand of MOVEI instruction");
354 if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK)
355 return MalformedOpcode(0x04);
357 if (lastOpcode == RI_JUMP || lastOpcode == RI_JR)
361 // User doesn't care, emit a NOP to fix
362 BuildRISCIntructionWord(57, 0, 0);
363 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
366 warn("MOVEI immediately follows JUMP");
369 if ((challoc - ch_size) < 4)
372 if (!(eattr & DEFINED))
374 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, (TOKENPTR)r_expr);
381 //printf("RISCASM: Doing MarkRelocatable for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
382 MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
386 // val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000);
387 val = WORDSWAP32(eval);
389 reg2 = GetRegister(FU_REGTWO);
391 D_word((((parm & 0x3F) << 10) + reg2));
397 if (*tok.u32 == KW_PC)
406 reg1 = GetRegister(FU_REGONE);
410 reg2 = GetRegister(FU_REGTWO);
412 BuildRISCIntructionWord(parm, reg1, reg2);
415 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
421 return MalformedOpcode(0x05);
425 if ((*(tok.u32 + 1) == '+') || (*(tok.u32 + 1) == '-')) {
426 // Trying to make indexed call
427 if ((*tok.u32 == KW_R14 || *tok.u32 == KW_R15)) {
428 indexed = (*tok.u32 - KW_R0);
430 return IllegalIndexedRegister(*tok.u32);
434 if (*tok.u32 == SYMBOL)
436 // sy = lookup((char *)tok.u32[1], LABEL, 0);
437 sy = lookup(string[tok.u32[1]], LABEL, 0);
445 if (sy->sattre & EQUATEDREG)
447 if ((*(tok.u32 + 2) == '+') || (*(tok.u32 + 2) == '-')) {
448 if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) {
449 indexed = (sy->svalue & 0x1F);
452 return IllegalIndexedRegisterEqur(sy);
460 reg1 = GetRegister(FU_REGONE);
470 parm = (WORD)(reg1 - 14 + 58);
473 if (*tok.u32 >= KW_R0 && *tok.u32 <= KW_R31)
476 if (*tok.u32 == SYMBOL)
478 // sy = lookup((char *)tok.u32[1], LABEL, 0);
479 sy = lookup(string[tok.u32[1]], LABEL, 0);
487 if (sy->sattre & EQUATEDREG)
493 reg1 = GetRegister(FU_REGONE);
497 if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK)
498 return MalformedOpcode(0x06);
500 if ((challoc - ch_size) < 4)
503 if (!(eattr & DEFINED))
504 return error("constant expected after '+'");
510 reg1 = 14 + (parm - 58);
512 warn("NULL offset in LOAD ignored");
516 if (reg1 < 1 || reg1 > 32)
517 return error("constant in LOAD out of range");
522 parm = (WORD)(parm - 58 + 43);
528 reg1 = GetRegister(FU_REGONE);
533 return MalformedOpcode(0x07);
537 reg2 = GetRegister(FU_REGTWO);
539 BuildRISCIntructionWord(parm, reg1, reg2);
542 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
545 reg1 = GetRegister(FU_REGONE);
549 return MalformedOpcode(0x08);
554 if ((*tok.u32 == KW_R14 || *tok.u32 == KW_R15) && (*(tok.u32 + 1) != ')'))
555 indexed = (*tok.u32 - KW_R0);
557 if (*tok.u32 == SYMBOL)
559 sy = lookup(string[tok.u32[1]], LABEL, 0);
567 if (sy->sattre & EQUATEDREG)
569 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
570 && (*(tok.u32 + 2) != ')'))
572 indexed = (sy->svalue & 0x1F);
580 reg2 = GetRegister(FU_REGTWO);
590 parm = (WORD)(reg2 - 14 + 60);
593 if (*tok.u32 >= KW_R0 && *tok.u32 <= KW_R31)
596 if (*tok.u32 == SYMBOL)
598 sy = lookup(string[tok.u32[1]], LABEL, 0);
606 if (sy->sattre & EQUATEDREG)
612 reg2 = GetRegister(FU_REGTWO);
616 if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK)
617 return MalformedOpcode(0x09);
619 if ((challoc - ch_size) < 4)
622 if (!(eattr & DEFINED))
624 AddFixup(FU_WORD | FU_REGTWO, sloc, (TOKENPTR)r_expr);
633 reg2 = 14 + (parm - 60);
635 warn("NULL offset in STORE ignored");
639 if (reg2 < 1 || reg2 > 32)
640 return error("constant in STORE out of range");
645 parm = (WORD)(parm - 60 + 49);
652 reg2 = GetRegister(FU_REGTWO);
657 return MalformedOpcode(0x0A);
661 BuildRISCIntructionWord(parm, reg2, reg1);
664 // LOADB/LOADP/LOADW (Rn),Rn
667 return MalformedOpcode(0x0B);
670 reg1 = GetRegister(FU_REGONE);
673 return MalformedOpcode(0x0C);
677 reg2 = GetRegister(FU_REGTWO);
679 BuildRISCIntructionWord(parm, reg1, reg2);
682 // STOREB/STOREP/STOREW Rn,(Rn)
684 reg1 = GetRegister(FU_REGONE);
688 return MalformedOpcode(0x0D);
691 reg2 = GetRegister(FU_REGTWO);
694 return MalformedOpcode(0x0E);
698 BuildRISCIntructionWord(parm, reg2, reg1);
701 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
704 // Jump Absolute - cc,(Rs) - reg2=cc
706 // Check to see if there is a comma in the token string. If not then
707 // the JR or JUMP should default to 0, Jump Always
710 for(t=tok.u32; *t!=EOL; t++)
721 if (*tok.u32 == CONST)
723 // CC using a constant number
725 uint64_t *tok64 = (uint64_t *)tok.u32;
727 tok.u32 = (uint32_t *)tok64;
730 else if (*tok.u32 == SYMBOL)
733 // strcpy(scratch, (char *)tok.u32[1]);
734 strcpy(scratch, string[tok.u32[1]]);
737 for(i=0; i<MAXINTERNCC; i++)
739 // Look for the condition code & break if found
740 if (strcmp(condname[i], scratch) == 0)
747 // Standard CC was not found, look for an equated one
750 // ccsym = lookup((char *)tok.u32[1], LABEL, 0);
751 ccsym = lookup(string[tok.u32[1]], LABEL, 0);
753 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
756 return error("unknown condition code");
762 else if (*tok.u32 == '(')
764 // Set CC to "Jump Always"
770 // Set CC to "Jump Always"
774 if (val < 0 || val > 31)
775 return error("condition constant out of range");
777 // Store condition code
783 if (expr((TOKENPTR)r_expr, &eval, &eattr, &esym) != OK)
784 return MalformedOpcode(0x0F);
786 if ((challoc - ch_size) < 4)
789 if (!(eattr & DEFINED))
791 AddFixup(FU_WORD | FU_JR, sloc, (TOKENPTR)r_expr);
796 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
798 if ((reg2 < -16) || (reg2 > 15))
799 error("PC relative overflow (outside of -16 to 15)");
802 BuildRISCIntructionWord(parm, reg2, reg1);
808 return MalformedOpcode(0x10);
811 reg2 = GetRegister(FU_REGTWO);
814 return MalformedOpcode(0x11);
818 BuildRISCIntructionWord(parm, reg2, reg1);
823 // Should never get here :-D
825 return error("Unknown RISC opcode type");