2 // RMAC - Reboot's Macro Assembler for the Atari Jaguar Console System
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011 - 2017 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
18 #define DEF_MR // Declare keyword values
19 #include "risckw.h" // Incl. generated risc keywords
21 #define DEF_KW // Declare keyword values
22 #include "kwtab.h" // Incl. generated keyword tables & defs
25 unsigned altbankok = 0; // Ok to use alternate register bank
26 unsigned orgactive = 0; // RISC org directive active
27 unsigned orgaddr = 0; // Org'd address
28 unsigned orgwarning = 0; // Has an ORG warning been issued
29 int lastOpcode = -1; // Last RISC opcode assembled
30 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
32 const char reg_err[] = "missing register R0...R31";
34 // Jaguar jump condition names
35 const char condname[MAXINTERNCC][5] = {
36 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
37 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
41 // Jaguar jump condition numbers
42 const char condnumber[] = {
43 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
44 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
47 const struct opcoderecord roptbl[] = {
48 { MR_ADD, RI_TWO, 0 },
49 { MR_ADDC, RI_TWO, 1 },
50 { MR_ADDQ, RI_NUM_32, 2 },
51 { MR_ADDQT, RI_NUM_32, 3 },
52 { MR_SUB, RI_TWO, 4 },
53 { MR_SUBC, RI_TWO, 5 },
54 { MR_SUBQ, RI_NUM_32, 6 },
55 { MR_SUBQT, RI_NUM_32, 7 },
56 { MR_NEG, RI_ONE, 8 },
57 { MR_AND, RI_TWO, 9 },
58 { MR_OR, RI_TWO, 10 },
59 { MR_XOR, RI_TWO, 11 },
60 { MR_NOT, RI_ONE, 12 },
61 { MR_BTST, RI_NUM_31, 13 },
62 { MR_BSET, RI_NUM_31, 14 },
63 { MR_BCLR, RI_NUM_31, 15 },
64 { MR_MULT, RI_TWO, 16 },
65 { MR_IMULT, RI_TWO, 17 },
66 { MR_IMULTN, RI_TWO, 18 },
67 { MR_RESMAC, RI_ONE, 19 },
68 { MR_IMACN, RI_TWO, 20 },
69 { MR_DIV, RI_TWO, 21 },
70 { MR_ABS, RI_ONE, 22 },
71 { MR_SH, RI_TWO, 23 },
72 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
73 { MR_SHRQ, RI_NUM_32, 25 },
74 { MR_SHA, RI_TWO, 26 },
75 { MR_SHARQ, RI_NUM_32, 27 },
76 { MR_ROR, RI_TWO, 28 },
77 { MR_RORQ, RI_NUM_32, 29 },
78 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
79 { MR_CMP, RI_TWO, 30 },
80 { MR_CMPQ, RI_NUM_15, 31 },
81 { MR_SAT8, RI_ONE, 32 + GPUONLY },
82 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
83 { MR_SAT16, RI_ONE, 33 + GPUONLY },
84 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
85 { MR_MOVEQ, RI_NUM_31, 35 },
86 { MR_MOVETA, RI_TWO, 36 },
87 { MR_MOVEFA, RI_TWO, 37 },
88 { MR_MOVEI, RI_MOVEI, 38 },
89 { MR_LOADB, RI_LOADN, 39 },
90 { MR_LOADW, RI_LOADN, 40 },
91 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
92 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
93 { MR_STOREB, RI_STOREN, 45 },
94 { MR_STOREW, RI_STOREN, 46 },
95 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
96 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
97 { MR_JUMP, RI_JUMP, 52 },
99 { MR_MMULT, RI_TWO, 54 },
100 { MR_MTOI, RI_TWO, 55 },
101 { MR_NORMI, RI_TWO, 56 },
102 { MR_NOP, RI_NONE, 57 },
103 { MR_SAT24, RI_ONE, 62 },
104 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
105 { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
106 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
107 { MR_MOVE, RI_MOVE, 0 },
108 { MR_LOAD, RI_LOAD, 0 },
109 { MR_STORE, RI_STORE, 0 }
114 // Convert a string to uppercase
116 void strtoupper(char * s)
124 // Function to return "malformed expression" error
125 // This is done mainly to remove a bunch of GOTO statements in the parser
127 static inline int MalformedOpcode(int signal)
130 sprintf(buf, "%02X", signal);
131 return errors("Malformed opcode [internal $%s]", buf);
135 // Function to return "Illegal Indexed Register" error
136 // Anyone trying to index something other than R14 or R15
138 static inline int IllegalIndexedRegister(int reg)
141 sprintf(buf, "%d", reg - KW_R0);
142 return errors("Attempted index reference with non-indexable register (r%s)", buf);
146 // Function to return "Illegal Indexed Register" error for EQUR scenarios
147 // Trying to use register value within EQUR that isn't 14 or 15
149 static inline int IllegalIndexedRegisterEqur(SYM *sy)
153 buf = (char *)malloc((strlen(sy->sname) + 7) * sizeof(char));
155 sprintf(buf, "%s = r%d",sy->sname, sy->svalue);
156 return errors("Attempted index reference with non-indexable register within EQUR (%s)", buf);
158 return errors("Unable to allocate memory! (IllegalIndexRegisterEqur)", "OOPS");
162 // Build RISC instruction word
164 void BuildRISCIntructionWord(unsigned short opcode, int reg1, int reg2)
166 // Check for absolute address setting
167 if (!orgwarning && !orgactive)
169 warn("RISC code generated with no origin defined");
173 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
175 //printf("BuildRISC: opcode=$%X, reg1=$%X, reg2=$%X, final=$%04X\n", opcode, reg1, reg2, value);
180 // Get a RISC register
182 int GetRegister(WORD rattr)
184 VALUE eval; // Expression value
185 WORD eattr; // Expression attributes
186 SYM * esym; // External symbol involved in expr.
187 TOKEN r_expr[EXPRSIZE]; // Expression token list
189 // Evaluate what's in the global "tok" buffer
190 if (expr(r_expr, &eval, &eattr, &esym) != OK)
193 if ((challoc - ch_size) < 4)
196 if (!(eattr & DEFINED))
198 AddFixup((WORD)(FU_WORD | rattr), sloc, r_expr);
202 // If we got a register in range (0-31), return it
203 if ((eval >= 0) && (eval <= 31))
206 // Otherwise, it's out of range & we flag an error
207 return error(reg_err);
212 // Do RISC code generation
214 int GenerateRISCCode(int state)
216 int reg1; // Register 1
217 int reg2; // Register 2
218 int val = 0; // Constructed value
225 int indexed; // Indexed register flag
227 VALUE eval; // Expression value
228 WORD eattr; // Expression attributes
229 SYM * esym; // External symbol involved in expr.
230 TOKEN r_expr[EXPRSIZE]; // Expression token list
232 // Get opcode parameter and type
233 unsigned short parm = (WORD)(roptbl[state - 3000].parm);
234 unsigned type = roptbl[state - 3000].typ;
235 riscImmTokenSeen = 0; // Set to "token not seen yet"
237 // Detect whether the opcode parmeter passed determines that the opcode is
238 // specific to only one of the RISC processors and ensure it is legal in
239 // the current code section. If not then show error and return.
240 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
241 return error("Opcode is not valid in this code section");
243 // Process RISC opcode
246 // No operand instructions
249 BuildRISCIntructionWord(parm, 0, 0);
252 // Single operand instructions (Rd)
253 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
256 reg2 = GetRegister(FU_REGTWO);
258 BuildRISCIntructionWord(parm, parm >> 6, reg2);
261 // Two operand instructions (Rs,Rd)
262 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
263 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
266 altbankok = 1; // MOVEFA
268 reg1 = GetRegister(FU_REGONE);
272 altbankok = 1; // MOVETA
274 reg2 = GetRegister(FU_REGTWO);
276 BuildRISCIntructionWord(parm, reg1, reg2);
279 // Numeric operand (n,Rd) where n = -16..+15
283 // Numeric operand (n,Rd) where n = 0..31
284 // BCLR, BSET, BTST, MOVEQ
287 // Numeric operand (n,Rd) where n = 1..32
288 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
294 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
298 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
301 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
309 return MalformedOpcode(0x01);
312 riscImmTokenSeen = 1;
314 if (expr(r_expr, &eval, &eattr, &esym) != OK)
315 return MalformedOpcode(0x02);
317 if ((challoc - ch_size) < 4)
320 if (!(eattr & DEFINED))
322 AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
327 if ((int)eval < reg1 || (int)eval > reg2)
328 return error("constant out of range");
332 else if (type == RI_NUM_32)
333 reg1 = (reg1 == 32 ? 0 : eval);
339 reg2 = GetRegister(FU_REGTWO);
341 BuildRISCIntructionWord(parm, reg1, reg2);
344 // Move Immediate--n,Rn--n in Second Word
347 return MalformedOpcode(0x03);
350 riscImmTokenSeen = 1;
352 // Check for equated register after # and return error if so
355 sy = lookup(string[tok[1]], LABEL, 0);
357 if (sy && (sy->sattre & EQUATEDREG))
358 return error("equated register in 1st operand of MOVEI instruction");
361 if (expr(r_expr, &eval, &eattr, &esym) != OK)
362 return MalformedOpcode(0x04);
364 if (lastOpcode == RI_JUMP || lastOpcode == RI_JR)
368 // User doesn't care, emit a NOP to fix
369 BuildRISCIntructionWord(57, 0, 0);
370 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
373 warn("MOVEI immediately follows JUMP");
376 if ((challoc - ch_size) < 4)
379 if (!(eattr & DEFINED))
381 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
388 //printf("RISCASM: Doing MarkRelocatable for RI_MOVEI (tdb=$%X)...\n", eattr & TDB);
389 MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
393 // val = ((eval >> 16) & 0x0000FFFF) | ((eval << 16) & 0xFFFF0000);
394 val = WORDSWAP32(eval);
396 reg2 = GetRegister(FU_REGTWO);
398 D_word((((parm & 0x3F) << 10) + reg2));
413 reg1 = GetRegister(FU_REGONE);
417 reg2 = GetRegister(FU_REGTWO);
419 BuildRISCIntructionWord(parm, reg1, reg2);
422 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
428 return MalformedOpcode(0x05);
432 if ((*(tok + 1) == '+') || (*(tok + 1) == '-')) {
433 // Trying to make indexed call
434 if ((*tok == KW_R14 || *tok == KW_R15)) {
435 indexed = (*tok - KW_R0);
437 return IllegalIndexedRegister(*tok);
443 // sy = lookup((char *)tok[1], LABEL, 0);
444 sy = lookup(string[tok[1]], LABEL, 0);
452 if (sy->sattre & EQUATEDREG)
454 if ((*(tok + 2) == '+') || (*(tok + 2) == '-')) {
455 if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) {
456 indexed = (sy->svalue & 0x1F);
459 return IllegalIndexedRegisterEqur(sy);
467 reg1 = GetRegister(FU_REGONE);
477 parm = (WORD)(reg1 - 14 + 58);
480 if (*tok >= KW_R0 && *tok <= KW_R31)
485 // sy = lookup((char *)tok[1], LABEL, 0);
486 sy = lookup(string[tok[1]], LABEL, 0);
494 if (sy->sattre & EQUATEDREG)
500 reg1 = GetRegister(FU_REGONE);
504 if (expr(r_expr, &eval, &eattr, &esym) != OK)
505 return MalformedOpcode(0x06);
507 if ((challoc - ch_size) < 4)
510 if (!(eattr & DEFINED))
511 return error("constant expected after '+'");
517 reg1 = 14 + (parm - 58);
519 warn("NULL offset in LOAD ignored");
523 if (reg1 < 1 || reg1 > 32)
524 return error("constant in LOAD out of range");
529 parm = (WORD)(parm - 58 + 43);
535 reg1 = GetRegister(FU_REGONE);
540 return MalformedOpcode(0x07);
544 reg2 = GetRegister(FU_REGTWO);
546 BuildRISCIntructionWord(parm, reg1, reg2);
549 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
552 reg1 = GetRegister(FU_REGONE);
556 return MalformedOpcode(0x08);
561 if ((*tok == KW_R14 || *tok == KW_R15) && (*(tok + 1) != ')'))
562 indexed = (*tok - KW_R0);
566 sy = lookup(string[tok[1]], LABEL, 0);
574 if (sy->sattre & EQUATEDREG)
576 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
577 && (*(tok + 2) != ')'))
579 indexed = (sy->svalue & 0x1F);
587 reg2 = GetRegister(FU_REGTWO);
597 parm = (WORD)(reg2 - 14 + 60);
600 if (*tok >= KW_R0 && *tok <= KW_R31)
605 sy = lookup(string[tok[1]], LABEL, 0);
613 if (sy->sattre & EQUATEDREG)
619 reg2 = GetRegister(FU_REGTWO);
623 if (expr(r_expr, &eval, &eattr, &esym) != OK)
624 return MalformedOpcode(0x09);
626 if ((challoc - ch_size) < 4)
629 if (!(eattr & DEFINED))
631 AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
640 reg2 = 14 + (parm - 60);
642 warn("NULL offset in STORE ignored");
646 if (reg2 < 1 || reg2 > 32)
647 return error("constant in STORE out of range");
652 parm = (WORD)(parm - 60 + 49);
659 reg2 = GetRegister(FU_REGTWO);
664 return MalformedOpcode(0x0A);
668 BuildRISCIntructionWord(parm, reg2, reg1);
671 // LOADB/LOADP/LOADW (Rn),Rn
674 return MalformedOpcode(0x0B);
677 reg1 = GetRegister(FU_REGONE);
680 return MalformedOpcode(0x0C);
684 reg2 = GetRegister(FU_REGTWO);
686 BuildRISCIntructionWord(parm, reg1, reg2);
689 // STOREB/STOREP/STOREW Rn,(Rn)
691 reg1 = GetRegister(FU_REGONE);
695 return MalformedOpcode(0x0D);
698 reg2 = GetRegister(FU_REGTWO);
701 return MalformedOpcode(0x0E);
705 BuildRISCIntructionWord(parm, reg2, reg1);
708 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
711 // Jump Absolute - cc,(Rs) - reg2=cc
713 // Check to see if there is a comma in the token string. If not then
714 // the JR or JUMP should default to 0, Jump Always
717 for(t=tok; *t!=EOL; t++)
730 // CC using a constant number
736 else if (*tok == SYMBOL)
739 // strcpy(scratch, (char *)tok[1]);
740 strcpy(scratch, string[tok[1]]);
743 for(i=0; i<MAXINTERNCC; i++)
745 // Look for the condition code & break if found
746 if (strcmp(condname[i], scratch) == 0)
753 // Standard CC was not found, look for an equated one
756 // ccsym = lookup((char *)tok[1], LABEL, 0);
757 ccsym = lookup(string[tok[1]], LABEL, 0);
759 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
764 return error("unknown condition code");
770 else if (*tok == '(')
772 // Set CC to "Jump Always"
778 // Set CC to "Jump Always"
782 if (val < 0 || val > 31)
783 return error("condition constant out of range");
785 // Store condition code
791 if (expr(r_expr, &eval, &eattr, &esym) != OK)
792 return MalformedOpcode(0x0F);
794 if ((challoc - ch_size) < 4)
797 if (!(eattr & DEFINED))
799 AddFixup(FU_WORD | FU_JR, sloc, r_expr);
804 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
806 if ((reg2 < -16) || (reg2 > 15))
807 error("PC relative overflow");
810 BuildRISCIntructionWord(parm, reg2, reg1);
816 return MalformedOpcode(0x10);
819 reg2 = GetRegister(FU_REGTWO);
822 return MalformedOpcode(0x11);
826 BuildRISCIntructionWord(parm, reg2, reg1);
831 // Should never get here :-D
833 return error("Unknown RISC opcode type");