2 // RMAC - Reboot's Macro Assembler for all Atari computers
3 // RISCA.C - GPU/DSP Assembler
4 // Copyright (C) 199x Landon Dyer, 2011-2018 Reboot and Friends
5 // RMAC derived from MADMAC v1.07 Written by Landon Dyer, 1986
6 // Source utilised with the kind permission of Landon Dyer
20 #define DEF_MR // Declare keyword values
21 #include "risckw.h" // Incl. generated risc keywords
23 #define DEF_KW // Declare keyword values
24 #include "kwtab.h" // Incl. generated keyword tables & defs
26 #define MAXINTERNCC 26 // Maximum internal condition codes
29 unsigned altbankok = 0; // Ok to use alternate register bank
30 unsigned orgactive = 0; // RISC/6502 org directive active
31 unsigned orgaddr = 0; // Org'd address
32 unsigned orgwarning = 0; // Has an ORG warning been issued
33 int lastOpcode = -1; // Last RISC opcode assembled
34 uint8_t riscImmTokenSeen; // The '#' (immediate) token was seen
36 static const char reg_err[] = "missing register R0...R31";
38 // Jaguar jump condition names
39 static const char condname[MAXINTERNCC][5] = {
40 "NZ", "Z", "NC", "NCNZ", "NCZ", "C", "CNZ", "CZ", "NN", "NNNZ", "NNZ",
41 "N", "N_NZ", "N_Z", "T", "A", "NE", "EQ", "CC", "HS", "HI", "CS", "LO",
45 // Jaguar jump condition numbers
46 static const char condnumber[] = {
47 1, 2, 4, 5, 6, 8, 9, 10, 20, 21, 22, 24, 25, 26,
48 0, 0, 1, 2, 4, 4, 5, 8, 8, 20, 24, 31
51 // Opcode Specific Data
53 uint16_t state; // Opcode Name (unused)
54 uint16_t type; // Opcode Type
55 uint16_t param; // Opcode Parameter
58 static const struct opcoderecord roptbl[] = {
59 { MR_ADD, RI_TWO, 0 },
60 { MR_ADDC, RI_TWO, 1 },
61 { MR_ADDQ, RI_NUM_32, 2 },
62 { MR_ADDQT, RI_NUM_32, 3 },
63 { MR_SUB, RI_TWO, 4 },
64 { MR_SUBC, RI_TWO, 5 },
65 { MR_SUBQ, RI_NUM_32, 6 },
66 { MR_SUBQT, RI_NUM_32, 7 },
67 { MR_NEG, RI_ONE, 8 },
68 { MR_AND, RI_TWO, 9 },
69 { MR_OR, RI_TWO, 10 },
70 { MR_XOR, RI_TWO, 11 },
71 { MR_NOT, RI_ONE, 12 },
72 { MR_BTST, RI_NUM_31, 13 },
73 { MR_BSET, RI_NUM_31, 14 },
74 { MR_BCLR, RI_NUM_31, 15 },
75 { MR_MULT, RI_TWO, 16 },
76 { MR_IMULT, RI_TWO, 17 },
77 { MR_IMULTN, RI_TWO, 18 },
78 { MR_RESMAC, RI_ONE, 19 },
79 { MR_IMACN, RI_TWO, 20 },
80 { MR_DIV, RI_TWO, 21 },
81 { MR_ABS, RI_ONE, 22 },
82 { MR_SH, RI_TWO, 23 },
83 { MR_SHLQ, RI_NUM_32, 24 + SUB32 },
84 { MR_SHRQ, RI_NUM_32, 25 },
85 { MR_SHA, RI_TWO, 26 },
86 { MR_SHARQ, RI_NUM_32, 27 },
87 { MR_ROR, RI_TWO, 28 },
88 { MR_RORQ, RI_NUM_32, 29 },
89 { MR_ROLQ, RI_NUM_32, 29 + SUB32 },
90 { MR_CMP, RI_TWO, 30 },
91 { MR_CMPQ, RI_NUM_15, 31 },
92 { MR_SAT8, RI_ONE, 32 + GPUONLY },
93 { MR_SUBQMOD, RI_NUM_32, 32 + DSPONLY },
94 { MR_SAT16, RI_ONE, 33 + GPUONLY },
95 { MR_SAT16S, RI_ONE, 33 + DSPONLY },
96 { MR_MOVEQ, RI_NUM_31, 35 },
97 { MR_MOVETA, RI_TWO, 36 },
98 { MR_MOVEFA, RI_TWO, 37 },
99 { MR_MOVEI, RI_MOVEI, 38 },
100 { MR_LOADB, RI_LOADN, 39 },
101 { MR_LOADW, RI_LOADN, 40 },
102 { MR_LOADP, RI_LOADN, 42 + GPUONLY },
103 { MR_SAT32S, RI_ONE, 42 + DSPONLY },
104 { MR_STOREB, RI_STOREN, 45 },
105 { MR_STOREW, RI_STOREN, 46 },
106 { MR_STOREP, RI_STOREN, 48 + GPUONLY },
107 { MR_MIRROR, RI_ONE, 48 + DSPONLY },
108 { MR_JUMP, RI_JUMP, 52 },
109 { MR_JR, RI_JR, 53 },
110 { MR_MMULT, RI_TWO, 54 },
111 { MR_MTOI, RI_TWO, 55 },
112 { MR_NORMI, RI_TWO, 56 },
113 { MR_NOP, RI_NONE, 57 },
114 { MR_SAT24, RI_ONE, 62 },
115 { MR_UNPACK, RI_ONE, 63 + GPUONLY | (0 << 6) },
116 { MR_PACK, RI_ONE, 63 + GPUONLY | (1 << 6) },
117 { MR_ADDQMOD, RI_NUM_32, 63 + DSPONLY },
118 { MR_MOVE, RI_MOVE, 0 },
119 { MR_LOAD, RI_LOAD, 0 },
120 { MR_STORE, RI_STORE, 0 }
125 #define MALF_LPAREN 2
126 #define MALF_RPAREN 3
128 static const char malform1[] = "missing '#'";
129 static const char malform2[] = "bad expression";
130 static const char malform3[] = "missing ')'";
131 static const char malform4[] = "missing '('";
133 static const char * malformErr[] = {
134 malform1, malform2, malform3, malform4
139 // Function to return "malformed expression" error
140 // This is done mainly to remove a bunch of GOTO statements in the parser
142 static inline int MalformedOpcode(int signal)
144 return error("Malformed opcode, %s", malformErr[signal]);
149 // Function to return "Illegal Indexed Register" error
150 // Anyone trying to index something other than R14 or R15
152 static inline int IllegalIndexedRegister(int reg)
154 return error("Attempted index reference with non-indexable register (r%d)", reg - KW_R0);
159 // Function to return "Illegal Indexed Register" error for EQUR scenarios
160 // Trying to use register value within EQUR that isn't 14 or 15
162 static inline int IllegalIndexedRegisterEqur(SYM * sy)
164 return error("Attempted index reference with non-indexable register within EQUR (%s = r%d)", sy->sname, sy->svalue);
169 // Build up & deposit RISC instruction word
171 static void DepositRISCInstructionWord(uint16_t opcode, int reg1, int reg2)
173 // Check for absolute address setting
174 if (!orgwarning && !orgactive)
176 warn("RISC code generated with no origin defined");
180 int value = ((opcode & 0x3F) << 10) + ((reg1 & 0x1F) << 5) + (reg2 & 0x1F);
186 // Evaluate the RISC register from the token stream. Passed in value is the
187 // FIXUP attribute to use if the expression comes back as undefined.
189 static int EvaluateRegisterFromTokenStream(uint32_t attr)
191 uint64_t eval; // Expression value
192 WORD eattr; // Expression attributes
193 SYM * esym; // External symbol involved in expr.
194 TOKEN r_expr[EXPRSIZE]; // Expression token list
196 // Evaluate what's in the global "tok" buffer
197 if (expr(r_expr, &eval, &eattr, &esym) != OK)
200 if (!(eattr & DEFINED))
202 AddFixup(FU_WORD | attr, sloc, r_expr);
206 // If we got a register in range (0-31), return it
210 // Otherwise, it's out of range & we flag an error
211 return error(reg_err);
216 // Do RISC code generation
218 int GenerateRISCCode(int state)
220 int reg1; // Register 1
221 int reg2; // Register 2
222 int val = 0; // Constructed value
229 int indexed; // Indexed register flag
231 uint64_t eval; // Expression value
232 uint16_t eattr; // Expression attributes
233 SYM * esym; // External symbol involved in expr.
234 TOKEN r_expr[EXPRSIZE]; // Expression token list
236 // Get opcode parameter and type
237 uint16_t parm = roptbl[state - 3000].param;
238 uint16_t type = roptbl[state - 3000].type;
239 riscImmTokenSeen = 0; // Set to "token not seen yet"
241 // Detect whether the opcode parmeter passed determines that the opcode is
242 // specific to only one of the RISC processors and ensure it is legal in
243 // the current code section. If not then show error and return.
244 if (((parm & GPUONLY) && rdsp) || ((parm & DSPONLY) && rgpu))
245 return error("Opcode is not valid in this code section");
247 // Process RISC opcode
250 // No operand instructions
253 DepositRISCInstructionWord(parm, 0, 0);
256 // Single operand instructions (Rd)
257 // ABS, MIRROR, NEG, NOT, PACK, RESMAC, SAT8, SAT16, SAT16S, SAT24, SAT32S,
260 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
262 DepositRISCInstructionWord(parm, parm >> 6, reg2);
265 // Two operand instructions (Rs,Rd)
266 // ADD, ADDC, AND, CMP, DIV, IMACN, IMULT, IMULTN, MOVEFA, MOVETA, MULT,
267 // MMULT, MTOI, NORMI, OR, ROR, SH, SHA, SUB, SUBC, XOR
270 altbankok = 1; // MOVEFA
272 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
276 altbankok = 1; // MOVETA
278 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
280 DepositRISCInstructionWord(parm, reg1, reg2);
283 // Numeric operand (n,Rd) where n = -16..+15
287 // Numeric operand (n,Rd) where n = 0..31
288 // BCLR, BSET, BTST, MOVEQ
291 // Numeric operand (n,Rd) where n = 1..32
292 // ADDQ, ADDQMOD, ADDQT, SHARQ, SHLQ, SHRQ, SUBQ, SUBQMOD, SUBQT, ROLQ,
298 reg1 = -16; reg2 = 15; attrflg = FU_NUM15;
302 reg1 = 0; reg2 = 31; attrflg = FU_NUM31;
305 reg1 = 1; reg2 = 32; attrflg = FU_NUM32;
313 return MalformedOpcode(MALF_NUM);
316 riscImmTokenSeen = 1;
318 if (expr(r_expr, &eval, &eattr, &esym) != OK)
319 return MalformedOpcode(MALF_EXPR);
321 if (!(eattr & DEFINED))
323 AddFixup((WORD)(FU_WORD | attrflg), sloc, r_expr);
328 if (((int)eval < reg1) || ((int)eval > reg2))
329 return error("constant out of range (%d to %d", reg1, reg2);
332 reg1 = 32 - (int)eval;
333 else if (type == RI_NUM_32)
334 reg1 = (reg1 == 32 ? 0 : (int)eval);
340 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
342 DepositRISCInstructionWord(parm, reg1, reg2);
345 // Move Immediate--n,Rn--n in Second Word
348 return MalformedOpcode(MALF_NUM);
351 riscImmTokenSeen = 1;
353 // Check for equated register after # and return error if so
356 sy = lookup(string[tok[1]], LABEL, 0);
358 if (sy && (sy->sattre & EQUATEDREG))
359 return error("equated register in 1st operand of MOVEI instruction");
362 if (expr(r_expr, &eval, &eattr, &esym) != OK)
363 return MalformedOpcode(MALF_EXPR);
365 if ((lastOpcode == RI_JUMP) || (lastOpcode == RI_JR))
369 // User doesn't care, emit a NOP to fix
370 DepositRISCInstructionWord(57, 0, 0);
371 warn("MOVEI following JUMP, inserting NOP to fix your BROKEN CODE");
374 warn("MOVEI immediately follows JUMP");
377 if (!(eattr & DEFINED))
379 AddFixup(FU_LONG | FU_MOVEI, sloc + 2, r_expr);
385 MarkRelocatable(cursect, sloc + 2, (eattr & TDB), (MLONG | MMOVEI), NULL);
389 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
392 DepositRISCInstructionWord(parm, 0, reg2);
393 val = WORDSWAP32(eval);
408 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
412 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
414 DepositRISCInstructionWord(parm, reg1, reg2);
417 // (Rn),Rn = 41 / (R14/R15+n),Rn = 43/44 / (R14/R15+Rn),Rn = 58/59
423 return MalformedOpcode(MALF_LPAREN);
427 if ((tok[1] == '+') || (tok[1] == '-'))
429 // Trying to make indexed call
430 if ((*tok == KW_R14) || (*tok == KW_R15))
431 indexed = (*tok - KW_R0);
433 return IllegalIndexedRegister(*tok);
438 sy = lookup(string[tok[1]], LABEL, 0);
446 if (sy->sattre & EQUATEDREG)
448 if ((tok[2] == '+') || (tok[2] == '-'))
450 if ((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15) {
451 indexed = (sy->svalue & 0x1F);
455 return IllegalIndexedRegisterEqur(sy);
462 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
472 parm = (WORD)(reg1 - 14 + 58);
475 if ((*tok >= KW_R0) && (*tok <= KW_R31))
480 sy = lookup(string[tok[1]], LABEL, 0);
488 if (sy->sattre & EQUATEDREG)
494 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
498 if (expr(r_expr, &eval, &eattr, &esym) != OK)
499 return MalformedOpcode(MALF_EXPR);
501 if (!(eattr & DEFINED))
502 return error("constant expected after '+'");
508 reg1 = 14 + (parm - 58);
510 warn("NULL offset in LOAD ignored");
514 if ((reg1 < 1) || (reg1 > 32))
515 return error("constant in LOAD out of range (1-32)");
520 parm = (WORD)(parm - 58 + 43);
526 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
531 return MalformedOpcode(MALF_RPAREN);
535 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
537 DepositRISCInstructionWord(parm, reg1, reg2);
540 // Rn,(Rn) = 47 / Rn,(R14/R15+n) = 49/50 / Rn,(R14/R15+Rn) = 60/61
543 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
547 return MalformedOpcode(MALF_LPAREN);
552 if (((*tok == KW_R14) || (*tok == KW_R15)) && (tok[1] != ')'))
553 indexed = *tok - KW_R0;
557 sy = lookup(string[tok[1]], LABEL, 0);
565 if (sy->sattre & EQUATEDREG)
567 if (((sy->svalue & 0x1F) == 14 || (sy->svalue & 0x1F) == 15)
570 indexed = (sy->svalue & 0x1F);
578 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
588 parm = (WORD)(reg2 - 14 + 60);
591 if ((*tok >= KW_R0) && (*tok <= KW_R31))
596 sy = lookup(string[tok[1]], LABEL, 0);
604 if (sy->sattre & EQUATEDREG)
610 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
614 if (expr(r_expr, &eval, &eattr, &esym) != OK)
615 return MalformedOpcode(MALF_EXPR);
617 if (!(eattr & DEFINED))
619 AddFixup(FU_WORD | FU_REGTWO, sloc, r_expr);
628 reg2 = 14 + (parm - 60);
630 warn("NULL offset in STORE ignored");
634 if ((reg2 < 1) || (reg2 > 32))
635 return error("constant in STORE out of range (1-32)");
640 parm = (WORD)(parm - 60 + 49);
647 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
652 return MalformedOpcode(MALF_RPAREN);
656 DepositRISCInstructionWord(parm, reg2, reg1);
659 // LOADB/LOADP/LOADW (Rn),Rn
662 return MalformedOpcode(MALF_LPAREN);
665 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
668 return MalformedOpcode(MALF_RPAREN);
672 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
674 DepositRISCInstructionWord(parm, reg1, reg2);
677 // STOREB/STOREP/STOREW Rn,(Rn)
679 reg1 = EvaluateRegisterFromTokenStream(FU_REGONE);
683 return MalformedOpcode(MALF_LPAREN);
686 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
689 return MalformedOpcode(MALF_RPAREN);
693 DepositRISCInstructionWord(parm, reg2, reg1);
696 // Jump Relative - cc,n - n=-16..+15 words, reg2=cc
699 // Jump Absolute - cc,(Rs) - reg2=cc
701 // Check to see if there is a comma in the token string. If not then
702 // the JR or JUMP should default to 0, Jump Always
705 for(t=tok; *t!=EOL; t++)
718 // CC using a constant number (O_o)
725 else if (*tok == SYMBOL)
728 strcpy(scratch, string[tok[1]]);
731 for(i=0; i<MAXINTERNCC; i++)
733 // Look for the condition code & break if found
734 if (strcmp(condname[i], scratch) == 0)
741 // Standard CC was not found, look for an equated one
744 ccsym = lookup(string[tok[1]], LABEL, 0);
746 if (ccsym && (ccsym->sattre & EQUATEDCC) && !(ccsym->sattre & UNDEF_CC))
747 val = (int)ccsym->svalue;
749 return error("unknown condition code");
755 else if (*tok == '(')
757 // Set CC to "Jump Always"
763 // Set CC to "Jump Always"
767 if ((val < 0) || (val > 31))
768 return error("condition constant out of range");
770 // Store condition code
776 if (expr(r_expr, &eval, &eattr, &esym) != OK)
777 return MalformedOpcode(MALF_EXPR);
779 if (!(eattr & DEFINED))
781 AddFixup(FU_WORD | FU_JR, sloc, r_expr);
786 reg2 = ((int)(eval - ((orgactive ? orgaddr : sloc) + 2))) / 2;
788 if ((reg2 < -16) || (reg2 > 15))
789 error("PC relative overflow in JR (outside of -16 to 15)");
796 return MalformedOpcode(MALF_LPAREN);
799 reg2 = EvaluateRegisterFromTokenStream(FU_REGTWO);
802 return MalformedOpcode(MALF_RPAREN);
808 DepositRISCInstructionWord(parm, reg2, reg1);
811 // We should never get here. If we do, somebody done fucked up. :-D
813 return error("Unknown RISC opcode type");