1 abs M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d110 dsp_ab d=(a=0, b=1)
\r
2 asl M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d010 dsp_ab d=(a=0, b=1)
\r
3 asr M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d010 dsp_ab d=(a=0, b=1)
\r
4 clr M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0001d011 dsp_ab d=(a=0, b=1)
\r
5 lsl M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d011 dsp_ab d=(a=0, b=1)
\r
6 lsr M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d011 dsp_ab d=(a=0, b=1)
\r
7 not M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0001d111 dsp_ab d=(a=0, b=1)
\r
8 addl M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d010 dsp_baab d=(b,a=0, a,b=1)
\r
9 addr M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d010 dsp_baab d=(b,a=0, a,b=1)
\r
10 add M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d000 dsp_baab + d=(a=0, b=1)
\r
11 - M_ALL48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd000 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
\r
12 cmp M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d101 dsp_baab + d=(a=0, b=1)
\r
13 - M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd101 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
\r
14 cmpm M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d111 dsp_baab + d=(a=0, b=1)
\r
15 - M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd111 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
\r
16 sub M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d100 dsp_baab + d=(a=0, b=1)
\r
17 - M_ALL48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd100 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
\r
18 tfr M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d001 dsp_baab + d=(a=0, b=1)
\r
19 - M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0jjjd001 dsp_acc48 jjj=(x=2, y=3, x0=4, y0=5, x1=6, y1=7), d=(a=0, b=1)
\r
20 rnd M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0001d001 dsp_ab d=(a=0, b=1)
\r
21 rol M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d111 dsp_ab d=(a=0, b=1)
\r
22 ror M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0010d111 dsp_ab d=(a=0, b=1)
\r
23 subl M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0001d110 dsp_baab d=(b,a=0, a,b=1)
\r
24 subr M_ACC56 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm0000d110 dsp_baab d=(b,a=0, a,b=1)
\r
25 tst M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0000d011 dsp_ab d=(a=0, b=1)
\r
26 enddo M_AM_NONE M_AM_NONE NOPARMO %000000000000000010001100 dsp_self
\r
27 illegal M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000101 dsp_self
\r
28 nop M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000000 dsp_self
\r
29 reset M_AM_NONE M_AM_NONE NOPARMO %000000000000000010000100 dsp_self
\r
30 rti M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000100 dsp_self
\r
31 rts M_AM_NONE M_AM_NONE NOPARMO %000000000000000000001100 dsp_self
\r
32 stop M_AM_NONE M_AM_NONE NOPARMO %000000000000000010000111 dsp_self
\r
33 swi M_AM_NONE M_AM_NONE NOPARMO %000000000000000000000110 dsp_self
\r
34 wait M_AM_NONE M_AM_NONE NOPARMO %000000000000000010000110 dsp_self
\r
35 adc M_INP48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm001jd001 dsp_xyab j=(x=0, y=1), d=(a=0, b=1)
\r
36 sbc M_INP48 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm001jd101 dsp_xyab s1 (j)=(x=0,y=1),s2 (d)=(a=0,b=1)
\r
37 and M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm01jjd110 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
\r
38 eor M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm01jjd011 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
\r
39 div M_ALU24 M_ACC56 NOPARMO %000000011000000001jjd000 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
\r
40 or M_ALU24 M_ACC56 PARMOVE %mmmmmmmmmmmmmmmm01jjd010 dsp_x0y0ab jj=(x0=0, x1=2, y0=1, y1=3), d=(a=0, b=1)
\r
41 andi M_DSPIM8 M_DSPPCU NOPARMO %00000000iiiiiiii101110ee dsp_immcr ee=(mr=0, ccr=1, omr=2)
\r
42 ori M_DSPIM8 M_DSPPCU NOPARMO %00000000iiiiiiii111110ee dsp_immcr ee=(mr=0, ccr=1, omr=2)
\r
43 tcc M_ACC56 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
44 - M_ALL48 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
45 ths M_ACC56 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
46 - M_ALL48 M_ACC56 NOPARMO %00000010000000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
47 tcs M_ACC56 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
48 - M_ALL48 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
49 tlo M_ACC56 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
50 - M_ALL48 M_ACC56 NOPARMO %00000010100000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
51 tec M_ACC56 M_ACC56 NOPARMO %00000010010100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
52 - M_ALL48 M_ACC56 NOPARMO %00000010010100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
53 teq M_ACC56 M_ACC56 NOPARMO %00000010101000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
54 - M_ALL48 M_ACC56 NOPARMO %00000010101000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
55 tes M_ACC56 M_ACC56 NOPARMO %00000010110100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
56 - M_ALL48 M_ACC56 NOPARMO %00000010110100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
57 tge M_ACC56 M_ACC56 NOPARMO %00000010000100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
58 - M_ALL48 M_ACC56 NOPARMO %00000010000100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
59 tgt M_ACC56 M_ACC56 NOPARMO %00000010011100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
60 - M_ALL48 M_ACC56 NOPARMO %00000010011100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
61 tlc M_ACC56 M_ACC56 NOPARMO %00000010011000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
62 - M_ALL48 M_ACC56 NOPARMO %00000010011000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
63 tle M_ACC56 M_ACC56 NOPARMO %00000010111100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
64 - M_ALL48 M_ACC56 NOPARMO %00000010111100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
65 tls M_ACC56 M_ACC56 NOPARMO %00000010111000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
66 - M_ALL48 M_ACC56 NOPARMO %00000010111000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
67 tlt M_ACC56 M_ACC56 NOPARMO %00000010100100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
68 - M_ALL48 M_ACC56 NOPARMO %00000010100100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
69 tmi M_ACC56 M_ACC56 NOPARMO %00000010101100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
70 - M_ALL48 M_ACC56 NOPARMO %00000010101100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
71 tne M_ACC56 M_ACC56 NOPARMO %00000010001000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
72 - M_ALL48 M_ACC56 NOPARMO %00000010001000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
73 tnr M_ACC56 M_ACC56 NOPARMO %00000010110000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
74 - M_ALL48 M_ACC56 NOPARMO %00000010110000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
75 tpl M_ACC56 M_ACC56 NOPARMO %00000010001100000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
76 - M_ALL48 M_ACC56 NOPARMO %00000010001100000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
77 tnn M_ACC56 M_ACC56 NOPARMO %00000010010000000jjjd000 dsp_baab + s1,d1 [s2,d2]
\r
78 - M_ALL48 M_ACC56 NOPARMO %00000010010000000jjjd000 dsp_tcc2 s1,d1 [s2,d2]
\r
79 jcc M_DSPABS12 M_AM_NONE NOPARMO %000011100000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
80 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100000 dsp_ea Jcc ea mmmrrr=ea
\r
81 jhs M_DSPABS12 M_AM_NONE NOPARMO %000011100000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
82 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100000 dsp_ea Jcc ea mmmrrr=ea
\r
83 jcs M_DSPABS12 M_AM_NONE NOPARMO %000011101000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
84 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101000 dsp_ea Jcc ea mmmrrr=ea
\r
85 jlo M_DSPABS12 M_AM_NONE NOPARMO %000011101000aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
86 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101000 dsp_ea Jcc ea mmmrrr=ea
\r
87 jec M_DSPABS12 M_AM_NONE NOPARMO %000011100101aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
88 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100101 dsp_ea Jcc ea mmmrrr=ea
\r
89 jeq M_DSPABS12 M_AM_NONE NOPARMO %000011101010aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
90 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101010 dsp_ea Jcc ea mmmrrr=ea
\r
91 jes M_DSPABS12 M_AM_NONE NOPARMO %000011101101aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
92 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101101 dsp_ea Jcc ea mmmrrr=ea
\r
93 jge M_DSPABS12 M_AM_NONE NOPARMO %000011100001aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
94 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100001 dsp_ea Jcc ea mmmrrr=ea
\r
95 jgt M_DSPABS12 M_AM_NONE NOPARMO %000011100111aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
96 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100111 dsp_ea Jcc ea mmmrrr=ea
\r
97 jge M_DSPABS12 M_AM_NONE NOPARMO %000011100001aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
98 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100001 dsp_ea Jcc ea mmmrrr=ea
\r
99 jlc M_DSPABS12 M_AM_NONE NOPARMO %000011100110aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
100 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100110 dsp_ea Jcc ea mmmrrr=ea
\r
101 jle M_DSPABS12 M_AM_NONE NOPARMO %000011101111aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
102 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101111 dsp_ea Jcc ea mmmrrr=ea
\r
103 jls M_DSPABS12 M_AM_NONE NOPARMO %000011101110aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
104 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101110 dsp_ea Jcc ea mmmrrr=ea
\r
105 jlt M_DSPABS12 M_AM_NONE NOPARMO %000011101001aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
106 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101001 dsp_ea Jcc ea mmmrrr=ea
\r
107 jmi M_DSPABS12 M_AM_NONE NOPARMO %000011101011aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
108 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101011 dsp_ea Jcc ea mmmrrr=ea
\r
109 jne M_DSPABS12 M_AM_NONE NOPARMO %000011100010aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
110 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100010 dsp_ea Jcc ea mmmrrr=ea
\r
111 jnr M_DSPABS12 M_AM_NONE NOPARMO %000011101100aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
112 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10101100 dsp_ea Jcc ea mmmrrr=ea
\r
113 jpl M_DSPABS12 M_AM_NONE NOPARMO %000011100011aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
114 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100011 dsp_ea Jcc ea mmmrrr=ea
\r
115 jnn M_DSPABS12 M_AM_NONE NOPARMO %000011100100aaaaaaaaaaaa dsp_abs12 + Jcc xxx aaaaaaaaaaaa=12bit address
\r
116 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10100100 dsp_ea Jcc ea mmmrrr=ea
\r
117 jmp M_DSPABS12 M_AM_NONE NOPARMO %000011000000aaaaaaaaaaaa dsp_abs12 + JMP xxx aaaaaaaaaaaa=12bit address
\r
118 - C_DSPABSEA M_AM_NONE NOPARMO %0000101011mmmrrr10000000 dsp_ea JMP ea (+optional 24bit address)
\r
119 jscc M_DSPABS12 M_AM_NONE NOPARMO %000011110000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
120 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
121 jshs M_DSPABS12 M_AM_NONE NOPARMO %000011110000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
122 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
123 jscs M_DSPABS12 M_AM_NONE NOPARMO %000011111000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
124 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
125 jslo M_DSPABS12 M_AM_NONE NOPARMO %000011111000aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
126 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101000 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
127 jsec M_DSPABS12 M_AM_NONE NOPARMO %000011110101aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
128 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100101 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
129 jseq M_DSPABS12 M_AM_NONE NOPARMO %000011111010aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
130 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101010 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
131 jses M_DSPABS12 M_AM_NONE NOPARMO %000011111101aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
132 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101101 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
133 jsge M_DSPABS12 M_AM_NONE NOPARMO %000011110001aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
134 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100001 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
135 jsgt M_DSPABS12 M_AM_NONE NOPARMO %000011110111aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
136 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100111 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
137 jslc M_DSPABS12 M_AM_NONE NOPARMO %000011110110aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
138 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100110 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
139 jsle M_DSPABS12 M_AM_NONE NOPARMO %000011111111aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
140 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101111 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
141 jsls M_DSPABS12 M_AM_NONE NOPARMO %000011111110aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
142 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101110 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
143 jslt M_DSPABS12 M_AM_NONE NOPARMO %000011111001aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
144 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101001 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
145 jsmi M_DSPABS12 M_AM_NONE NOPARMO %000011111011aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
146 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101011 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
147 jsne M_DSPABS12 M_AM_NONE NOPARMO %000011110010aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
148 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100010 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
149 jsnr M_DSPABS12 M_AM_NONE NOPARMO %000011111100aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
150 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10101100 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
151 jspl M_DSPABS12 M_AM_NONE NOPARMO %000011110011aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
152 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100011 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
153 jsnn M_DSPABS12 M_AM_NONE NOPARMO %000011110100aaaaaaaaaaaa dsp_abs12 + JScc xxx aaaaaaaaaaaa=12bit address
\r
154 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10100100 dsp_ea JScc ea mmmrrr=ea (+optional 24bit address)
\r
155 jsr M_DSPABS12 M_AM_NONE NOPARMO %000011010000aaaaaaaaaaaa dsp_abs12 + JSR xxx aaaaaaaaaaaa=12bit address
\r
156 - C_DSPABSEA M_AM_NONE NOPARMO %0000101111mmmrrr10000000 dsp_ea JSR ea mmmrrr=ea (+optional 24bit address)
\r
157 neg M_ACC56 M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm0011d110 dsp_ab d=(a=0, b=1)
\r
158 bchg C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr0s0bbbbb dsp_ea_imm5 + bchg #n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
\r
159 - C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa0s0bbbbb dsp_ea_imm5 + bchg #n,X:aa / bchg #n,Y:aa
\r
160 - C_DSPIM M_DSPPP NOPARMO %0000101110pppppp0s0bbbbb dsp_ea_imm5 + bchg #n,X:pp / bchg #n,Y:pp
\r
161 - C_DSPIM C_DD NOPARMO %00001011110001dd010bbbbb dsp_reg_imm5 + bchg #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
162 - C_DSPIM C_DDD NOPARMO %0000101111001ddd010bbbbb dsp_reg_imm5 + bchg #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
163 - C_DSPIM C_TTT NOPARMO %0000101111010ddd010bbbbb dsp_reg_imm5 + bchg #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
164 - C_DSPIM C_NNN NOPARMO %0000101111011ddd010bbbbb dsp_reg_imm5 + bchg #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
165 - C_DSPIM C_FFF NOPARMO %0000101111100ddd010bbbbb dsp_reg_imm5 + bchg #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
166 - C_DSPIM C_GGG NOPARMO %0000101111111ddd010bbbbb dsp_reg_imm5 bchg #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
167 bclr C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr0s0bbbbb dsp_ea_imm5 + bclr #n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
\r
168 - C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa0s0bbbbb dsp_ea_imm5 + bclr #n,X:aa / bclr #n,Y:aa
\r
169 - C_DSPIM M_DSPPP NOPARMO %0000101010pppppp0s0bbbbb dsp_ea_imm5 + bclr #n,X:pp / bclr #n,Y:pp
\r
170 - C_DSPIM C_DDD NOPARMO %0000101011001ddd010bbbbb dsp_reg_imm5 + bclr #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
171 - C_DSPIM C_DD NOPARMO %00001010110001dd010bbbbb dsp_reg_imm5 + bclr #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
172 - C_DSPIM C_TTT NOPARMO %0000101011010ddd010bbbbb dsp_reg_imm5 + bclr #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
173 - C_DSPIM C_NNN NOPARMO %0000101011011ddd010bbbbb dsp_reg_imm5 + bclr #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
174 - C_DSPIM C_FFF NOPARMO %0000101011100ddd010bbbbb dsp_reg_imm5 + bclr #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
175 - C_DSPIM C_GGG NOPARMO %0000101011111ddd010bbbbb dsp_reg_imm5 bclr #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
176 bset C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr0s1bbbbb dsp_ea_imm5 + bset #n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
\r
177 - C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa0s1bbbbb dsp_ea_imm5 + bset #n,X:aa / bset #n,Y:aa
\r
178 - C_DSPIM M_DSPPP NOPARMO %0000101010pppppp0s1bbbbb dsp_ea_imm5 + bset #n,X:pp / bset #n,Y:pp
\r
179 - C_DSPIM C_DD NOPARMO %00001010110001dd011bbbbb dsp_reg_imm5 + bset #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
180 - C_DSPIM C_DDD NOPARMO %0000101011001ddd011bbbbb dsp_reg_imm5 + bset #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
181 - C_DSPIM C_TTT NOPARMO %0000101011010ddd011bbbbb dsp_reg_imm5 + bset #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
182 - C_DSPIM C_NNN NOPARMO %0000101011011ddd011bbbbb dsp_reg_imm5 + bset #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
183 - C_DSPIM C_FFF NOPARMO %0000101011100ddd011bbbbb dsp_reg_imm5 + bset #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
184 - C_DSPIM C_GGG NOPARMO %0000101011111ddd011bbbbb dsp_reg_imm5 bset #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
185 btst C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr0s1bbbbb dsp_ea_imm5 + btst#n,X:ea / #n,Y:ea mmmrrr=ea, s=(X=0, Y=1), bbbbb=0-31
\r
186 - C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa0s1bbbbb dsp_ea_imm5 + btst #n,X:aa / btst #n,Y:aa
\r
187 - C_DSPIM M_DSPPP NOPARMO %0000101110pppppp0s1bbbbb dsp_ea_imm5 + btst #n,X:pp / btst #n,Y:pp
\r
188 - C_DSPIM C_DDD NOPARMO %0000101111001ddd011bbbbb dsp_reg_imm5 + btst #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
189 - C_DSPIM C_DD NOPARMO %00001011110001dd011bbbbb dsp_reg_imm5 + btst #n,D DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
190 - C_DSPIM C_TTT NOPARMO %0000101111010ddd011bbbbb dsp_reg_imm5 + btst #n,D TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
191 - C_DSPIM C_NNN NOPARMO %0000101111011ddd011bbbbb dsp_reg_imm5 + btst #n,D NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
192 - C_DSPIM C_FFF NOPARMO %0000101111100ddd011bbbbb dsp_reg_imm5 + btst #n,D FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
193 - C_DSPIM C_GGG NOPARMO %0000101111111ddd011bbbbb dsp_reg_imm5 btst #n,D GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
194 do M_DSPEA C_DSPABS24 NOPARMO %0000011001mmmrrr0s000000 dsp_ea_abs16 + DO X:ea,expr / DO Y:ea,expr mmmrrr=ea, s=(X=0, Y=1), expr=16bit in extension word
\r
195 - M_DSPAA C_DSPABS24 NOPARMO %0000011000aaaaaa0s000000 dsp_ea_abs16 + DO X:aa,expr / DO Y:aa,expr aaaaaa=aa, s=(X=0, Y=1), expr=16bit in extension word
\r
196 - C_DSPIM C_DSPABS24 NOPARMO %00000110iiiiiiii1000hhhh dsp_imm12_abs16 + DO #xxx,expr hhhhiiiiiiii=12bit immediate, expr=16bit in extension word
\r
197 - M_ALU24 C_DSPABS24 NOPARMO %0000011011000ddd00000000 dsp_alu24_abs16 + DO S,expr x0, x1, y0, y1
\r
198 - C_DDD C_DSPABS24 NOPARMO %0000011011001ddd00000000 dsp_reg_abs16 + DO S,expr DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
199 - C_TTT C_DSPABS24 NOPARMO %0000011011010ddd00000000 dsp_reg_abs16 + DO S,expr TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
200 - C_NNN C_DSPABS24 NOPARMO %0000011011011ddd00000000 dsp_reg_abs16 + DO S,expr NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
201 - C_FFF C_DSPABS24 NOPARMO %0000011011100ddd00000000 dsp_reg_abs16 + DO S,expr FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
202 - C_GGG C_DSPABS24 NOPARMO %0000011011111ddd00000000 dsp_reg_abs16 DO S,expr GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
203 rep C_DSPIM M_AM_NONE NOPARMO %00000110iiiiiiii1010hhhh dsp_imm12 + rep #xx
\r
204 - M_DSPEA M_AM_NONE NOPARMO %0000011001mmmrrr0s100000 dsp_ea + rep x:ea / y:ea
\r
205 - M_DSPAA M_AM_NONE NOPARMO %0000011000aaaaaa0s100000 dsp_ea + rep x:aa / y:aa
\r
206 - M_ALU24 M_AM_NONE NOPARMO %0000011011000ddd00100000 dsp_alu24 + rep S,expr x0, x1, y0, y1
\r
207 - C_DDD M_AM_NONE NOPARMO %0000011011001ddd00100000 dsp_reg + rep S DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
208 - C_TTT M_AM_NONE NOPARMO %0000011011010ddd00100000 dsp_reg + rep S TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
209 - C_NNN M_AM_NONE NOPARMO %0000011011011ddd00100000 dsp_reg + rep S NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
210 - C_FFF M_AM_NONE NOPARMO %0000011011100ddd00100000 dsp_reg + rep S FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
211 - C_GGG M_AM_NONE NOPARMO %0000011011111ddd00100000 dsp_reg rep S GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
212 jsclr C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr1s0bbbbb dsp_ea_imm5_abs16 + JSCLR #n,X:ea,xxxx / #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
\r
213 - C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa1s0bbbbb dsp_ea_imm5_abs16 + JSCLR #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
\r
214 - C_DSPIM M_DSPPP NOPARMO %0000101110pppppp1s0bbbbb dsp_ea_imm5_abs16 + JSCLR #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
\r
215 - C_DSPIM C_DD NOPARMO %00001011110001dd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
216 - C_DSPIM C_DDD NOPARMO %0000101111001ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
217 - C_DSPIM C_TTT NOPARMO %0000101111010ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
218 - C_DSPIM C_NNN NOPARMO %0000101111011ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
219 - C_DSPIM C_FFF NOPARMO %0000101111100ddd000bbbbb dsp_reg_imm5_abs16 + JSCLR #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
220 - C_DSPIM C_GGG NOPARMO %0000101111101ddd000bbbbb dsp_reg_imm5_abs16 JSCLR #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
221 jset C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr1s1bbbbb dsp_ea_imm5_abs16 + JSET #n,X:ea,xxxx / #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
\r
222 - C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa1s1bbbbb dsp_ea_imm5_abs16 + JSET #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
\r
223 - C_DSPIM M_DSPPP NOPARMO %0000101010pppppp1s1bbbbb dsp_ea_imm5_abs16 + JSET #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
\r
224 - C_DSPIM C_DD NOPARMO %00001010110001dd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
225 - C_DSPIM C_DDD NOPARMO %0000101011001ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
226 - C_DSPIM C_TTT NOPARMO %0000101011010ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
227 - C_DSPIM C_NNN NOPARMO %0000101011011ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
228 - C_DSPIM C_FFF NOPARMO %0000101011100ddd001bbbbb dsp_reg_imm5_abs16 + JSET #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
229 - C_DSPIM C_GGG NOPARMO %0000101011101ddd001bbbbb dsp_reg_imm5_abs16 JSET #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
230 jsset C_DSPIM M_DSPEA NOPARMO %0000101101mmmrrr1s1bbbbb dsp_ea_imm5_abs16 + JSSET #n,X:ea,xxxx / JSSET #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
\r
231 - C_DSPIM M_DSPAA NOPARMO %0000101100aaaaaa1s1bbbbb dsp_ea_imm5_abs16 + JSSET #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
\r
232 - C_DSPIM M_DSPPP NOPARMO %0000101110pppppp1s1bbbbb dsp_ea_imm5_abs16 + JSSET #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
\r
233 - C_DSPIM C_DD NOPARMO %00001011110001dd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
234 - C_DSPIM C_DDD NOPARMO %0000101111001ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
235 - C_DSPIM C_TTT NOPARMO %0000101111010ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
236 - C_DSPIM C_NNN NOPARMO %0000101111011ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
237 - C_DSPIM C_FFF NOPARMO %0000101111100ddd001bbbbb dsp_reg_imm5_abs16 + JSSET #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
238 - C_DSPIM C_GGG NOPARMO %0000101111101ddd001bbbbb dsp_reg_imm5_abs16 JSSET #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
239 jclr C_DSPIM M_DSPEA NOPARMO %0000101001mmmrrr1s0bbbbb dsp_ea_imm5_abs16 + JCLR #n,X:ea,xxxx / #n,Y:ea,xxxx n=bbbbb=0-31, ea=mmmrrr, xxxx=16bit extension, s=(X=0, Y=1)
\r
240 - C_DSPIM M_DSPAA NOPARMO %0000101000aaaaaa1s0bbbbb dsp_ea_imm5_abs16 + JCLR #n,X:aa,xxxx / #n,Y:aa,xxxx n=bbbbb=0-31, aa=aaaaaa=short address, s=(X=0, Y=1)
\r
241 - C_DSPIM M_DSPPP NOPARMO %0000101010pppppp1s0bbbbb dsp_ea_imm5_abs16 + JCLR #n,X:pp,xxxx / #n,Y:pp,xxxx n=bbbbb=0-31, pp=pppppp=short i/o address, s=(X=0, Y=1)
\r
242 - C_DSPIM C_DD NOPARMO %00001010110001dd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
243 - C_DSPIM C_DDD NOPARMO %0000101011001ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx DDD See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
244 - C_DSPIM C_TTT NOPARMO %0000101011010ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx TTT See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
245 - C_DSPIM C_NNN NOPARMO %0000101011011ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx NNN See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
246 - C_DSPIM C_FFF NOPARMO %0000101011100ddd000bbbbb dsp_reg_imm5_abs16 + JCLR #n,S,xxxx FFF See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
247 - C_DSPIM C_GGG NOPARMO %0000101011101ddd000bbbbb dsp_reg_imm5_abs16 JCLR #n,S,xxxx GGG See A.9 Instruction Encoding and Table A-18 for specific register encodings.
\r
248 lua M_DSPEA C_LUADST NOPARMO %00000100010mmrrr0001dddd dsp_ea_lua mmrrr=ea (subset), dddd=(bit 3=(0=Rn, 1=Nn), bits 2-0=0-7)
\r
249 norm M_DSPR M_ACC56 NOPARMO %0000000111011rrr0001d101 dsp_ab_rn norm Rn,D D=(a=0, b=1)
\r
250 move M_AM_NONE M_AM_NONE PARMOVE %mmmmmmmmmmmmmmmm00000000 dsp_self
\r
251 movec M_DSPIM8 C_MOVEC NOPARMO %00000101iiiiiiii101ddddd dsp_immmovec + move(c) #xx,d1
\r
252 - M_DSPEA C_MOVEC NOPARMO %0000010111mmmrrr0s1ddddd dsp_movec_ea + move(c) x:ea,d1 / y:ea,d1
\r
253 - C_MOVEC M_DSPEA NOPARMO %0000010101mmmrrr0s1ddddd dsp_movec_ea + move(c) s1,x:ea / s1,y:ea
\r
254 - C_DSPIM C_MOVEC NOPARMO %0000010111110100001ddddd dsp_movec_ea + move(c) #xxxx,d1
\r
255 - M_DSPAA C_MOVEC NOPARMO %0000010110aaaaaa0s1ddddd dsp_movec_aa + move(c) x:aa,d1 / y:aa,d1
\r
256 - C_MOVEC M_DSPAA NOPARMO %0000010100aaaaaa0s1ddddd dsp_movec_aa + move(c) s1,x:aa / s1,y:aa
\r
257 - C_MOVEC M_ALU24 NOPARMO %0000010001000eee101ddddd dsp_movec_reg + move(c) s1,d2
\r
258 - C_MOVEC C_DDD NOPARMO %0000010001001eee101ddddd dsp_movec_reg + move(c) s1,d2
\r
259 - C_MOVEC C_TTT NOPARMO %0000010001010eee101ddddd dsp_movec_reg + move(c) s1,d2
\r
260 - C_MOVEC C_NNN NOPARMO %0000010001011eee101ddddd dsp_movec_reg + move(c) s1,d2
\r
261 - C_MOVEC C_FFF NOPARMO %0000010001100eee101ddddd dsp_movec_reg + move(c) s1,d2
\r
262 - C_MOVEC C_GGG NOPARMO %0000010001111eee101ddddd dsp_movec_reg + move(c) s1,d2
\r
263 - M_ALU24 C_MOVEC NOPARMO %0000010011000eee101ddddd dsp_movec_reg + move(c) s2,d1
\r
264 - C_DDD C_MOVEC NOPARMO %0000010011001eee101ddddd dsp_movec_reg + move(c) s2,d1
\r
265 - C_TTT C_MOVEC NOPARMO %0000010011010eee101ddddd dsp_movec_reg + move(c) s2,d1
\r
266 - C_NNN C_MOVEC NOPARMO %0000010011011eee101ddddd dsp_movec_reg + move(c) s2,d1
\r
267 - C_FFF C_MOVEC NOPARMO %0000010011100eee101ddddd dsp_movec_reg + move(c) s2,d1
\r
268 - C_GGG C_MOVEC NOPARMO %0000010011111eee101ddddd dsp_movec_reg move(c) s2,d1
\r
269 movem M_ALU24 M_DSPEA NOPARMO %0000011101mmmrrr10000ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
270 - C_DDD M_DSPEA NOPARMO %0000011101mmmrrr10001ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
271 - C_TTT M_DSPEA NOPARMO %0000011101mmmrrr10010ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
272 - C_NNN M_DSPEA NOPARMO %0000011101mmmrrr10011ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
273 - C_FFF M_DSPEA NOPARMO %0000011101mmmrrr10100ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
274 - C_GGG M_DSPEA NOPARMO %0000011101mmmrrr10111ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
275 - M_DSPEA M_ALU24 NOPARMO %0000011111mmmrrr10000ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
276 - M_DSPEA C_DDD NOPARMO %0000011111mmmrrr10001ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
277 - M_DSPEA C_TTT NOPARMO %0000011111mmmrrr10010ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
278 - M_DSPEA C_NNN NOPARMO %0000011111mmmrrr10011ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
279 - M_DSPEA C_FFF NOPARMO %0000011111mmmrrr10100ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
280 - M_DSPEA C_GGG NOPARMO %0000011111mmmrrr10111ddd dsp_movem_ea + move(m) s,p:ea / p:ea,d
\r
281 - M_ALU24 M_DSPAA NOPARMO %0000011100aaaaaa00000ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
282 - C_DDD M_DSPAA NOPARMO %0000011100aaaaaa00001ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
283 - C_TTT M_DSPAA NOPARMO %0000011100aaaaaa00010ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
284 - C_NNN M_DSPAA NOPARMO %0000011100aaaaaa00011ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
285 - C_FFF M_DSPAA NOPARMO %0000011100aaaaaa00100ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
286 - C_GGG M_DSPAA NOPARMO %0000011100aaaaaa00111ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
287 - M_DSPAA M_ALU24 NOPARMO %0000011110aaaaaa00000ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
288 - M_DSPAA C_DDD NOPARMO %0000011110aaaaaa00001ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
289 - M_DSPAA C_TTT NOPARMO %0000011110aaaaaa00010ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
290 - M_DSPAA C_NNN NOPARMO %0000011110aaaaaa00011ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
291 - M_DSPAA C_FFF NOPARMO %0000011110aaaaaa00100ddd dsp_movem_aa + move(m) s,p:aa / p:aa,d
\r
292 - M_DSPAA C_GGG NOPARMO %0000011110aaaaaa00111ddd dsp_movem_aa move(m) s,p:aa / p:aa,d
\r
293 mac M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk10 dsp_mult mac -+s1,s2,d / mac -+s2,s1,d
\r
294 macr M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk11 dsp_mult macr -+s1,s2,d / macr -+s2,s1,d
\r
295 mpy M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk00 dsp_mult mpy -+s1,d2,d / -+s2,s1,d
\r
296 mpyr M_ALU24 M_ALU24 PARMOVE %mmmmmmmmmmmmmmmm1qqqdk01 dsp_mult mpyr -+s1,d2,d / -+s2,s1,d
\r
297 movep M_DSPEA M_DSPPP NOPARMO %0000100s11mmmrrr1spppppp dsp_movep_ea + movep p:ea,x:pp / p:ea,y:pp
\r
298 - M_DSPAA M_DSPPP NOPARMO %0000100s11mmmrrr1spppppp dsp_movep_ea + movep p:aa,x:pp / p:aa,y:pp
\r
299 - M_DSPPP M_DSPEA NOPARMO %0000100s01mmmrrr1spppppp dsp_movep_ea + x:pp,p:ea / y:pp,p:ea
\r
300 - M_DSPPP M_DSPPP NOPARMO %0000100s01mmmrrr1spppppp dsp_movep_ea + x:pp,p:ea / y:pp,p:ea
\r
301 - M_DSPPP M_DSPAA NOPARMO %0000100s01mmmrrr1spppppp dsp_movep_ea + x:pp,p:aa / y:pp,p:aa
\r
302 - C_DSPIM M_DSPPP NOPARMO %0000100s111101001spppppp dsp_movep_ea + #xxxxxx,x:pp / #xxxxxx,y:pp
\r
303 - C_DSPIM M_DSPEA NOPARMO %0000100s111101001spppppp dsp_movep_ea + #xxxxxx,x:pp / #xxxxxx,y:pp
\r
304 - M_ALU24 M_DSPPP NOPARMO %0000100s11000ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
\r
305 - C_DDD M_DSPPP NOPARMO %0000100s11001ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
\r
306 - C_TTT M_DSPPP NOPARMO %0000100s11010ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
\r
307 - C_NNN M_DSPPP NOPARMO %0000100s11011ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
\r
308 - C_FFF M_DSPPP NOPARMO %0000100s11100ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
\r
309 - C_GGG M_DSPPP NOPARMO %0000100s11111ddd0spppppp dsp_movep_reg + movep s,x:pp / s,y:pp
\r
310 - M_DSPPP M_ALU24 NOPARMO %0000100s01000ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
\r
311 - M_DSPPP C_DDD NOPARMO %0000100s01001ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
\r
312 - M_DSPPP C_TTT NOPARMO %0000100s01010ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
\r
313 - M_DSPPP C_NNN NOPARMO %0000100s01011ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
\r
314 - M_DSPPP C_FFF NOPARMO %0000100s01100ddd0spppppp dsp_movep_reg + movep x:pp,d / y:pp,d
\r
315 - M_DSPPP C_GGG NOPARMO %0000100s01111ddd0spppppp dsp_movep_reg movep x:pp,d / y:pp,d
\r
316 debug M_AM_NONE M_AM_NONE NOPARMO %000000000000001000000000 dsp_self
\r
317 debugcc M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000000 dsp_self
\r
318 debughs M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000000 dsp_self
\r
319 debugcs M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001000 dsp_self
\r
320 debuglo M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001000 dsp_self
\r
321 debugec M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000101 dsp_self
\r
322 debugeq M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001010 dsp_self
\r
323 debuges M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001101 dsp_self
\r
324 debugge M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000001 dsp_self
\r
325 debuggt M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000111 dsp_self
\r
326 debuglc M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000110 dsp_self
\r
327 debugle M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001111 dsp_self
\r
328 debugls M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001110 dsp_self
\r
329 debuglt M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001001 dsp_self
\r
330 debugmi M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001011 dsp_self
\r
331 debugne M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000010 dsp_self
\r
332 debugnr M_AM_NONE M_AM_NONE NOPARMO %000000000000001100001100 dsp_self
\r
333 debugpl M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000011 dsp_self
\r
334 debugnn M_AM_NONE M_AM_NONE NOPARMO %000000000000001100000100 dsp_self
\r
projects / rmac / blob