X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fv6809.cpp.bak;fp=src%2Fv6809.cpp.bak;h=0000000000000000000000000000000000000000;hb=8dafbf94c7bc84dae635f9dabfc9be5424e49e68;hp=0d503b4c78130487711a806e1451b9476ccf6698;hpb=e3ad811139308bfe8a818cf5e42e7553785fea82;p=stargem2 diff --git a/src/v6809.cpp.bak b/src/v6809.cpp.bak deleted file mode 100755 index 0d503b4..0000000 --- a/src/v6809.cpp.bak +++ /dev/null @@ -1,2840 +0,0 @@ -// -// Virtual 6809 v1.2P (Last build: 2/2/2004) -// -// by James L. Hammons -// -// (c) 1997 Underground Software -// - -#include // To make this really clean, we'd have to make our own memcpy, etc... -#include "v6809.h" - -// Global defs (needed because functions can only return one value. -// Maybe you could use a struct to pass multiple values, but -// what a pain in the ass! This way makes a little more sense -// to me.) - -//BYTE * ram, * rom; // RAM & ROM image spaces (64K each) -WORD pcr, xr, yr, sr, ur; // Double byte registers -BYTE ccr, ar, br, dpr; -long iclock; -bool /*color_reg = false,*/ illegal = false, inter; - -// Instead of the above, we can use a private struct for our CPU state... - -static V6809REGS regs; - -static WORD addr; // Temporary variables common to all funcs... -static BYTE tmp; - -extern BYTE Fetch(); // You need to define these functions -//extern WORD FetchW(); // externally because every hardware situation -extern BYTE RdMem(WORD); // is going to be different... -extern void WrMem(WORD, BYTE); - -// Internal function prototypes - -WORD ReadEXG(BYTE); // Read TFR/EXG post byte -void WriteEXG(BYTE, WORD); // Set TFR/EXG data -WORD DecodeReg(BYTE); // Decode register data -WORD DecodeIDX(BYTE); // Decode IDX data - -// -// Fetch word function -// -WORD FetchW(void) -{ - return (WORD)(Fetch() << 8) | Fetch(); -} - -// -// Return signed byte from unsigned -// -int SignedB(BYTE b) -{ - return (b & 0x80 ? b - 256 : b); -} - -// -// Return signed word from unsigned -// -int SignedW(WORD w) -{ - return (w & 0x8000 ? w - 65536 : w); -} - -// -// Function to read TFR/EXG post byte -// -WORD ReadEXG(BYTE code) -{ - WORD retval; - - switch(code) - { - case 0: retval = (ar<<8) | br; break; - case 1: retval = xr; break; - case 2: retval = yr; break; - case 3: retval = ur; break; - case 4: retval = sr; break; - case 5: retval = pcr; break; - case 8: retval = ar; break; - case 9: retval = br; break; - case 10: retval = ccr; break; - case 11: retval = dpr; break; - default: retval = 0xFF; - } - return(retval); -} - -// -// Function to set TFR/EXG data -// -void WriteEXG(BYTE code, WORD data) -{ - switch(code) - { - case 0: - ar = data >> 8, br = data & 0xFF; break; - case 1: - xr = data; break; - case 2: - yr = data; break; - case 3: - ur = data; break; - case 4: - sr = data; break; - case 5: - pcr = data; break; - case 8: - ar = data & 0xFF; break; - case 9: - br = data & 0xFF; break; - case 10: - ccr = data & 0xFF; break; - case 11: - dpr = data & 0xFF; break; - } -} - -// -// Function to decode register data -// -WORD DecodeReg(BYTE reg) -{ - WORD retval; - - switch (reg) - { - case 0: - retval = xr; break; - case 1: - retval = yr; break; - case 2: - retval = ur; break; - case 3: - retval = sr; break; - } - - return retval; -} - -// -// Function to decode IDX data -// -WORD DecodeIDX(BYTE code) -{ - WORD addr, woff; - BYTE reg = (code&0x60)>>5, idxind = (code&0x10)>>4, lo_nyb = code&0x0F; - - if (!(code&0x80)) // Hi bit unset? Then decode 4 bit offset - { - addr = DecodeReg(reg) + (idxind ? lo_nyb-16 : lo_nyb); - } - else - { - if (idxind) - { - switch(lo_nyb) - { - case 1: { woff = DecodeReg(reg); - addr = (RdMem(woff)<<8) | RdMem(woff+1); - switch(reg) - { - case 0: xr++; xr++; break; - case 1: yr++; yr++; break; - case 2: ur++; ur++; break; - case 3: sr++; sr++; break; - } - break; } - case 3: { switch(reg) - { - case 0: xr--; xr--; break; - case 1: yr--; yr--; break; - case 2: ur--; ur--; break; - case 3: sr--; sr--; break; - } - woff = DecodeReg(reg); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 4: { woff = DecodeReg(reg); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 5: { woff = DecodeReg(reg) + SignedB(br); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 6: { woff = DecodeReg(reg) + SignedB(ar); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 8: { woff = DecodeReg(reg) + SignedB(Fetch()); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 9: { woff = DecodeReg(reg) + SignedW(FetchW()); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 11: { woff = DecodeReg(reg) + SignedW((ar<<8) | br); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 12: { woff = pcr + SignedB(Fetch()); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 13: { woff = pcr + SignedW(FetchW()); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - case 15: { woff = FetchW(); - addr = (RdMem(woff)<<8) | RdMem(woff+1); break; } - } - } - else - { - switch(lo_nyb) - { - case 0: { addr = DecodeReg(reg); - switch(reg) - { - case 0: xr++; break; - case 1: yr++; break; - case 2: ur++; break; - case 3: sr++; break; - } - break; } - case 1: { addr = DecodeReg(reg); - switch(reg) - { - case 0: xr++; xr++; break; - case 1: yr++; yr++; break; - case 2: ur++; ur++; break; - case 3: sr++; sr++; break; - } - break; } - case 2: { switch(reg) - { - case 0: xr--; break; - case 1: yr--; break; - case 2: ur--; break; - case 3: sr--; break; - } - addr = DecodeReg(reg); break; } - case 3: { switch(reg) - { - case 0: xr--; xr--; break; - case 1: yr--; yr--; break; - case 2: ur--; ur--; break; - case 3: sr--; sr--; break; - } - addr = DecodeReg(reg); break; } - case 4: { addr = DecodeReg(reg); break; } - case 5: { addr = DecodeReg(reg) + SignedB(br); break; } - case 6: { addr = DecodeReg(reg) + SignedB(ar); break; } - case 8: { addr = DecodeReg(reg) + SignedB(Fetch()); break; } - case 9: { addr = DecodeReg(reg) + SignedW(FetchW()); break; } - case 11: { addr = DecodeReg(reg) + SignedW((ar<<8) | br); break; } - case 12: { addr = pcr + SignedB(Fetch()); break; } - case 13: { addr = pcr + SignedW(FetchW()); break; } - } - } - } - return(addr); -} - -// -// Page zero instructions... -// - -void Op00(void) // NEG DP -{ - addr = (dpr<<8) | Fetch(); - tmp = 256 - RdMem(addr); - WrMem(addr, tmp); - (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (tmp > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry - iclock += 6; -} -void Op03(void) // COM DP -{ - addr = (dpr<<8) | Fetch(); - tmp = 0xFF ^ RdMem(addr); - WrMem(addr, tmp); - ccr &= 0xFD; ccr |= 0x01; // CLV SEC - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op04(void) // LSR DP -{ - addr = (dpr<<8) | Fetch(); - tmp = RdMem(addr); - (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry - tmp >>= 1; WrMem(addr, tmp); - ccr &= 0xF7; // CLN - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - iclock += 6; -} -void Op06(void) // ROR DP -{ - addr = (dpr<<8) | Fetch(); BYTE tmp2 = RdMem(addr); - tmp = (tmp2>>1) + (ccr&0x01)*128; - WrMem(addr, tmp); - (tmp2&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op07(void) // ASR DP -{ - addr = (dpr<<8) | Fetch(); tmp = RdMem(addr); - (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - tmp >>= 1; - if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set - WrMem(addr, tmp); - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op08(void) // LSL DP -{ - addr = (dpr<<8) | Fetch(); // NEEDS OVERFLOW ADJUSTMENT - tmp = RdMem(addr); - (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - tmp <<= 1; - WrMem(addr, tmp); - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op09(void) // ROL DP -{ - addr = (dpr<<8) | Fetch(); BYTE tmp2 = RdMem(addr); - tmp = (tmp2<<1) + (ccr&0x01); - WrMem(addr, tmp); - (tmp2&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - ((tmp2&0x80)^((tmp2<<1)&0x80) ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op0A(void) // DEC DP -{ - addr = (dpr<<8) | Fetch(); - tmp = RdMem(addr) - 1; - WrMem(addr, tmp); - (tmp == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op0C(void) // INC DP -{ - addr = (dpr<<8) | Fetch(); - tmp = RdMem(addr) + 1; - WrMem(addr, tmp); - (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op0D(void) // TST DP -{ - tmp = RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // CLV - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op0E(void) // JMP DP -{ - pcr = (dpr<<8) | Fetch(); - iclock += 3; -} -void Op0F(void) // CLR DP -{ - WrMem((dpr<<8)|Fetch(), 0); - ccr &= 0xF0; ccr |= 0x04; // CLN, SEZ, CLV, CLC - iclock += 6; -} -void Op12(void) // NOP -{ - iclock += 2; -} -void Op13(void) // SYNC -{ - iclock += 2; -} -void Op16(void) // LBRA -{ - pcr += SignedW(FetchW()); - iclock += 5; -} -void Op17(void) // LBSR -{ - addr = FetchW(); - WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); - pcr += SignedW(addr); - iclock += 9; -} -void Op19(void) // DAA -{ - if ((ccr&0x20) || ((ar&0x0F) > 0x09)) // H set or lo nyb too big? - { - ar += 0x06; ccr |= 0x20; // Then adjust & set half carry - } - if ((ccr&0x01) || (ar > 0x9F)) // C set or hi nyb too big? - { - ar += 0x60; ccr |= 0x01; // Then adjust & set carry - } - ccr &= 0xF1; // CL NZV - if (ar == 0) ccr |= 0x04; // Adjust Zero flag - if (ar&0x80) ccr |= 0x08; // Adjust Negative flag - iclock += 2; -} -void Op1A(void) // ORCC # -{ - ccr |= Fetch(); - iclock += 3; -} -void Op1C(void) // ANDCC # -{ - ccr &= Fetch(); - iclock += 3; -} -void Op1D(void) // SEX -{ - (br&0x80 ? ar = 0xFF : ar = 0x00); - ((ar|br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op1E(void) // EXG -{ - tmp = Fetch(); - addr = ReadEXG(tmp>>4); WriteEXG(tmp>>4, ReadEXG(tmp&0xF)); - WriteEXG(tmp&0xF, addr); - iclock += 8; -} -void Op1F(void) // TFR -{ - tmp = Fetch(); - WriteEXG(tmp&0xF, ReadEXG(tmp>>4)); - iclock += 7; -} -void Op20(void) // BRA -{ - pcr += SignedB(Fetch()); // Branch always - iclock += 3; -} -void Op21(void) // BRN -{ - Fetch(); - iclock += 3; -} -void Op22(void) // BHI -{ - tmp = Fetch(); - if (!(ccr&0x05)) pcr += SignedB(tmp); - iclock += 3; -} -void Op23(void) // BLS -{ - tmp = Fetch(); - if (ccr&0x05) pcr += SignedB(tmp); - iclock += 3; -} -void Op24(void) // BCC (BHS) -{ - tmp = Fetch(); - if (!(ccr&0x01)) pcr += SignedB(tmp); - iclock += 3; -} -void Op25(void) // BCS (BLO) -{ - tmp = Fetch(); - if (ccr&0x01) pcr += SignedB(tmp); - iclock += 3; -} -void Op26(void) // BNE -{ - tmp = Fetch(); - if (!(ccr&0x04)) pcr += SignedB(tmp); - iclock += 3; -} -void Op27(void) // BEQ -{ - tmp = Fetch(); - if (ccr&0x04) pcr += SignedB(tmp); - iclock += 3; -} -void Op28(void) // BVC -{ - tmp = Fetch(); - if (!(ccr&0x02)) pcr += SignedB(tmp); - iclock += 3; -} -void Op29(void) // BVS -{ - tmp = Fetch(); - if (ccr&0x02) pcr += SignedB(tmp); - iclock += 3; -} -void Op2A(void) // BPL -{ - tmp = Fetch(); - if (!(ccr&0x08)) pcr += SignedB(tmp); - iclock += 3; -} -void Op2B(void) // BMI -{ - tmp = Fetch(); - if (ccr&0x08) pcr += SignedB(tmp); - iclock += 3; -} -void Op2C(void) // BGE -{ - tmp = Fetch(); - if (!(((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedB(tmp); - iclock += 3; -} -void Op2D(void) // BLT -{ - tmp = Fetch(); - if (((ccr&0x08) >> 2) ^ (ccr&0x02)) pcr += SignedB(tmp); - iclock += 3; -} -void Op2E(void) // BGT -{ - tmp = Fetch(); - if (!((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02)))) pcr += SignedB(tmp); - iclock += 3; -} -void Op2F(void) // BLE -{ - tmp = Fetch(); - if ((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedB(tmp); - iclock += 3; -} -void Op30(void) // LEAX -{ - xr = DecodeIDX(Fetch()); - (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - iclock += 4; -} -void Op31(void) // LEAY -{ - yr = DecodeIDX(Fetch()); - (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - iclock += 4; -} -void Op32(void) // LEAS -{ - sr = DecodeIDX(Fetch()); - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - iclock += 4; -} -void Op33(void) // LEAU -{ - ur = DecodeIDX(Fetch()); - (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - iclock += 4; -} -void Op34(void) // PSHS -{ - tmp = Fetch(); - if (tmp&0x80) { WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); } - if (tmp&0x40) { WrMem(--sr, ur&0xFF); WrMem(--sr, ur>>8); } - if (tmp&0x20) { WrMem(--sr, yr&0xFF); WrMem(--sr, yr>>8); } - if (tmp&0x10) { WrMem(--sr, xr&0xFF); WrMem(--sr, xr>>8); } - if (tmp&0x08) WrMem(--sr, dpr); - if (tmp&0x04) WrMem(--sr, br); - if (tmp&0x02) WrMem(--sr, ar); - if (tmp&0x01) WrMem(--sr, ccr); - iclock += 5; -} -void Op35(void) // PULS -{ - tmp = Fetch(); - if (tmp&0x01) ccr = RdMem(sr++); - if (tmp&0x02) ar = RdMem(sr++); - if (tmp&0x04) br = RdMem(sr++); - if (tmp&0x08) dpr = RdMem(sr++); - if (tmp&0x10) xr = (RdMem(sr++)<<8) | RdMem(sr++); - if (tmp&0x20) yr = (RdMem(sr++)<<8) | RdMem(sr++); - if (tmp&0x40) ur = (RdMem(sr++)<<8) | RdMem(sr++); - if (tmp&0x80) pcr = (RdMem(sr++)<<8) | RdMem(sr++); - iclock += 5; -} -void Op36(void) // PSHU -{ - tmp = Fetch(); - if (tmp&0x80) { WrMem(--ur, pcr&0xFF); WrMem(--ur, pcr>>8); } - if (tmp&0x40) { WrMem(--ur, sr&0xFF); WrMem(--ur, sr>>8); } - if (tmp&0x20) { WrMem(--ur, yr&0xFF); WrMem(--ur, yr>>8); } - if (tmp&0x10) { WrMem(--ur, xr&0xFF); WrMem(--ur, xr>>8); } - if (tmp&0x08) WrMem(--ur, dpr); - if (tmp&0x04) WrMem(--ur, br); - if (tmp&0x02) WrMem(--ur, ar); - if (tmp&0x01) WrMem(--ur, ccr); - iclock += 5; -} -void Op37(void) // PULU -{ - tmp = Fetch(); - if (tmp&0x01) ccr = RdMem(ur++); - if (tmp&0x02) ar = RdMem(ur++); - if (tmp&0x04) br = RdMem(ur++); - if (tmp&0x08) dpr = RdMem(ur++); - if (tmp&0x10) xr = (RdMem(ur++)<<8) | RdMem(ur++); - if (tmp&0x20) yr = (RdMem(ur++)<<8) | RdMem(ur++); - if (tmp&0x40) sr = (RdMem(ur++)<<8) | RdMem(ur++); - if (tmp&0x80) pcr = (RdMem(ur++)<<8) | RdMem(ur++); - iclock += 5; -} -void Op39(void) // RTS -{ - pcr = (RdMem(sr++)<<8) | RdMem(sr++); - iclock += 5; -} -void Op3A(void) // ABX -{ - xr += br; - iclock += 3; -} -void Op3B(void) // RTI -{ - ccr = RdMem(sr++); - if (ccr&0x80) // If E flag set, pull all regs - { - ar = RdMem(sr++); br = RdMem(sr++); dpr = RdMem(sr++); - xr = (RdMem(sr++)<<8) | RdMem(sr++); - yr = (RdMem(sr++)<<8) | RdMem(sr++); - ur = (RdMem(sr++)<<8) | RdMem(sr++); - iclock += 15; - } - else - { - iclock += 6; - } - pcr = (RdMem(sr++)<<8) | RdMem(sr++); -} -void Op3C(void) // CWAI -{ - ccr &= Fetch(); ccr |= 0x80; - iclock += 1000000; // Force interrupt -} -void Op3D(void) // MUL -{ - addr = ar * br; ar = addr>>8; br = addr&0xFF; - (addr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero - (br&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry - iclock += 11; -} -void Op3E(void) // RESET -{ -} -void Op3F(void) // SWI -{ -} -void Op40(void) // NEGA -{ - ar = 256 - ar; - (ar > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry - (ar == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op43(void) // COMA -{ - ar ^= 0xFF; - ccr &= 0xFD; ccr |= 0x01; // CLV, SEC - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op44(void) // LSRA -{ - (ar&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry - ar >>= 1; - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op46(void) // RORA -{ - tmp = ar; ar = (tmp>>1) + (ccr&0x01)*128; - (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op47(void) // ASRA -{ - (ar&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - ar >>= 1; // Do the shift - if (ar&0x40) ar |= 0x80; // Set neg if it was set - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op48(void) // LSLA [Keep checking from here...] -{ - (ar&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - ar <<= 1; - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op49(void) // ROLA -{ - tmp = ar; ar = (tmp<<1) + (ccr&0x01); - (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op4A(void) // DECA -{ - ar--; - (ar == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op4C(void) // INCA - { - ar++; - (ar == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op4D(void) // TSTA - { - ccr &= 0xFD; // Clear oVerflow flag - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op4F(void) // CLRA -{ - ar = 0; - ccr &= 0xF0; ccr |= 0x04; // Set NZVC - iclock += 2; -} -void Op50(void) // NEGB - { - br = 256 - br; -// ((br^tmp)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Adjust H carry - (br == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (br > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry - iclock += 2; - } -void Op53(void) // COMB - { - br ^= 0xFF; - ccr &= 0xFD; ccr |= 0x01; // CLV, SEC - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op54(void) // LSRB - { - (br&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry - br >>= 1; - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op56(void) // RORB - { - tmp = br; br = (br >> 1) + (ccr&0x01)*128; - (tmp&0x01 ? ccr |=0x01 : ccr &= 0xFE); // Shift bit into carry - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op57(void) // ASRB - { - (br&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - br >>= 1; // Do the shift - if (br&0x40) br |= 0x80; // Set neg if it was set - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op58(void) // LSLB - { - (br&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - br <<= 1; - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op59(void) // ROLB -{ - tmp = br; - br = (tmp<<1) + (ccr&0x01); - (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op5A(void) // DECB - { - br--; - (br == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op5C(void) // INCB - { - br++; - (br == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op5D(void) // TSTB - { - ccr &= 0xFD; // Clear oVerflow flag - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op5F(void) // CLRB - { - br = 0; - ccr &= 0xF0; ccr |= 0x04; // Set NZVC - iclock += 2; - } -void Op60(void) // NEG IDX - { - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr); BYTE res = 256 - tmp; - WrMem(addr, res); -// ((res^tmp)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Adjust H carry - (res == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (res == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (res&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (res > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry - iclock += 6; - } -void Op63(void) // COM IDX - { - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr) ^ 0xFF; - WrMem(addr, tmp); - ccr &= 0xFD; ccr |= 0x01; // CLV, SEC - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op64(void) // LSR IDX - { - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr); - (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry - tmp >>= 1; WrMem(addr, tmp); - ccr &= 0xF7; // CLN - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - iclock += 6; - } -void Op66(void) // ROR IDX - { - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr); BYTE tmp2 = tmp; - tmp = (tmp >> 1) + (ccr&0x01)*128; - WrMem(addr, tmp); - (tmp2&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op67(void) // ASR IDX - { - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr); - (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - tmp >>= 1; - if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set - WrMem(addr, tmp); - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op68(void) // LSL IDX - { - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr); - (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - tmp <<= 1; - WrMem(addr, tmp); - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op69(void) // ROL IDX -{ - BYTE tmp2 = RdMem(DecodeIDX(Fetch())); - tmp = (tmp2<<1) + (ccr&0x01); - WrMem(addr, tmp); - (tmp2&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void Op6A(void) // DEC IDX - { - BYTE tmp; WORD addr; - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr) - 1; - WrMem(addr, tmp); - (tmp == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op6C(void) // INC IDX - { - addr = DecodeIDX(Fetch()); - tmp = RdMem(addr) + 1; - WrMem(addr, tmp); - (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op6D(void) // TST IDX - { - tmp = RdMem(DecodeIDX(Fetch())); - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op6E(void) // JMP IDX -{ - pcr = DecodeIDX(Fetch()); - iclock += 3; -} -void Op6F(void) // CLR IDX -{ - addr = DecodeIDX(Fetch()); - WrMem(addr, 0); - ccr &= 0xF0; ccr |= 0x04; // Set NZVC - iclock += 6; -} -void Op70(void) // NEG ABS - { - addr = FetchW(); - tmp = RdMem(addr); BYTE res = 256 - tmp; - WrMem(addr, res); - (res == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (res == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (res&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (res > 0x7F ? ccr |= 0x01 : ccr &= 0xFE); // Adjust carry - iclock += 7; - } -void Op73(void) // COM ABS - { - addr = FetchW(); - tmp = RdMem(addr) ^ 0xFF; - WrMem(addr, tmp); - ccr &= 0xFD; ccr |= 0x01; // CLV, SEC - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op74(void) // LSR ABS - { - addr = FetchW(); - tmp = RdMem(addr); - (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift low bit into carry - tmp >>= 1; WrMem(addr, tmp); - ccr &= 0xF7; // CLN - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - iclock += 7; - } -void Op76(void) // ROR ABS - { - BYTE tmp; WORD addr; - addr = FetchW(); - tmp = RdMem(addr); BYTE tmp2 = tmp; - tmp = (tmp >> 1) + (ccr&0x01)*128; - WrMem(addr, tmp); - (tmp2&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op77(void) // ASR ABS - { - BYTE tmp; WORD addr; - addr = FetchW(); - tmp = RdMem(addr); - (tmp&0x01 ? ccr |= 0x01 : ccr &= 0xFE); // Shift bit into carry - tmp >>= 1; - if (tmp&0x40) tmp |= 0x80; // Set Neg if it was set - WrMem(addr, tmp); - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op78(void) // LSL ABS - { - BYTE tmp; WORD addr; - addr = FetchW(); - tmp = RdMem(addr); - (tmp&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - tmp <<= 1; - WrMem(addr, tmp); - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op79(void) // ROL ABS -{ - BYTE tmp2 = RdMem(FetchW()); - tmp = (tmp2<<1) + (ccr&0x01); - WrMem(addr, tmp); - (tmp2&0x80 ? ccr |= 0x01 : ccr &= 0xFE); // Shift hi bit into carry - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; -} -void Op7A(void) // DEC ABS - { - BYTE tmp; WORD addr; - addr = FetchW(); - tmp = RdMem(addr) - 1; - WrMem(addr, tmp); - (tmp == 0x7F ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op7C(void) // INC ABS - { - BYTE tmp; WORD addr; - addr = FetchW(); - tmp = RdMem(addr) + 1; - WrMem(addr, tmp); - (tmp == 0x80 ? ccr |= 0x02 : ccr &= 0xFD); // Adjust oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } - -void Op7D(void) // TST ABS -{ - BYTE tmp = RdMem(FetchW()); - - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - - iclock += 7; -} - -void Op7E(void) // JMP ABS -{ - pcr = FetchW(); - iclock += 3; -} -void Op7F(void) // CLR ABS - { - WrMem(FetchW(), 0); - ccr &= 0xF0; ccr |= 0x04; // Set NZVC - iclock += 7; - } -void Op80(void) // SUBA # -{ - BYTE tmp = Fetch(); BYTE as = ar; - ar -= tmp; - (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op81(void) // CMPA # -{ - tmp = Fetch(); - BYTE db = ar - tmp; - (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op82(void) // SBCA # -{ - tmp = Fetch(); BYTE as = ar; - ar = ar - tmp - (ccr&0x01); - (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void Op83(void) // SUBD # -{ - addr = FetchW(); WORD dr = (ar<<8)|br, ds = dr; - dr -= addr; - (ds < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ds^addr^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ar = dr>>8; br = dr&0xFF; - iclock += 4; -} -void Op84(void) // ANDA # - { - ar &= Fetch(); - ccr &= 0xFD; // Clear oVerflow flag - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op85(void) // BITA # - { - tmp = ar & Fetch(); - ccr &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op86(void) // LDA # - { - ar = Fetch(); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op88(void) // EORA # - { - ar ^= Fetch(); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op89(void) // ADCA # -{ - tmp = Fetch(); - addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - ar = addr & 0xFF; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative - iclock += 2; -} -void Op8A(void) // ORA # - { - ar |= Fetch(); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void Op8B(void) // ADDA # -{ - tmp = Fetch(); addr = ar + tmp; - (addr > 0xFF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - ar = addr & 0xFF; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 2; -} -void Op8C(void) // CMPX # -{ - addr = FetchW(); - WORD dw = xr - addr; - (xr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((xr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; -} -void Op8D(void) // BSR - { - tmp = Fetch(); - WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); - pcr += SignedB(tmp); - iclock += 7; - } -void Op8E(void) // LDX # - { - xr = FetchW(); - ccr &= 0xFD; // CLV - (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 3; - } -void Op90(void) // SUBA DP - { - tmp = RdMem((dpr<<8)|Fetch()); BYTE as = ar; - ar -= tmp; - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; - } -void Op91(void) // CMPA DP - { - tmp = RdMem((dpr<<8)|Fetch()); - BYTE db = ar - tmp; - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; - } -void Op92(void) // SBCA DP -{ - tmp = RdMem((dpr<<8)|Fetch()); BYTE as = ar; - ar = ar - tmp - (ccr&0x01); - (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; -} -void Op93(void) // SUBD DP -{ - addr = (dpr<<8)|Fetch(); WORD dr = (ar<<8)|br, ds = dr; - WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1); - dr -= adr2; - (ds < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ar = dr>>8; br = dr&0xFF; - iclock += 6; -} -void Op94(void) // ANDA DP -{ - ar &= RdMem((dpr<<8)|Fetch()); - ccr &= 0xF1; // CLV CLZ CLN - if (ar == 0) ccr |= 0x04; // Adjust Zero flag - if (ar&0x80) ccr |= 0x08; // Adjust Negative flag - iclock += 4; -} -void Op95(void) // BITA DP - { - tmp = ar & RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void Op96(void) // LDA DP -{ - ar = RdMem((dpr<<8)|Fetch()); - ccr &= 0xF1; // CLN CLZ CLV - if (ar == 0) ccr |= 0x04; // Set Zero flag - if (ar&0x80) ccr |= 0x08; // Set Negative flag - iclock += 4; -} -void Op97(void) // STA DP - { - WrMem((dpr<<8)|Fetch(), ar); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void Op98(void) // EORA DP - { - ar ^= RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void Op99(void) // ADCA DP -{ - tmp = RdMem((dpr<<8)|Fetch()); - addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - ar = addr & 0xFF; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative - iclock += 4; -} -void Op9A(void) // ORA DP - { - ar |= RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void Op9B(void) // ADDA DP -{ - tmp = RdMem((dpr<<8)|Fetch()); - addr = (WORD)ar + (WORD)tmp; - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - ar = addr & 0xFF; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 4; -} -void Op9C(void) // CMPX DP - { - addr = (dpr<<8)|Fetch(); - WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1); - WORD dw = xr - adr2; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (xr < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((xr^adr2^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 6; - } -void Op9D(void) // JSR DP - { - addr = (dpr<<8) | Fetch(); - WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); - pcr = addr; // JSR to DP location... - iclock += 7; - } -void Op9E(void) // LDX DP - { - addr = (dpr<<8) | Fetch(); - xr = (RdMem(addr) << 8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void Op9F(void) // STX DP - { - addr = (dpr<<8) | Fetch(); - WrMem(addr, xr>>8); WrMem(addr+1, xr&0xFF); - ccr &= 0xFD; // CLV - (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void OpA0(void) // SUBA IDX - { - tmp = RdMem(DecodeIDX(Fetch())); BYTE as = ar; - ar -= tmp; - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; - } -void OpA1(void) // CMPA IDX - { - tmp = RdMem(DecodeIDX(Fetch())); - BYTE db = ar - tmp; - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; - } -void OpA2(void) // SBCA IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); BYTE as = ar; - ar = ar - tmp - (ccr&0x01); - (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; -} -void OpA3(void) // SUBD IDX -{ - addr = DecodeIDX(Fetch()); WORD dr = (ar<<8)|br, ds = dr; - WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1); - dr -= adr2; - (ds < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ar = dr>>8; br = dr&0xFF; - iclock += 6; -} -void OpA4(void) // ANDA IDX - { - ar &= RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // Clear oVerflow flag - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpA5(void) // BITA IDX - { - tmp = ar & RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpA6(void) // LDA IDX -{ - ar = RdMem(DecodeIDX(Fetch())); - ccr &= 0xF1; // CLV CLZ CLN - if (ar == 0) ccr |= 0x04; // Set Zero flag - if (ar&0x80) ccr |= 0x08; // Set Negative flag - iclock += 4; -} -void OpA7(void) // STA IDX -{ - WrMem(DecodeIDX(Fetch()), ar); - ccr &= 0xF1; // CLV CLZ CLN - if (ar == 0) ccr |= 0x04; // Set Zero flag - if (ar&0x80) ccr |= 0x08; // Set Negative flag - iclock += 4; -} -void OpA8(void) // EORA IDX - { - ar ^= RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpA9(void) // ADCA IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); - addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - ar = addr & 0xFF; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 4; -} -void OpAA(void) // ORA IDX -{ - ar |= RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; -} -void OpAB(void) // ADDA IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); - addr = (WORD)ar + (WORD)tmp; - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - ar = addr & 0xFF; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 4; -} -void OpAC(void) // CMPX IDX -{ - addr = DecodeIDX(Fetch()); - WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1); - WORD dw = xr - addr2; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (xr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((xr^addr2^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 6; -} -void OpAD(void) // JSR IDX -{ - addr = DecodeIDX(Fetch()); - WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); - pcr = addr; // JSR directly to IDX ptr - iclock += 7; -} -void OpAE(void) // LDX IDX -{ - addr = DecodeIDX(Fetch()); - xr = (RdMem(addr) << 8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpAF(void) // STX IDX -{ - addr = DecodeIDX(Fetch()); - WrMem(addr, xr>>8); WrMem(addr+1, xr&0xFF); - ccr &= 0xF1; // CLV CLZ CLN - if (xr == 0) ccr |= 0x04; // Set Zero flag - if (xr&0x8000) ccr |= 0x08; // Set Negative flag - iclock += 5; -} -void OpB0(void) // SUBA ABS - { - tmp = RdMem(FetchW()); BYTE as = ar; - ar -= tmp; - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (as < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 5; - } -void OpB1(void) // CMPA ABS - { - tmp = RdMem(FetchW()); - BYTE db = ar - tmp; - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (ar < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ar^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 5; - } -void OpB2(void) // SBCA ABS -{ - tmp = RdMem(FetchW()); BYTE as = ar; - ar = ar - tmp - (ccr&0x01); - (as < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((as^tmp^ar^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpB3(void) // SUBD ABS -{ - addr = FetchW(); WORD dr = (ar<<8)|br, ds = dr; - WORD adr2 = (RdMem(addr)<<8) | RdMem(addr+1); - dr -= adr2; - (ds < adr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ar = dr>>8; br = dr&0xFF; - iclock += 7; -} -void OpB4(void) // ANDA ABS -{ - ar &= RdMem(FetchW()); - ccr &= 0xFD; // Clear oVerflow flag - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpB5(void) // BITA ABS -{ - tmp = ar & RdMem(FetchW()); - ccr &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpB6(void) // LDA ABS -{ - ar = RdMem(FetchW()); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpB7(void) // STA ABS -{ - WrMem(FetchW(), ar); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpB8(void) // EORA ABS -{ - ar ^= RdMem(FetchW()); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpB9(void) // ADCA ABS -{ - tmp = RdMem(FetchW()); - addr = (WORD)ar + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - ar = addr; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 5; -} -void OpBA(void) // ORA ABS -{ - ar |= RdMem(FetchW()); - ccr &= 0xFD; // CLV - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpBB(void) // ADDA ABS -{ - tmp = RdMem(FetchW()); - addr = (WORD)ar + (WORD)tmp; - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((ar^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((ar^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - ar = addr & 0xFF; // Set accumulator - (ar == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 5; -} -void OpBC(void) // CMPX ABS -{ - addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1); - WORD dw = xr - addr2; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (xr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((xr^addr2^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 7; -} -void OpBD(void) // JSR ABS -{ - addr = FetchW(); - WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); - pcr = addr; // Go to absolute address (Not indir) - iclock += 8; -} -void OpBE(void) // LDX ABS -{ - addr = FetchW(); - xr = (RdMem(addr) << 8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; -} -void OpBF(void) // STX ABS - { - addr = FetchW(); - WrMem(addr, xr>>8); WrMem(addr+1, xr&0xFF); - ccr &= 0xFD; // CLV - (xr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (xr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void OpC0(void) // SUBB # - { - tmp = Fetch(); BYTE bs = br; - br -= tmp; - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 2; - } -void OpC1(void) // CMPB # - { - tmp = Fetch(); - BYTE db = br - tmp; - (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void OpC2(void) // SBCB # -{ - tmp = Fetch(); BYTE bs = br; - br = br - tmp - (ccr&0x01); - (bs < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; -} -void OpC3(void) // ADDD # -{ - addr = FetchW(); long dr = ((ar<<8)|br)&0xFFFF, ds = dr; - dr += addr; - (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - dr &= 0xFFFF; - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ((ds^addr^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - ar = dr>>8; br = dr&0xFF; - iclock += 4; -} -void OpC4(void) // ANDB # - { - br &= Fetch(); - ccr &= 0xFD; // Clear oVerflow flag - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void OpC5(void) // BITB # -{ - tmp = br & Fetch(); - ccr &= 0xF1; // CLV CLZ CLN - if (tmp == 0) ccr |= 0x04; // Set Zero flag - if (tmp&0x80) ccr |= 0x08; // Set Negative flag - iclock += 2; -} -void OpC6(void) // LDB # -{ - br = Fetch(); - ccr &= 0xF1; // CLV CLZ CLN - if (br == 0) ccr |= 0x04; // Set Zero flag - if (br&0x80) ccr |= 0x08; // Set Negative flag - iclock += 2; -} -void OpC8(void) // EORB # - { - br ^= Fetch(); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void OpC9(void) // ADCB # -{ - tmp = Fetch(); - addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - br = addr & 0xFF; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 2; -} -void OpCA(void) // ORB # - { - br |= Fetch(); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 2; - } -void OpCB(void) // ADDB # -{ - tmp = Fetch(); addr = br + tmp; - (addr > 0xFF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - br = addr & 0xFF; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 2; -} -void OpCC(void) // LDD # -{ - ar = Fetch(); br = Fetch(); - ccr &= 0xFD; // CLV - ((ar+br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 3; -} -void OpCE(void) // LDU # -{ - ur = FetchW(); - ccr &= 0xFD; // CLV - (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 3; -} -void OpD0(void) // SUBB DP -{ - tmp = RdMem((dpr<<8)|Fetch()); BYTE bs = br; - br -= tmp; - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; -} -void OpD1(void) // CMPB DP -{ - tmp = RdMem((dpr<<8)|Fetch()); - BYTE db = br - tmp; - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; -} -void OpD2(void) // SBCB DP -{ - tmp = RdMem((dpr<<8)|Fetch()); BYTE bs = br; - br = br - tmp - (ccr&0x01); - (bs < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; -} -void OpD3(void) // ADDD DP -{ - addr = (dpr<<8)|Fetch(); long dr = ((ar<<8)|br)&0xFFFF, ds = dr; - WORD adr2 = (RdMem(addr)<<8)|RdMem(addr+1); - dr += adr2; - (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - dr &= 0xFFFF; - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - ar = dr>>8; br = dr&0xFF; - iclock += 6; -} -void OpD4(void) // ANDB DP - { - br &= RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // Clear oVerflow flag - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpD5(void) // BITB DP - { - tmp = br & RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpD6(void) // LDB DP -{ - br = RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; -} -void OpD7(void) // STB DP - { - WrMem((dpr<<8)|Fetch(), br); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpD8(void) // EORB DP - { - br ^= RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpD9(void) // ADCB DP -{ - tmp = RdMem((dpr<<8)|Fetch()); - addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - br = addr; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 4; -} -void OpDA(void) // ORB DP - { - br |= RdMem((dpr<<8)|Fetch()); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpDB(void) // ADDB DP -{ - tmp = RdMem((dpr<<8)|Fetch()); - addr = (WORD)br + (WORD)tmp; - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - br = addr & 0xFF; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 4; -} -void OpDC(void) // LDD DP -{ - addr = (dpr<<8)|Fetch(); - ar = RdMem(addr); br = RdMem(addr+1); - ccr &= 0xFD; // CLV - ((ar|br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpDD(void) // STD DP -{ - addr = (dpr<<8)|Fetch(); - WrMem(addr, ar); WrMem(addr+1, br); - ccr &= 0xFD; // CLV - ((ar|br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpDE(void) // LDU DP -{ - addr = (dpr<<8)|Fetch(); - ur = (RdMem(addr) << 8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpDF(void) // STU DP -{ - addr = (dpr<<8)|Fetch(); - WrMem(addr, ur>>8); WrMem(addr+1, ur&0xFF); - ccr &= 0xFD; // CLV - (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; -} -void OpE0(void) // SUBB IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); BYTE bs = br; - br -= tmp; - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; -} -void OpE1(void) // CMPB IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); - BYTE db = br - tmp; - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 4; -} -void OpE2(void) // SBCB IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); BYTE bs = br; - br = br - tmp - (ccr&0x01); - (bs < (tmp+(ccr&0x01)) ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; -} -void OpE3(void) // ADDD IDX -{ - addr = DecodeIDX(Fetch()); long dr = ((ar<<8)|br)&0xFFFF, ds = dr; - WORD adr2 = (RdMem(addr)<<8)|RdMem(addr+1); - dr += adr2; - (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - dr &= 0xFFFF; - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - ar = dr>>8; br = dr&0xFF; - iclock += 6; -} -void OpE4(void) // ANDB IDX - { - br &= RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // Clear oVerflow flag - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpE5(void) // BITB IDX - { - tmp = br & RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpE6(void) // LDB IDX - { - br = RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpE7(void) // STB IDX -{ - WrMem(DecodeIDX(Fetch()), br); - ccr &= 0xF1; // CLV CLZ CLN - if (br == 0) ccr |= 0x04; // Adjust Zero flag - if (br&0x80) ccr |= 0x08; // Adjust Negative flag - iclock += 4; -} -void OpE8(void) // EORB IDX - { - br ^= RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpE9(void) // ADCB IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); - addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - br = addr; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 4; -} -void OpEA(void) // ORB IDX - { - br |= RdMem(DecodeIDX(Fetch())); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void OpEB(void) // ADDB IDX -{ - tmp = RdMem(DecodeIDX(Fetch())); - addr = (WORD)br + (WORD)tmp; - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - br = addr; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 4; -} -void OpEC(void) // LDD IDX -{ - addr = DecodeIDX(Fetch()); - ar = RdMem(addr); br = RdMem(addr+1); - ccr &= 0xF1; // CLV CLZ CLN - if (!(ar|br)) ccr |= 0x04; // Adjust Zero flag - if (ar&0x80) ccr |= 0x08; // Adjust Negative flag - iclock += 5; -} -void OpED(void) // STD IDX -{ - addr = DecodeIDX(Fetch()); - WrMem(addr, ar); WrMem(addr+1, br); - ccr &= 0xF1; // CLV CLZ CLZ - if (!(ar|br)) ccr |= 0x04; // Adjust Zero flag - if (ar&0x80) ccr |= 0x08; // Adjust Negative flag - iclock += 5; -} -void OpEE(void) // LDU IDX -{ - addr = DecodeIDX(Fetch()); - ur = (RdMem(addr) << 8) | RdMem(addr+1); - ccr &= 0xF1; // CLV CLZ CLN - if (ur == 0) ccr |= 0x04; // Set Zero flag - if (ur&0x8000) ccr |= 0x08; // Set Negative flag - iclock += 5; -} -void OpEF(void) // STU IDX -{ - addr = DecodeIDX(Fetch()); - WrMem(addr, ur>>8); WrMem(addr+1, ur&0xFF); - ccr &= 0xF1; // CLV CLZ CLN - if (ur == 0) ccr |= 0x04; // Set Zero flag - if (ur&0x8000) ccr |= 0x08; // Set Negative flag - iclock += 5; -} -void OpF0(void) // SUBB ABS - { - tmp = RdMem(FetchW()); BYTE bs = br; - br -= tmp; - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - } -void OpF1(void) // CMPB ABS - { - tmp = RdMem(FetchW()); - BYTE db = br - tmp; - (db == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (db&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (br < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((br^tmp^db^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 5; - } -void OpF2(void) // SBCB ABS -{ - tmp = RdMem(FetchW()); BYTE bs = br; - br = br - tmp - (ccr&0x01); - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (bs < tmp ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((bs^tmp^br^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflow - iclock += 5; -} -void OpF3(void) // ADDD ABS -{ - addr = FetchW(); long dr = ((ar<<8)|br)&0xFFFF, ds = dr; - WORD adr2 = (RdMem(addr)<<8)|RdMem(addr+1); - dr += adr2; - (dr > 0xFFFF ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - dr &= 0xFFFF; - (dr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - ((ds^adr2^dr^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - ar = dr>>8; br = dr&0xFF; - iclock += 7; -} -void OpF4(void) // ANDB ABS - { - br &= RdMem(FetchW()); - ccr &= 0xFD; // Clear oVerflow flag - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void OpF5(void) // BITB ABS - { - tmp = br & RdMem(FetchW()); - ccr &= 0xFD; // Clear oVerflow flag - (tmp == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (tmp&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void OpF6(void) // LDB ABS - { - br = RdMem(FetchW()); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void OpF7(void) // STB ABS - { - WrMem(FetchW(), br); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void OpF8(void) // EORB ABS - { - br ^= RdMem(FetchW()); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void OpF9(void) // ADCB ABS -{ - tmp = RdMem(FetchW()); - addr = (WORD)br + (WORD)tmp + (WORD)(ccr&0x01); - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - br = addr & 0xFF; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 5; -} -void OpFA(void) // ORB ABS - { - br |= RdMem(FetchW()); - ccr &= 0xFD; // CLV - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 5; - } -void OpFB(void) // ADDB ABS -{ - tmp = RdMem(FetchW()); - addr = (WORD)br + (WORD)tmp; - (addr > 0x00FF ? ccr |= 0x01 : ccr &= 0xFE); // Set Carry flag - ((br^tmp^addr)&0x10 ? ccr |= 0x20 : ccr &= 0xDF); // Set Half carry - ((br^tmp^addr^(ccr<<7))&0x80 ? ccr |= 0x02 : ccr &= 0xFD); // oVerflo - br = addr & 0xFF; // Set accumulator - (br == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Set Zero flag - (br&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Set Negative flag - iclock += 5; -} -void OpFC(void) // LDD ABS - { - addr = FetchW(); - ar = RdMem(addr); br = RdMem(addr+1); - ccr &= 0xFD; // CLV - ((ar+br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void OpFD(void) // STD ABS - { - addr = FetchW(); - WrMem(addr, ar); WrMem(addr+1, br); - ccr &= 0xFD; // CLV - ((ar+br) == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ar&0x80 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void OpFE(void) // LDU ABS - { - addr = FetchW(); - ur = (RdMem(addr) << 8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void OpFF(void) // STU ABS - { - addr = FetchW(); - WrMem(addr, ur>>8); WrMem(addr+1, ur&0xFF); - ccr &= 0xFD; // CLV - (ur == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (ur&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } - -// -// Page one opcodes' execute code -// - -void Op1021(void) // LBRN -{ - addr = FetchW(); - iclock += 5; -} -void Op1022(void) // LBHI -{ - addr = FetchW(); - if (!((ccr&0x01)|(ccr&0x04))) pcr += SignedW(addr); - iclock += 5; -} -void Op1023(void) // LBLS -{ - addr = FetchW(); - if ((ccr&0x01)|(ccr&0x04)) pcr += SignedW(addr); - iclock += 5; -} -void Op1024(void) // LBCC (LBHS) -{ - addr = FetchW(); - if (!(ccr&0x01)) pcr += SignedW(addr); - iclock += 5; -} -void Op1025(void) // LBCS (LBLO) -{ - addr = FetchW(); - if (ccr&0x01) pcr += SignedW(addr); - iclock += 5; -} -void Op1026(void) // LBNE -{ - addr = FetchW(); - if (!(ccr&0x04)) pcr += SignedW(addr); - iclock += 5; -} -void Op1027(void) // LBEQ -{ - addr = FetchW(); - if (ccr&0x04) pcr += SignedW(addr); - iclock += 5; -} -void Op1028(void) // LBVC -{ - addr = FetchW(); - if (!(ccr&0x02)) pcr += SignedW(addr); - iclock += 5; -} -void Op1029(void) // LBVS -{ - addr = FetchW(); - if (ccr&0x02) pcr += SignedW(addr); - iclock += 5; -} -void Op102A(void) // LBPL -{ - addr = FetchW(); - if (!(ccr&0x08)) pcr += SignedW(addr); - iclock += 5; -} -void Op102B(void) // LBMI -{ - addr = FetchW(); - if (ccr&0x08) pcr += SignedW(addr); - iclock += 5; -} -void Op102C(void) // LBGE -{ - addr = FetchW(); - if (!(((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedW(addr); - iclock += 5; -} -void Op102D(void) // LBLT -{ - addr = FetchW(); - if (((ccr&0x08) >> 2) ^ (ccr&0x02)) pcr += SignedW(addr); - iclock += 5; -} -void Op102E(void) // LBGT -{ - addr = FetchW(); - if (!((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02)))) pcr += SignedW(addr); - iclock += 5; -} -void Op102F(void) // LBLE -{ - addr = FetchW(); - if ((ccr&0x04) | (((ccr&0x08) >> 2) ^ (ccr&0x02))) pcr += SignedW(addr); - iclock += 5; -} -void Op103F(void) // SWI2 (Not yet implemented) -{ - iclock += 20; -} -void Op1083(void) // CMPD # - { - addr = FetchW(); WORD dr = (ar<<8)|br; - WORD dw = dr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (dr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((dr^addr^dw^((WORD)ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 5; - } -void Op108C(void) // CMPY # - { - addr = FetchW(); - WORD dw = yr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (yr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((yr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 5; - } -void Op108E(void) // LDY # - { - yr = FetchW(); - ccr &= 0xFD; // CLV - (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void Op1093(void) // CMPD DP - { - WORD adr2 = (dpr<<8)|Fetch(), dr = (ar<<8)|br; - addr = (RdMem(adr2)<<8) | RdMem(adr2+1); - WORD dw = dr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (dr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((dr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 7; - } -void Op109C(void) // CMPY DP - { - WORD adr2 = (dpr<<8)|Fetch(); - addr = (RdMem(adr2)<<8) | RdMem(adr2+1); - WORD dw = yr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (yr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - ((yr^addr^dw^(ccr<<15))&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 7; - } -void Op109E(void) // LDY DP - { - addr = (dpr<<8)|Fetch(); - yr = (RdMem(addr)<<8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op109F(void) // STY DP - { - addr = (dpr<<8)|Fetch(); - WrMem(addr, yr>>8); WrMem(addr+1, yr&0xFF); - ccr &= 0xFD; // CLV - (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op10A3(void) // CMPD IDX -{ - WORD adr2 = DecodeIDX(Fetch()), dr = (ar<<8)|br; - addr = (RdMem(adr2)<<8) | RdMem(adr2+1); - WORD dw = dr - addr; - ccr &= 0xF0; // CLC CLV CLZ CLN - if (dr < addr) ccr |= 0x01; // Set Carry flag - if ((dr^addr^dw^(ccr<<15))&0x8000) ccr |= 0x02; // Set oVerflow - if (dw == 0) ccr |= 0x04; // Set Zero flag - if (dw&0x8000) ccr |= 0x08; // Set Negative flag - iclock += 7; -} -void Op10AC(void) // CMPY IDX - { - WORD adr2 = DecodeIDX(Fetch()); - addr = (RdMem(adr2)<<8) | RdMem(adr2+1); - WORD dw = yr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (yr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^yr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 7; - } -void Op10AE(void) // LDY IDX -{ - addr = DecodeIDX(Fetch()); - yr = (RdMem(addr)<<8) | RdMem(addr+1); - ccr &= 0xF1; // CLV CLZ CLN - if (yr == 0) ccr |= 0x04; // Adjust Zero flag - if (yr&0x8000) ccr |= 0x08; // Adjust Negative flag - iclock += 6; -} -void Op10AF(void) // STY IDX - { - addr = DecodeIDX(Fetch()); - WrMem(addr, yr>>8); WrMem(addr+1, yr&0xFF); - ccr &= 0xFD; // CLV - (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op10B3(void) // CMPD ABS - { - addr = FetchW(); WORD dr = (ar<<8)|br; - WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1); - WORD dw = dr - addr2; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (dr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^dr^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 8; - } -void Op10BC(void) // CMPY ABS - { - addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1); - WORD dw = yr - addr2; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (yr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^yr^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 8; - } -void Op10BE(void) // LDY ABS - { - addr = FetchW(); - yr = (RdMem(addr)<<8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op10BF(void) // STY ABS - { - addr = FetchW(); - WrMem(addr, yr>>8); WrMem(addr+1, yr&0xFF); - ccr &= 0xFD; // CLV - (yr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (yr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op10CE(void) // LDS # - { - sr = FetchW(); - ccr &= 0xFD; // CLV - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 4; - } -void Op10DE(void) // LDS DP - { - addr = (dpr<<8)|Fetch(); - sr = (RdMem(addr)<<8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op10DF(void) // STS DP - { - addr = (dpr<<8)|Fetch(); - WrMem(addr, sr>>8); WrMem(addr+1, sr&0xFF); - ccr &= 0xFD; // CLV - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op10EE(void) // LDS IDX - { - addr = DecodeIDX(Fetch()); - sr = (RdMem(addr)<<8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op10EF(void) // STS IDX - { - addr = DecodeIDX(Fetch()); - WrMem(addr, sr>>8); WrMem(addr+1, sr&0xFF); - ccr &= 0xFD; // CLV - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 6; - } -void Op10FE(void) // LDS ABS - { - addr = FetchW(); - sr = (RdMem(addr)<<8) | RdMem(addr+1); - ccr &= 0xFD; // CLV - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; - } -void Op10FF(void) // STS ABS -{ - addr = FetchW(); - WrMem(addr, sr>>8); WrMem(addr+1, sr&0xFF); - ccr &= 0xFD; // CLV - (sr == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (sr&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - iclock += 7; -} - -// -// Page two opcodes' execute code -// - -void Op113F(void) // SWI3 - { - iclock += 20; - } -void Op1183(void) // CMPU # - { - addr = FetchW(); - WORD dw = ur - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (ur < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^ur^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 5; - } -void Op118C(void) // CMPS # - { - addr = FetchW(); - WORD dw = sr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (sr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^sr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 5; - } -void Op1193(void) // CMPU DP - { - WORD adr2 = (dpr<<8)|Fetch(); - addr = (RdMem(adr2)<<8) | RdMem(adr2+1); - WORD dw = ur - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (ur < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^ur^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 7; - } -void Op119C(void) // CMPS DP - { - WORD adr2 = (dpr<<8)|Fetch(); - addr = (RdMem(adr2)<<8) | RdMem(adr2+1); - WORD dw = sr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (sr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^sr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 7; - } -void Op11A3(void) // CMPU IDX - { - WORD addr2 = DecodeIDX(Fetch()); - addr = (RdMem(addr2)<<8) | RdMem(addr2+1); - WORD dw = ur - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (ur < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^ur^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 7; - } -void Op11AC(void) // CMPS IDX - { - WORD addr2 = DecodeIDX(Fetch()); - addr = (RdMem(addr2)<<8) | RdMem(addr2+1); - WORD dw = sr - addr; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (sr < addr ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^sr^addr^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 7; - } -void Op11B3(void) // CMPU ABS - { - addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1); - WORD dw = ur - addr2; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (ur < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^ur^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 8; - } - -void Op11BC(void) // CMPS ABS -{ - addr = FetchW(); WORD addr2 = (RdMem(addr)<<8) | RdMem(addr+1); - WORD dw = sr - addr2; - (dw == 0 ? ccr |= 0x04 : ccr &= 0xFB); // Adjust Zero flag - (dw&0x8000 ? ccr |= 0x08 : ccr &= 0xF7); // Adjust Negative flag - (sr < addr2 ? ccr |= 0x01 : ccr &= 0xFE); // Adjust Carry flag - (((ccr<<15)^sr^addr2^dw)&0x8000 ? ccr |= 0x02 : ccr &= 0xFD); // oVerfl - iclock += 8; -} - -void IllegalOp(void) -{ - iclock++; - illegal = true; -} - -void Op__(void) -{ - iclock++; - illegal = true; -} - -// -// Function arrays -// - -// Array of page zero opcode functions... -void (* exec_op0[256])() = { - Op00, Op__, Op__, Op03, Op04, Op__, Op06, Op07, Op08, Op09, Op0A, Op__, Op0C, Op0D, Op0E, Op0F, - Op__, Op__, Op12, Op13, Op__, Op__, Op16, Op17, Op__, Op19, Op1A, Op__, Op1C, Op1D, Op1E, Op1F, - Op20, Op21, Op22, Op23, Op24, Op25, Op26, Op27, Op28, Op29, Op2A, Op2B, Op2C, Op2D, Op2E, Op2F, - Op30, Op31, Op32, Op33, Op34, Op35, Op36, Op37, Op__, Op39, Op3A, Op3B, Op3C, Op3D, Op3E, Op3F, - Op40, Op__, Op__, Op43, Op44, Op__, Op46, Op47, Op48, Op49, Op4A, Op__, Op4C, Op4D, Op__, Op4F, - Op50, Op__, Op__, Op53, Op54, Op__, Op56, Op57, Op58, Op59, Op5A, Op__, Op5C, Op5D, Op__, Op5F, - Op60, Op__, Op__, Op63, Op64, Op__, Op66, Op67, Op68, Op69, Op6A, Op__, Op6C, Op6D, Op6E, Op6F, - Op70, Op__, Op__, Op73, Op74, Op__, Op76, Op77, Op78, Op79, Op7A, Op__, Op7C, Op7D, Op7E, Op7F, - Op80, Op81, Op82, Op83, Op84, Op85, Op86, Op__, Op88, Op89, Op8A, Op8B, Op8C, Op8D, Op8E, Op__, - Op90, Op91, Op92, Op93, Op94, Op95, Op96, Op97, Op98, Op99, Op9A, Op9B, Op9C, Op9D, Op9E, Op9F, - OpA0, OpA1, OpA2, OpA3, OpA4, OpA5, OpA6, OpA7, OpA8, OpA9, OpAA, OpAB, OpAC, OpAD, OpAE, OpAF, - OpB0, OpB1, OpB2, OpB3, OpB4, OpB5, OpB6, OpB7, OpB8, OpB9, OpBA, OpBB, OpBC, OpBD, OpBE, OpBF, - OpC0, OpC1, OpC2, OpC3, OpC4, OpC5, OpC6, Op__, OpC8, OpC9, OpCA, OpCB, OpCC, Op__, OpCE, Op__, - OpD0, OpD1, OpD2, OpD3, OpD4, OpD5, OpD6, OpD7, OpD8, OpD9, OpDA, OpDB, OpDC, OpDD, OpDE, OpDF, - OpE0, OpE1, OpE2, OpE3, OpE4, OpE5, OpE6, OpE7, OpE8, OpE9, OpEA, OpEB, OpEC, OpED, OpEE, OpEF, - OpF0, OpF1, OpF2, OpF3, OpF4, OpF5, OpF6, OpF7, OpF8, OpF9, OpFA, OpFB, OpFC, OpFD, OpFE, OpFF -}; - -// Array of page one opcode functions... -void (* exec_op1[256])() = { - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op1021, Op1022, Op1023, Op1024, Op1025, Op1026, Op1027, Op1028, Op1029, Op102A, Op102B, Op102C, Op102D, Op102E, Op102F, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op103F, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op1083, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op108C, Op__, Op108E, Op__, - Op__, Op__, Op__, Op1093, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op109C, Op__, Op109E, Op109F, - Op__, Op__, Op__, Op10A3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10AC, Op__, Op10AE, Op10AF, - Op__, Op__, Op__, Op10B3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10BC, Op__, Op10BE, Op10BF, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10CE, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10DE, Op10DF, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10EE, Op10EF, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op10FE, Op10FF -}; -// Array of page two opcode functions... -void (* exec_op2[256])() = { - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op113F, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op1183, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op118C, Op__, Op__, Op__, - Op__, Op__, Op__, Op1193, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op119C, Op__, Op__, Op__, - Op__, Op__, Op__, Op11A3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op11AC, Op__, Op__, Op__, - Op__, Op__, Op__, Op11B3, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op11BC, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, - Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__, Op__ -}; - -// -// Initialize 6809 function adressess -// - -void Init_6809(void) -{ - return; -/* - for(int i=0; i<256; i++) // Set all functions to illegal - exec_op0[i] = exec_op1[i] = exec_op2[i] = IllegalOp; - - exec_op0[0x00] = Op00; exec_op0[0x03] = Op03; exec_op0[0x04] = Op04; - exec_op0[0x06] = Op06; exec_op0[0x07] = Op07; exec_op0[0x08] = Op08; - exec_op0[0x09] = Op09; exec_op0[0x0A] = Op0A; exec_op0[0x0C] = Op0C; - exec_op0[0x0D] = Op0D; exec_op0[0x0E] = Op0E; exec_op0[0x0F] = Op0F; - exec_op0[0x12] = Op12; exec_op0[0x13] = Op13; exec_op0[0x16] = Op16; - exec_op0[0x17] = Op17; exec_op0[0x19] = Op19; exec_op0[0x1A] = Op1A; - exec_op0[0x1C] = Op1C; exec_op0[0x1D] = Op1D; exec_op0[0x1E] = Op1E; - exec_op0[0x1F] = Op1F; exec_op0[0x20] = Op20; exec_op0[0x21] = Op21; - exec_op0[0x22] = Op22; exec_op0[0x23] = Op23; exec_op0[0x24] = Op24; - exec_op0[0x25] = Op25; exec_op0[0x26] = Op26; exec_op0[0x27] = Op27; - exec_op0[0x28] = Op28; exec_op0[0x29] = Op29; exec_op0[0x2A] = Op2A; - exec_op0[0x2B] = Op2B; exec_op0[0x2C] = Op2C; exec_op0[0x2D] = Op2D; - exec_op0[0x2E] = Op2E; exec_op0[0x2F] = Op2F; exec_op0[0x30] = Op30; - exec_op0[0x31] = Op31; exec_op0[0x32] = Op32; exec_op0[0x33] = Op33; - exec_op0[0x34] = Op34; exec_op0[0x35] = Op35; exec_op0[0x36] = Op36; - exec_op0[0x37] = Op37; exec_op0[0x39] = Op39; exec_op0[0x3A] = Op3A; - exec_op0[0x3B] = Op3B; exec_op0[0x3C] = Op3C; exec_op0[0x3D] = Op3D; - exec_op0[0x3E] = Op3E; exec_op0[0x3F] = Op3F; exec_op0[0x40] = Op40; - exec_op0[0x43] = Op43; exec_op0[0x44] = Op44; exec_op0[0x46] = Op46; - exec_op0[0x47] = Op47; exec_op0[0x48] = Op48; exec_op0[0x49] = Op49; - exec_op0[0x4A] = Op4A; exec_op0[0x4C] = Op4C; exec_op0[0x4D] = Op4D; - exec_op0[0x4F] = Op4F; exec_op0[0x50] = Op50; exec_op0[0x53] = Op53; - exec_op0[0x54] = Op54; exec_op0[0x56] = Op56; exec_op0[0x57] = Op57; - exec_op0[0x58] = Op58; exec_op0[0x59] = Op59; exec_op0[0x5A] = Op5A; - exec_op0[0x5C] = Op5C; exec_op0[0x5D] = Op5D; exec_op0[0x5F] = Op5F; - exec_op0[0x60] = Op60; exec_op0[0x63] = Op63; exec_op0[0x64] = Op64; - exec_op0[0x66] = Op66; exec_op0[0x67] = Op67; exec_op0[0x68] = Op68; - exec_op0[0x69] = Op69; exec_op0[0x6A] = Op6A; exec_op0[0x6C] = Op6C; - exec_op0[0x6D] = Op6D; exec_op0[0x6E] = Op6E; exec_op0[0x6F] = Op6F; - exec_op0[0x70] = Op70; exec_op0[0x73] = Op73; exec_op0[0x74] = Op74; - exec_op0[0x76] = Op76; exec_op0[0x77] = Op77; exec_op0[0x78] = Op78; - exec_op0[0x79] = Op79; exec_op0[0x7A] = Op7A; exec_op0[0x7C] = Op7C; - exec_op0[0x7D] = Op7D; exec_op0[0x7E] = Op7E; exec_op0[0x7F] = Op7F; - exec_op0[0x80] = Op80; exec_op0[0x81] = Op81; exec_op0[0x82] = Op82; - exec_op0[0x83] = Op83; exec_op0[0x84] = Op84; exec_op0[0x85] = Op85; - exec_op0[0x86] = Op86; exec_op0[0x88] = Op88; exec_op0[0x89] = Op89; - exec_op0[0x8A] = Op8A; exec_op0[0x8B] = Op8B; exec_op0[0x8C] = Op8C; - exec_op0[0x8D] = Op8D; exec_op0[0x8E] = Op8E; exec_op0[0x90] = Op90; - exec_op0[0x91] = Op91; exec_op0[0x92] = Op92; exec_op0[0x93] = Op93; - exec_op0[0x94] = Op94; exec_op0[0x95] = Op95; exec_op0[0x96] = Op96; - exec_op0[0x97] = Op97; exec_op0[0x98] = Op98; exec_op0[0x99] = Op99; - exec_op0[0x9A] = Op9A; exec_op0[0x9B] = Op9B; exec_op0[0x9C] = Op9C; - exec_op0[0x9D] = Op9D; exec_op0[0x9E] = Op9E; exec_op0[0x9F] = Op9F; - exec_op0[0xA0] = OpA0; exec_op0[0xA1] = OpA1; exec_op0[0xA2] = OpA2; - exec_op0[0xA3] = OpA3; exec_op0[0xA4] = OpA4; exec_op0[0xA5] = OpA5; - exec_op0[0xA6] = OpA6; exec_op0[0xA7] = OpA7; exec_op0[0xA8] = OpA8; - exec_op0[0xA9] = OpA9; exec_op0[0xAA] = OpAA; exec_op0[0xAB] = OpAB; - exec_op0[0xAC] = OpAC; exec_op0[0xAD] = OpAD; exec_op0[0xAE] = OpAE; - exec_op0[0xAF] = OpAF; exec_op0[0xB0] = OpB0; exec_op0[0xB1] = OpB1; - exec_op0[0xB2] = OpB2; exec_op0[0xB3] = OpB3; exec_op0[0xB4] = OpB4; - exec_op0[0xB5] = OpB5; exec_op0[0xB6] = OpB6; exec_op0[0xB7] = OpB7; - exec_op0[0xB8] = OpB8; exec_op0[0xB9] = OpB9; exec_op0[0xBA] = OpBA; - exec_op0[0xBB] = OpBB; exec_op0[0xBC] = OpBC; exec_op0[0xBD] = OpBD; - exec_op0[0xBE] = OpBE; exec_op0[0xBF] = OpBF; exec_op0[0xC0] = OpC0; - exec_op0[0xC1] = OpC1; exec_op0[0xC2] = OpC2; exec_op0[0xC3] = OpC3; - exec_op0[0xC4] = OpC4; exec_op0[0xC5] = OpC5; exec_op0[0xC6] = OpC6; - exec_op0[0xC8] = OpC8; exec_op0[0xC9] = OpC9; exec_op0[0xCA] = OpCA; - exec_op0[0xCB] = OpCB; exec_op0[0xCC] = OpCC; exec_op0[0xCE] = OpCE; - exec_op0[0xD0] = OpD0; exec_op0[0xD1] = OpD1; exec_op0[0xD2] = OpD2; - exec_op0[0xD3] = OpD3; exec_op0[0xD4] = OpD4; exec_op0[0xD5] = OpD5; - exec_op0[0xD6] = OpD6; exec_op0[0xD7] = OpD7; exec_op0[0xD8] = OpD8; - exec_op0[0xD9] = OpD9; exec_op0[0xDA] = OpDA; exec_op0[0xDB] = OpDB; - exec_op0[0xDC] = OpDC; exec_op0[0xDD] = OpDD; exec_op0[0xDE] = OpDE; - exec_op0[0xDF] = OpDF; exec_op0[0xE0] = OpE0; exec_op0[0xE1] = OpE1; - exec_op0[0xE2] = OpE2; exec_op0[0xE3] = OpE3; exec_op0[0xE4] = OpE4; - exec_op0[0xE5] = OpE5; exec_op0[0xE6] = OpE6; exec_op0[0xE7] = OpE7; - exec_op0[0xE8] = OpE8; exec_op0[0xE9] = OpE9; exec_op0[0xEA] = OpEA; - exec_op0[0xEB] = OpEB; exec_op0[0xEC] = OpEC; exec_op0[0xED] = OpED; - exec_op0[0xEE] = OpEE; exec_op0[0xEF] = OpEF; exec_op0[0xF0] = OpF0; - exec_op0[0xF1] = OpF1; exec_op0[0xF2] = OpF2; exec_op0[0xF3] = OpF3; - exec_op0[0xF4] = OpF4; exec_op0[0xF5] = OpF5; exec_op0[0xF6] = OpF6; - exec_op0[0xF7] = OpF7; exec_op0[0xF8] = OpF8; exec_op0[0xF9] = OpF9; - exec_op0[0xFA] = OpFA; exec_op0[0xFB] = OpFB; exec_op0[0xFC] = OpFC; - exec_op0[0xFD] = OpFD; exec_op0[0xFE] = OpFE; exec_op0[0xFF] = OpFF; - - exec_op1[0x21] = Op1021; exec_op1[0x22] = Op1022; exec_op1[0x23] = Op1023; - exec_op1[0x24] = Op1024; exec_op1[0x25] = Op1025; exec_op1[0x26] = Op1026; - exec_op1[0x27] = Op1027; exec_op1[0x28] = Op1028; exec_op1[0x29] = Op1029; - exec_op1[0x2A] = Op102A; exec_op1[0x2B] = Op102B; exec_op1[0x2C] = Op102C; - exec_op1[0x2D] = Op102D; exec_op1[0x2E] = Op102E; exec_op1[0x2F] = Op102F; - exec_op1[0x3F] = Op103F; exec_op1[0x83] = Op1083; exec_op1[0x8C] = Op108C; - exec_op1[0x8E] = Op108E; exec_op1[0x93] = Op1093; exec_op1[0x9C] = Op109C; - exec_op1[0x9E] = Op109E; exec_op1[0x9F] = Op109F; exec_op1[0xA3] = Op10A3; - exec_op1[0xAC] = Op10AC; exec_op1[0xAE] = Op10AE; exec_op1[0xAF] = Op10AF; - exec_op1[0xB3] = Op10B3; exec_op1[0xBC] = Op10BC; exec_op1[0xBE] = Op10BE; - exec_op1[0xBF] = Op10BF; exec_op1[0xCE] = Op10CE; exec_op1[0xDE] = Op10DE; - exec_op1[0xDF] = Op10DF; exec_op1[0xEE] = Op10EE; exec_op1[0xEF] = Op10EF; - exec_op1[0xFE] = Op10FE; exec_op1[0xFF] = Op10FF; - - exec_op2[0x3F] = Op113F; exec_op2[0x83] = Op1183; exec_op2[0x8C] = Op118C; - exec_op2[0x93] = Op1193; exec_op2[0x9C] = Op119C; exec_op2[0xA3] = Op11A3; - exec_op2[0xAC] = Op11AC; exec_op2[0xB3] = Op11B3; exec_op2[0xBC] = Op11BC;*/ -} - -// -// Function to execute one 6809 instruction -// - -void Execute_6809(long num_of_instrs_to_exec) -{ - for(long i=0; i 2177) - { - iclock = 0; - if (!(ccr&0x10) && (!inter)) // Process an interrupt? - { - inter = true; - ccr |= 0x80; // Set E - WrMem(--sr, pcr&0xFF); WrMem(--sr, pcr>>8); // Save all regs... - WrMem(--sr, ur&0xFF); WrMem(--sr, ur>>8); - WrMem(--sr, yr&0xFF); WrMem(--sr, yr>>8); - WrMem(--sr, xr&0xFF); WrMem(--sr, xr>>8); - WrMem(--sr, dpr); WrMem(--sr, br); - WrMem(--sr, ar); WrMem(--sr, ccr); - ccr |= 0x50; // Set F,I - pcr = (RdMem(0xFFF8)<<8) | RdMem(0xFFF9); // And do it! -// ram[0xCB00] += 64; // Set to 64 for faster updates... - } - } - } -} - -void Execute6809(V6809REGS * context, DWORD cycles) -{ - memcpy(®s, context, sizeof(V6809REGS)); - - // Execute here... - - memcpy(context, ®s, sizeof(V6809REGS)); -}