X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fv6809.cpp;h=487493762f5a947db704d4a2eb9337beaffc5145;hb=1c58629b5fa5b89dd3982991efa15decde7dc823;hp=4de9d29757cc3a8353c4b0bb1f82fc2fd8da26e2;hpb=27ad8041c00ff80e50ba0ad9022c3eaa7a05b8b0;p=thunder

diff --git a/src/v6809.cpp b/src/v6809.cpp
index 4de9d29..4874937 100755
--- a/src/v6809.cpp
+++ b/src/v6809.cpp
@@ -1,41 +1,112 @@
 //
-// Virtual 6809 v1.2 (Last build: 2/27/2004)
+// Virtual 6809 v1.3
 //
 // by James L. Hammons
+// (c) 1997, 2006 Underground Software
 //
-// (c) 1997,2004 Underground Software
+// JLH = James L. Hammons <jlhamm@acm.org>
+//
+// WHO  WHEN        WHAT
+// ---  ----------  ------------------------------------------------------------
+// JLH  06/15/2006  Added changelog ;-)
+// JLH  06/15/2006  Scrubbed all BYTE, WORD & DWORD references from the code
+// JLH  11/11/2006  Removed all SignedX() references
+//
+
+// Mebbe someday I'll get around to fixing the core to be more like V65C02...
+// We have a start... ;-)
 //
 
 #include "v6809.h"
 
+#define __DEBUG__
 #ifdef __DEBUG__
 #include "dis6809.h"	// Temporary...
 #include "log.h"		// Temporary...
 #endif
 
+// Various macros
+
+#define CLR_Z				(regs.cc &= ~FLAG_Z)
+#define CLR_ZN				(regs.cc &= ~(FLAG_Z | FLAG_N))
+#define CLR_ZNC				(regs.cc &= ~(FLAG_Z | FLAG_N | FLAG_C))
+#define CLR_V				(regs.cc &= ~FLAG_V)
+#define CLR_N				(regs.cc &= ~FLAG_N)
+#define SET_Z(r)			(regs.cc = ((r) == 0 ? regs.cc | FLAG_Z : regs.cc & ~FLAG_Z))
+#define SET_N(r)			(regs.cc = ((r) & 0x80 ? regs.cc | FLAG_N : regs.cc & ~FLAG_N))
+
+//Not sure that this code is computing the carry correctly... Investigate! [Seems to be]
+#define SET_C_ADD(a,b)		(regs.cc = ((uint8)(b) > (uint8)(~(a)) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+//#define SET_C_SUB(a,b)		(regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_C_CMP(a,b)		(regs.cc = ((uint8)(b) >= (uint8)(a) ? regs.cc | FLAG_C : regs.cc & ~FLAG_C))
+#define SET_ZN(r)			SET_N(r); SET_Z(r)
+#define SET_ZNC_ADD(a,b,r)	SET_N(r); SET_Z(r); SET_C_ADD(a,b)
+//#define SET_ZNC_SUB(a,b,r)	SET_N(r); SET_Z(r); SET_C_SUB(a,b)
+#define SET_ZNC_CMP(a,b,r)	SET_N(r); SET_Z(r); SET_C_CMP(a,b)
+
+//Small problem with the EA_ macros: ABS macros don't increment the PC!!! !!! FIX !!!
+//Hmm, why not do like we did for READ_ABS*???
+//Because the EA_* macros are usually used as an argument to a function call, that's why.
+#define EA_IMM				regs.pc++
+#define EA_ZP				regs.RdMem(regs.pc++)
+#define EA_ZP_X				(regs.RdMem(regs.pc++) + regs.x) & 0xFF
+#define EA_ZP_Y				(regs.RdMem(regs.pc++) + regs.y) & 0xFF
+#define EA_ABS				RdMemW(regs.pc)
+#define EA_ABS_X			RdMemW(regs.pc) + regs.x
+#define EA_ABS_Y			RdMemW(regs.pc) + regs.y
+#define EA_IND_ZP_X			RdMemW((regs.RdMem(regs.pc++) + regs.x) & 0xFF)
+#define EA_IND_ZP_Y			RdMemW(regs.RdMem(regs.pc++)) + regs.y
+#define EA_IND_ZP			RdMemW(regs.RdMem(regs.pc++))
+
+#define READ_IMM			regs.RdMem(EA_IMM)
+#define READ_ZP				regs.RdMem(EA_ZP)
+#define READ_ZP_X			regs.RdMem(EA_ZP_X)
+#define READ_ZP_Y			regs.RdMem(EA_ZP_Y)
+#define READ_ABS			regs.RdMem(EA_ABS);     regs.pc += 2
+#define READ_ABS_X			regs.RdMem(EA_ABS_X);   regs.pc += 2
+#define READ_ABS_Y			regs.RdMem(EA_ABS_Y);   regs.pc += 2
+#define READ_IND_ZP_X		regs.RdMem(EA_IND_ZP_X)
+#define READ_IND_ZP_Y		regs.RdMem(EA_IND_ZP_Y)
+#define READ_IND_ZP			regs.RdMem(EA_IND_ZP)
+
+#define READ_IMM_WB(v)		uint16 addr = EA_IMM;      v = regs.RdMem(addr)
+#define READ_ZP_WB(v)		uint16 addr = EA_ZP;       v = regs.RdMem(addr)
+#define READ_ZP_X_WB(v)		uint16 addr = EA_ZP_X;     v = regs.RdMem(addr)
+#define READ_ABS_WB(v)		uint16 addr = EA_ABS;      v = regs.RdMem(addr); regs.pc += 2
+#define READ_ABS_X_WB(v)	uint16 addr = EA_ABS_X;    v = regs.RdMem(addr); regs.pc += 2
+#define READ_ABS_Y_WB(v)	uint16 addr = EA_ABS_Y;    v = regs.RdMem(addr); regs.pc += 2
+#define READ_IND_ZP_X_WB(v)	uint16 addr = EA_IND_ZP_X; v = regs.RdMem(addr)
+#define READ_IND_ZP_Y_WB(v)	uint16 addr = EA_IND_ZP_Y; v = regs.RdMem(addr)
+#define READ_IND_ZP_WB(v)	uint16 addr = EA_IND_ZP;   v = regs.RdMem(addr)
+
+#define WRITE_BACK(d)		regs.WrMem(addr, (d))
+
 // Private global variables
 
 static V6809REGS regs;
-static WORD addr;										// Temporary variables common to all funcs...
-static BYTE tmp;
+//Let's see if we can nuke this shit.
+static uint16 addr;								// Temporary variables common to all funcs...
+static uint8 tmp;
 
 // Private function prototypes
 
-static int SignedB(BYTE);								// Return signed byte from unsigned
-static int SignedW(WORD);								// Return signed word from unsigned
-static WORD FetchW(void);
-static WORD RdMemW(WORD addr);
-static void WrMemW(WORD addr, WORD w);
-static WORD ReadEXG(BYTE);								// Read TFR/EXG post byte
-static void WriteEXG(BYTE, WORD);						// Set TFR/EXG data
-static WORD DecodeReg(BYTE);							// Decode register data
-static WORD DecodeIDX(BYTE);							// Decode IDX data
+static uint16 FetchW(void);
+static uint16 RdMemW(uint16 addr);
+static void WrMemW(uint16 addr, uint16 w);
+static uint16 ReadEXG(uint8);					// Read TFR/EXG post byte
+static void WriteEXG(uint8, uint16);			// Set TFR/EXG data
+static uint16 DecodeReg(uint8);					// Decode register data
+static uint16 DecodeIDX(uint8);					// Decode IDX data
+
+//static void (* exec_op1[256])();
+//static void (* exec_op2[256])();
+#if 1
 
 // This is here because of the stupid forward declaration rule that C++ forces (the C++ compiler
 // isn't smart enough to know that the identifiers in the arrays are declared later, it doesn't
 // even *try* to see if they're there).
 
-#define FD(x)		static void Op##x();				// FD -> "Forward Declaration"
+#define FD(x)		static void Op##x();		// FD -> "Forward Declaration"
 #define FE(x)		static void Op10##x();
 #define FF(x)		static void Op11##x();
 
@@ -67,6 +138,12 @@ FF(3F) FF(83) FF(8C) FF(93) FF(9C) FF(A3) FF(AC) FF(B3) FF(BC)
 #undef FE
 #undef FF
 
+#endif
+
+// We can move these down and do away with the forward declarations... !!! FIX !!!
+// Actually, we can't because these are used in a couple of the opcode functions.
+// Have to think about how to fix that...
+
 //
 // Function arrays
 //
@@ -136,59 +213,36 @@ static void (* exec_op2[256])() = {
 // Fetch a word out of 6809 memory (little endian format)
 // This is a leftover from when fetches were separated from garden variety reads...
 //
-static WORD FetchW()
+static uint16 FetchW()
 {
-	WORD w = RdMemW(regs.pc);
+	uint16 w = RdMemW(regs.pc);
 	regs.pc += 2;
 	return w;
 }
-//
-// Fetch word function
-//
-/*WORD FetchW(void)
-{
-	return (WORD)(regs.RdMem(regs.pc++) << 8) | regs.RdMem(regs.pc++);
-}*/
 
 //
 // Read word from memory function
 //
-WORD RdMemW(WORD addr)
+uint16 RdMemW(uint16 addr)
 {
-	return (WORD)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
+	return (uint16)(regs.RdMem(addr) << 8) | regs.RdMem(addr + 1);
 }
 
 //
 // Write word to memory function
 //
-void WrMemW(WORD addr, WORD w)
+void WrMemW(uint16 addr, uint16 w)
 {
 	regs.WrMem(addr + 0, w >> 8);
 	regs.WrMem(addr + 1, w & 0xFF);
 }
 
-//
-// return signed byte from unsigned
-//
-int SignedB(BYTE b)
-{
-	return (b & 0x80 ? b - 256 : b);
-}
-
-//
-// return signed word from unsigned
-//
-int SignedW(WORD w)
-{
-	return (w & 0x8000 ? w - 65536 : w);
-}
-
 //
 // Function to read TFR/EXG post byte
 //
-WORD ReadEXG(BYTE code)
+uint16 ReadEXG(uint8 code)
 {
-	WORD retval;
+	uint16 retval;
 
 	switch (code)
 	{
@@ -232,7 +286,7 @@ WORD ReadEXG(BYTE code)
 //
 // Function to set TFR/EXG data
 //
-void WriteEXG(BYTE code, WORD data)
+void WriteEXG(uint8 code, uint16 data)
 {
 	switch (code)
 	{
@@ -262,9 +316,9 @@ void WriteEXG(BYTE code, WORD data)
 //
 // Function to decode register data
 //
-WORD DecodeReg(BYTE reg)
+uint16 DecodeReg(uint8 reg)
 {
-	WORD retval;
+	uint16 retval;
 
 	switch (reg)
 	{
@@ -284,12 +338,12 @@ WORD DecodeReg(BYTE reg)
 //
 // Function to decode IDX data
 //
-WORD DecodeIDX(BYTE code)
+uint16 DecodeIDX(uint8 code)
 {
-	WORD addr, woff;
-	BYTE reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
+	uint16 addr, woff;
+	uint8 reg = (code & 0x60) >> 5, idxind = (code & 0x10) >> 4, lo_nyb = code & 0x0F;
 
-	if (!(code & 0x80))									// Hi bit unset? Then decode 4 bit offset
+	if (!(code & 0x80))							// Hi bit unset? Then decode 4 bit offset
 		addr = DecodeReg(reg) + (idxind ? lo_nyb - 16 : lo_nyb);
 	else
 	{
@@ -324,31 +378,31 @@ WORD DecodeIDX(BYTE code)
 				addr = RdMemW(woff);
 				break;
 			case 5:
-				woff = DecodeReg(reg) + SignedB(regs.b);
+				woff = DecodeReg(reg) + (int16)(int8)regs.b;
 				addr = RdMemW(woff);
 				break;
 			case 6:
-				woff = DecodeReg(reg) + SignedB(regs.a);
+				woff = DecodeReg(reg) + (int16)(int8)regs.a;
 				addr = RdMemW(woff);
 				break;
 			case 8:
-				woff = DecodeReg(reg) + SignedB(regs.RdMem(regs.pc++));
+				woff = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++);
 				addr = RdMemW(woff);
 				break;
 			case 9:
-				woff = DecodeReg(reg) + SignedW(FetchW());
+				woff = DecodeReg(reg) + FetchW();
 				addr = RdMemW(woff);
 				break;
 			case 11:
-				woff = DecodeReg(reg) + SignedW((regs.a << 8) | regs.b);
+				woff = DecodeReg(reg) + ((regs.a << 8) | regs.b);
 				addr = RdMemW(woff);
 				break;
 			case 12:
-				woff = regs.pc + SignedB(regs.RdMem(regs.pc++));
+				woff = regs.pc + (int16)(int8)regs.RdMem(regs.pc++);
 				addr = RdMemW(woff);
 				break;
 			case 13:
-				woff = regs.pc + SignedW(FetchW());
+				woff = regs.pc + FetchW();
 				addr = RdMemW(woff);
 				break;
 			case 15:
@@ -398,13 +452,13 @@ WORD DecodeIDX(BYTE code)
                    }
                    addr = DecodeReg(reg);  break; }
         case 4:  { addr = DecodeReg(reg);  break; }
-        case 5:  { addr = DecodeReg(reg) + SignedB(regs.b);  break; }
-        case 6:  { addr = DecodeReg(reg) + SignedB(regs.a);  break; }
-        case 8:  { addr = DecodeReg(reg) + SignedB(regs.RdMem(regs.pc++));  break; }
-        case 9:  { addr = DecodeReg(reg) + SignedW(FetchW());  break; }
-        case 11: { addr = DecodeReg(reg) + SignedW((regs.a << 8) | regs.b);  break; }
-        case 12: { addr = regs.pc + SignedB(regs.RdMem(regs.pc++));  break; }
-        case 13: { addr = regs.pc + SignedW(FetchW());  break; }
+        case 5:  { addr = DecodeReg(reg) + (int16)(int8)regs.b;  break; }
+        case 6:  { addr = DecodeReg(reg) + (int16)(int8)regs.a;  break; }
+        case 8:  { addr = DecodeReg(reg) + (int16)(int8)regs.RdMem(regs.pc++);  break; }
+        case 9:  { addr = DecodeReg(reg) + FetchW();  break; }
+        case 11: { addr = DecodeReg(reg) + ((regs.a << 8) | regs.b);  break; }
+        case 12: { addr = regs.pc + (int16)(int8)regs.RdMem(regs.pc++);  break; }
+        case 13: { addr = regs.pc + FetchW();  break; }
 			}
 		}
 	}
@@ -460,7 +514,7 @@ static void Op04(void)  // LSR DP
 }
 static void Op06(void)  // ROR DP
 {
-  addr = (regs.dp<<8) | regs.RdMem(regs.pc++);  BYTE tmp2 = regs.RdMem(addr);
+  addr = (regs.dp<<8) | regs.RdMem(regs.pc++);  uint8 tmp2 = regs.RdMem(addr);
   tmp = (tmp2>>1) + (regs.cc&0x01)*128;
   regs.WrMem(addr, tmp);
   (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
@@ -492,7 +546,7 @@ static void Op08(void)  // LSL DP
 }
 static void Op09(void)  // ROL DP
 {
-  addr = (regs.dp<<8) | regs.RdMem(regs.pc++);  BYTE tmp2 = regs.RdMem(addr);
+  addr = (regs.dp<<8) | regs.RdMem(regs.pc++);  uint8 tmp2 = regs.RdMem(addr);
   tmp = (tmp2<<1) + (regs.cc&0x01);
   regs.WrMem(addr, tmp);
   (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
@@ -525,8 +579,8 @@ static void Op0D(void)  // TST DP
 {
   tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
   regs.cc &= 0xFD;                              // CLV
-  (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);   // Adjust Zero flag 
-  (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);   // Adjust Negative flag 
+  (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);   // Adjust Zero flag
+  (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);   // Adjust Negative flag
   regs.clock += 6;
 }
 static void Op0E(void)  // JMP DP
@@ -546,46 +600,84 @@ static void Op10(void)											// Page 1 opcode
 	exec_op1[regs.RdMem(regs.pc++)]();
 }
 
-static void Op11(void)											// Page 2 opcode
+static void Op11(void)							// Page 2 opcode
 {
 	exec_op2[regs.RdMem(regs.pc++)]();
 }
 
-static void Op12(void)											// NOP
+static void Op12(void)							// NOP
 {
 	regs.clock += 2;
 }
 
-static void Op13(void)  // SYNC
-{ 
-  regs.clock += 2;
+static void Op13(void)							// SYNC
+{
+	// Fix this so it does the right thing (software interrupt!)
+	regs.clock += 2;
 }
-static void Op16(void)  // LBRA
+
+static void Op16(void)							// LBRA
 {
-  regs.pc += SignedW(FetchW());
-  regs.clock += 5;
+//	regs.pc += SignedW(FetchW());
+	regs.pc += FetchW();						// No need to make signed, both are 16 bit quantities
+
+	regs.clock += 5;
 }
-static void Op17(void)  // LBSR
+
+static void Op17(void)							// LBSR
 {
-  addr = FetchW();
-  regs.WrMem(--regs.s, regs.pc&0xFF);  regs.WrMem(--regs.s, regs.pc>>8);
-  regs.pc += SignedW(addr);
-  regs.clock += 9;
+	uint16 word = FetchW();
+	regs.WrMem(--regs.s, regs.pc & 0xFF);
+	regs.WrMem(--regs.s, regs.pc >> 8);
+//	regs.pc += SignedW(addr);
+	regs.pc += word;							// No need to make signed, both are 16 bit
+
+	regs.clock += 9;
 }
+
 static void Op19(void)  // DAA
 {
-  if ((regs.cc&0x20) || ((regs.a&0x0F) > 0x09))    // H set or lo nyb too big?
-  {
-    regs.a += 0x06;  regs.cc |= 0x20;              // Then adjust & set half carry
-  }
-  if ((regs.cc&0x01) || (regs.a > 0x9F))           // C set or hi nyb too big?
-  {
-    regs.a += 0x60;  regs.cc |= 0x01;              // Then adjust & set carry
-  }
-  regs.cc &= 0xF1;                             // CL NZV
-  if (regs.a == 0)  regs.cc |= 0x04;               // Adjust Zero flag 
-  if (regs.a&0x80)  regs.cc |= 0x08;               // Adjust Negative flag
-  regs.clock += 2;
+#if 0
+	uint8 result = regs.a;
+
+	if ((regs.cc&0x20) || ((regs.a&0x0F) > 0x09))    // H set or lo nyb too big?
+	{
+//		regs.a += 0x06;
+		result += 0x06;
+		regs.cc |= 0x20;              // Then adjust & set half carry
+	}
+
+	if ((regs.cc&0x01) || (regs.a > 0x9F))           // C set or hi nyb too big?
+	{
+//		regs.a += 0x60;
+		result += 0x60;
+		regs.cc |= 0x01;              // Then adjust & set carry
+	}
+
+	regs.a = result;
+
+	regs.cc &= 0xF1;                             // CL NZV
+	if (regs.a == 0)  regs.cc |= 0x04;               // Adjust Zero flag
+	if (regs.a&0x80)  regs.cc |= 0x08;               // Adjust Negative flag
+#else
+	uint16 result = (uint16)regs.a;
+
+	if ((regs.a & 0x0F) > 0x09 || (regs.cc & FLAG_H))
+		result += 0x06;
+
+	if ((regs.a & 0xF0) > 0x90 || (regs.cc & FLAG_C) || ((regs.a & 0xF0) > 0x80 && (regs.a & 0x0F) > 0x09))
+		result += 0x60;
+
+	regs.a = (uint8)result;
+//	SET_ZN(result);
+//	CLR_V;										// Not sure this is correct...
+	regs.cc &= 0xF1;                             // CL NZV
+	if (regs.a == 0)  regs.cc |= 0x04;               // Adjust Zero flag
+	if (regs.a&0x80)  regs.cc |= 0x08;               // Adjust Negative flag
+//	flagC |= (result & 0x100) >> 8;				// Overwrite carry if it was 0, otherwise, ignore
+	regs.cc |= (result & 0x100) > 8;
+#endif
+	regs.clock += 2;
 }
 
 static void Op1A(void)									// ORCC #
@@ -602,7 +694,7 @@ static void Op1C(void)									// ANDCC #
 	regs.clock += 3;
 }
 
-static void Op1D(void)									// SEX
+static void Op1D(void)							// SEX
 {
 	(regs.b & 0x80 ? regs.a = 0xFF : regs.a = 0x00);
 
@@ -612,7 +704,7 @@ static void Op1D(void)									// SEX
 	regs.clock += 2;
 }
 
-static void Op1E(void)									// EXG
+static void Op1E(void)							// EXG
 {
 	tmp = regs.RdMem(regs.pc++);
 	addr = ReadEXG(tmp >> 4);
@@ -628,100 +720,162 @@ static void Op1F(void)  // TFR
   WriteEXG(tmp&0xF, ReadEXG(tmp>>4));
   regs.clock += 7;
 }
-static void Op20(void)  // BRA
+
+static void Op20(void)							// BRA
 {
-  regs.pc += SignedB(regs.RdMem(regs.pc++));  // Branch always
-  regs.clock += 3;
+//	regs.pc += SignedB(regs.RdMem(regs.pc++));  // Branch always
+	regs.pc += (int16)(int8)regs.RdMem(regs.pc) + 1;	// Branch always
+
+	regs.clock += 3;
 }
-static void Op21(void)  // BRN
+
+static void Op21(void)							// BRN
 {
-  regs.RdMem(regs.pc++);
-  regs.clock += 3;
+	regs.RdMem(regs.pc++);
+
+	regs.clock += 3;
 }
-static void Op22(void)  // BHI
+
+static void Op22(void)							// BHI
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (!(regs.cc&0x05))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (!(regs.cc & 0x05))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op23(void)  // BLS
+
+static void Op23(void)							// BLS
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (regs.cc&0x05)  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (regs.cc & 0x05)
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op24(void)  // BCC (BHS)
+
+static void Op24(void)							// BCC (BHS)
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (!(regs.cc&0x01))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (!(regs.cc & 0x01))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op25(void)  // BCS (BLO)
+
+static void Op25(void)							// BCS (BLO)
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (regs.cc&0x01)  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (regs.cc & 0x01)
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op26(void)  // BNE
+
+static void Op26(void)							// BNE
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (!(regs.cc&0x04))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (!(regs.cc & 0x04))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op27(void)  // BEQ
+
+static void Op27(void)							// BEQ
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (regs.cc&0x04)  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (regs.cc & 0x04)
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op28(void)  // BVC
+
+static void Op28(void)							// BVC
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (!(regs.cc&0x02))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (!(regs.cc & 0x02))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op29(void)  // BVS
+
+static void Op29(void)							// BVS
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (regs.cc&0x02)  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (regs.cc & 0x02)
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op2A(void)  // BPL
+
+static void Op2A(void)							// BPL
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (!(regs.cc&0x08))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (!(regs.cc & 0x08))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op2B(void)  // BMI
+
+static void Op2B(void)							// BMI
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (regs.cc&0x08)  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (regs.cc & 0x08)
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op2C(void)  // BGE
+
+static void Op2C(void)							// BGE
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (!(((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op2D(void)  // BLT
+
+static void Op2D(void)							// BLT
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op2E(void)  // BGT
+
+static void Op2E(void)							// BGT
 {
-  tmp = regs.RdMem(regs.pc++);
-  if (!((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
-static void Op2F(void)  // BLE
+
+static void Op2F(void)							// BLE
 {
-  tmp = regs.RdMem(regs.pc++);
-  if ((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)))  regs.pc += SignedB(tmp);
-  regs.clock += 3;
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+
+	if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+		regs.pc += word;
+
+	regs.clock += 3;
 }
+
 static void Op30(void)  // LEAX
 {
   regs.x = DecodeIDX(regs.RdMem(regs.pc++));
@@ -848,7 +1002,7 @@ static void Op3F(void)  // SWI
 {
 }
 static void Op40(void)  // NEGA
-{ 
+{
   regs.a = 256 - regs.a;
   (regs.a > 0x7F  ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Adjust carry
   (regs.a == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -897,7 +1051,7 @@ static void Op48(void)  // LSLA  [Keep checking from here...]
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
   regs.clock += 2;
 }
-static void Op49(void)  // ROLA  
+static void Op49(void)  // ROLA
 {
   tmp = regs.a;  regs.a = (tmp<<1) + (regs.cc&0x01);
   (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
@@ -935,7 +1089,7 @@ static void Op4F(void)  // CLRA
   regs.clock += 2;
 }
 static void Op50(void)  // NEGB
-      { 
+      {
         regs.b = 256 - regs.b;
 //        ((regs.b^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
         (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1005,7 +1159,7 @@ static void Op5A(void)  // DECB
 static void Op5C(void)  // INCB
       {
         regs.b++;
-        (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag 
+        (regs.b == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // Adjust oVerflow flag
         (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);    // Adjust Zero flag
         (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);    // Adjust Negative flag
         regs.clock += 2;
@@ -1024,9 +1178,9 @@ static void Op5F(void)  // CLRB
         regs.clock += 2;
       }
 static void Op60(void)  // NEG IDX
-      { 
+      {
         addr = DecodeIDX(regs.RdMem(regs.pc++));
-        tmp = regs.RdMem(addr);  BYTE res = 256 - tmp;
+        tmp = regs.RdMem(addr);  uint8 res = 256 - tmp;
         regs.WrMem(addr, res);
 //        ((res^tmp)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF); // Adjust H carry
         (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1058,7 +1212,7 @@ static void Op64(void)  // LSR IDX
 static void Op66(void)  // ROR IDX
       {
         addr = DecodeIDX(regs.RdMem(regs.pc++));
-        tmp = regs.RdMem(addr);  BYTE tmp2 = tmp;
+        tmp = regs.RdMem(addr);  uint8 tmp2 = tmp;
         tmp = (tmp >> 1) + (regs.cc&0x01)*128;
         regs.WrMem(addr, tmp);
         (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
@@ -1091,7 +1245,7 @@ static void Op68(void)  // LSL IDX
       }
 static void Op69(void)  // ROL IDX
 {
-  BYTE tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
+  uint8 tmp2 = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
   tmp = (tmp2<<1) + (regs.cc&0x01);
   regs.WrMem(addr, tmp);
   (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
@@ -1101,7 +1255,7 @@ static void Op69(void)  // ROL IDX
 }
 static void Op6A(void)  // DEC IDX
       {
-  BYTE tmp;  WORD addr;
+  uint8 tmp;  uint16 addr;
         addr = DecodeIDX(regs.RdMem(regs.pc++));
         tmp = regs.RdMem(addr) - 1;
         regs.WrMem(addr, tmp);
@@ -1111,7 +1265,7 @@ static void Op6A(void)  // DEC IDX
         regs.clock += 6;
       }
 static void Op6C(void)  // INC IDX
-      {       
+      {
         addr = DecodeIDX(regs.RdMem(regs.pc++));
         tmp = regs.RdMem(addr) + 1;
         regs.WrMem(addr, tmp);
@@ -1123,8 +1277,8 @@ static void Op6C(void)  // INC IDX
 static void Op6D(void)  // TST IDX
       {
         tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
-        (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);   // Adjust Zero flag 
-        (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);   // Adjust Negative flag 
+        (tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);   // Adjust Zero flag
+        (tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);   // Adjust Negative flag
         regs.clock += 6;
       }
 static void Op6E(void)  // JMP IDX
@@ -1140,9 +1294,9 @@ static void Op6F(void)  // CLR IDX
   regs.clock += 6;
 }
 static void Op70(void)  // NEG ABS
-      { 
+      {
         addr = FetchW();
-        tmp = regs.RdMem(addr);  BYTE res = 256 - tmp;
+        tmp = regs.RdMem(addr);  uint8 res = 256 - tmp;
         regs.WrMem(addr, res);
         (res == 0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
         (res == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);   // Adjust Zero flag
@@ -1172,9 +1326,9 @@ static void Op74(void)  // LSR ABS
       }
 static void Op76(void)  // ROR ABS
       {
-  BYTE tmp;  WORD addr;
+  uint8 tmp;  uint16 addr;
         addr = FetchW();
-        tmp = regs.RdMem(addr);  BYTE tmp2 = tmp;
+        tmp = regs.RdMem(addr);  uint8 tmp2 = tmp;
         tmp = (tmp >> 1) + (regs.cc&0x01)*128;
         regs.WrMem(addr, tmp);
         (tmp2&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift bit into carry
@@ -1184,7 +1338,7 @@ static void Op76(void)  // ROR ABS
       }
 static void Op77(void)  // ASR ABS
       {
-  BYTE tmp;  WORD addr;
+  uint8 tmp;  uint16 addr;
         addr = FetchW();
         tmp = regs.RdMem(addr);
         (tmp&0x01 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Shift bit into carry
@@ -1197,7 +1351,7 @@ static void Op77(void)  // ASR ABS
       }
 static void Op78(void)  // LSL ABS
       {
-  BYTE tmp;  WORD addr;
+  uint8 tmp;  uint16 addr;
         addr = FetchW();
         tmp = regs.RdMem(addr);
         (tmp&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Shift hi bit into carry
@@ -1209,7 +1363,7 @@ static void Op78(void)  // LSL ABS
       }
 static void Op79(void)  // ROL ABS
 {
-  BYTE tmp2 = regs.RdMem(FetchW());
+  uint8 tmp2 = regs.RdMem(FetchW());
   tmp = (tmp2<<1) + (regs.cc&0x01);
   regs.WrMem(addr, tmp);
   (tmp2&0x80 ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Shift hi bit into carry
@@ -1219,7 +1373,7 @@ static void Op79(void)  // ROL ABS
 }
 static void Op7A(void)  // DEC ABS
       {
-  BYTE tmp;  WORD addr;
+  uint8 tmp;  uint16 addr;
         addr = FetchW();
         tmp = regs.RdMem(addr) - 1;
         regs.WrMem(addr, tmp);
@@ -1229,8 +1383,8 @@ static void Op7A(void)  // DEC ABS
         regs.clock += 7;
       }
 static void Op7C(void)  // INC ABS
-      {       
-  BYTE tmp;  WORD addr;
+      {
+  uint8 tmp;  uint16 addr;
         addr = FetchW();
         tmp = regs.RdMem(addr) + 1;
         regs.WrMem(addr, tmp);
@@ -1242,10 +1396,10 @@ static void Op7C(void)  // INC ABS
 
 static void Op7D(void)  // TST ABS
 {
-	BYTE tmp = regs.RdMem(FetchW());
+	uint8 tmp = regs.RdMem(FetchW());
 
-	(tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);   // Adjust Zero flag 
-	(tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);   // Adjust Negative flag 
+	(tmp == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);   // Adjust Zero flag
+	(tmp&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);   // Adjust Negative flag
 
 	regs.clock += 7;
 }
@@ -1262,8 +1416,8 @@ static void Op7F(void)  // CLR ABS
         regs.clock += 7;
       }
 static void Op80(void)  // SUBA #
-{ 
-  BYTE tmp = regs.RdMem(regs.pc++);  BYTE as = regs.a; 
+{
+  uint8 tmp = regs.RdMem(regs.pc++);  uint8 as = regs.a;
   regs.a -= tmp;
   (as < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1274,7 +1428,7 @@ static void Op80(void)  // SUBA #
 static void Op81(void)  // CMPA #
 {
   tmp = regs.RdMem(regs.pc++);
-  BYTE db = regs.a - tmp;
+  uint8 db = regs.a - tmp;
   (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((regs.a^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
@@ -1283,7 +1437,7 @@ static void Op81(void)  // CMPA #
 }
 static void Op82(void)  // SBCA #
 {
-  tmp = regs.RdMem(regs.pc++);  BYTE as = regs.a; 
+  tmp = regs.RdMem(regs.pc++);  uint8 as = regs.a;
   regs.a = regs.a - tmp - (regs.cc&0x01);
   (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1293,7 +1447,7 @@ static void Op82(void)  // SBCA #
 }
 static void Op83(void)  // SUBD #
 {
-  addr = FetchW();  WORD dr = (regs.a<<8)|regs.b, ds = dr;
+  addr = FetchW();  uint16 dr = (regs.a<<8)|regs.b, ds = dr;
   dr -= addr;
   (ds < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((ds^addr^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1337,10 +1491,10 @@ static void Op88(void)  // EORA #
 static void Op89(void)  // ADCA #
 {
   tmp = regs.RdMem(regs.pc++);
-  addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.a = addr & 0xFF;                       // Set accumulator
   (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative
@@ -1355,11 +1509,11 @@ static void Op8A(void)  // ORA #
         regs.clock += 2;
       }
 static void Op8B(void)  // ADDA #
-{       
+{
   tmp = regs.RdMem(regs.pc++);  addr = regs.a + tmp;
   (addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE); // Set Carry flag
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.a = addr & 0xFF;                       // Set accumulator
   (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -1368,20 +1522,24 @@ static void Op8B(void)  // ADDA #
 static void Op8C(void)  // CMPX #
 {
         addr = FetchW();
-        WORD dw = regs.x - addr;
+        uint16 dw = regs.x - addr;
         (regs.x < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
         ((regs.x^addr^dw^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
         (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
         regs.clock += 4;
 }
-static void Op8D(void)  // Bregs.s
-      {
-        tmp = regs.RdMem(regs.pc++);
-        regs.WrMem(--regs.s, regs.pc&0xFF);  regs.WrMem(--regs.s, regs.pc>>8);
-        regs.pc += SignedB(tmp);
-        regs.clock += 7;
-      }
+
+static void Op8D(void)							// Bregs.s
+{
+	uint16 word = (int16)(int8)regs.RdMem(regs.pc++);
+	regs.WrMem(--regs.s, regs.pc & 0xFF);
+	regs.WrMem(--regs.s, regs.pc >> 8);
+	regs.pc += word;
+
+	regs.clock += 7;
+}
+
 static void Op8E(void)  // LDX #
       {
         regs.x = FetchW();
@@ -1391,8 +1549,8 @@ static void Op8E(void)  // LDX #
         regs.clock += 3;
       }
 static void Op90(void)  // SUBA DP
-      { 
-        tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  BYTE as = regs.a; 
+      {
+        tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  uint8 as = regs.a;
         regs.a -= tmp;
         (regs.a == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (regs.a&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -1403,7 +1561,7 @@ static void Op90(void)  // SUBA DP
 static void Op91(void)  // CMPA DP
       {
         tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
-        BYTE db = regs.a - tmp;
+        uint8 db = regs.a - tmp;
         (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (db&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
         (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -1412,7 +1570,7 @@ static void Op91(void)  // CMPA DP
       }
 static void Op92(void)  // SBCA DP
 {
-  tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  BYTE as = regs.a; 
+  tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  uint8 as = regs.a;
   regs.a = regs.a - tmp - (regs.cc&0x01);
   (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1422,8 +1580,8 @@ static void Op92(void)  // SBCA DP
 }
 static void Op93(void)  // SUBD DP
 {
-  addr = (regs.dp<<8)|regs.RdMem(regs.pc++);  WORD dr = (regs.a<<8)|regs.b, ds = dr;
-  WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+  addr = (regs.dp<<8)|regs.RdMem(regs.pc++);  uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+  uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
   dr -= adr2;
   (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1475,10 +1633,10 @@ static void Op98(void)  // EORA DP
 static void Op99(void)  // ADCA DP
 {
   tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
-  addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.a = addr & 0xFF;                       // Set accumulator
   (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative
@@ -1493,12 +1651,12 @@ static void Op9A(void)  // ORA DP
         regs.clock += 4;
       }
 static void Op9B(void)  // ADDA DP
-{       
+{
   tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
-  addr = (WORD)regs.a + (WORD)tmp;
+  addr = (uint16)regs.a + (uint16)tmp;
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo 
+  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
   regs.a = addr & 0xFF;                       // Set accumulator
   (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -1507,8 +1665,8 @@ static void Op9B(void)  // ADDA DP
 static void Op9C(void)  // CMPX DP
       {
         addr = (regs.dp<<8)|regs.RdMem(regs.pc++);
-        WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
-        WORD dw = regs.x - adr2;
+        uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+        uint16 dw = regs.x - adr2;
         (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
         (regs.x < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -1541,8 +1699,8 @@ static void Op9F(void)  // STX DP
         regs.clock += 5;
       }
 static void OpA0(void)  // SUBA IDX
-      { 
-        tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  BYTE as = regs.a; 
+      {
+        tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  uint8 as = regs.a;
         regs.a -= tmp;
         (regs.a == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (regs.a&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -1553,7 +1711,7 @@ static void OpA0(void)  // SUBA IDX
 static void OpA1(void)  // CMPA IDX
       {
         tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
-        BYTE db = regs.a - tmp;
+        uint8 db = regs.a - tmp;
         (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (db&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
         (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -1562,7 +1720,7 @@ static void OpA1(void)  // CMPA IDX
       }
 static void OpA2(void)  // SBCA IDX
 {
-  tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  BYTE as = regs.a; 
+  tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  uint8 as = regs.a;
   regs.a = regs.a - tmp - (regs.cc&0x01);
   (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1572,8 +1730,8 @@ static void OpA2(void)  // SBCA IDX
 }
 static void OpA3(void)  // SUBD IDX
 {
-  addr = DecodeIDX(regs.RdMem(regs.pc++));  WORD dr = (regs.a<<8)|regs.b, ds = dr;
-  WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+  addr = DecodeIDX(regs.RdMem(regs.pc++));  uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+  uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
   dr -= adr2;
   (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1625,10 +1783,10 @@ static void OpA8(void)  // EORA IDX
 static void OpA9(void)  // ADCA IDX
 {
   tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
-  addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo 
+  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
   regs.a = addr & 0xFF;                       // Set accumulator
   (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -1643,12 +1801,12 @@ static void OpAA(void)  // ORA IDX
   regs.clock += 4;
 }
 static void OpAB(void)  // ADDA IDX
-{       
+{
   tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
-  addr = (WORD)regs.a + (WORD)tmp;
+  addr = (uint16)regs.a + (uint16)tmp;
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo 
+  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
   regs.a = addr & 0xFF;                       // Set accumulator
   (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -1657,8 +1815,8 @@ static void OpAB(void)  // ADDA IDX
 static void OpAC(void)  // CMPX IDX
 {
   addr = DecodeIDX(regs.RdMem(regs.pc++));
-  WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
-  WORD dw = regs.x - addr2;
+  uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+  uint16 dw = regs.x - addr2;
   (dw == 0    ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
   (dw&0x8000  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
   (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -1691,8 +1849,8 @@ static void OpAF(void)  // STX IDX
   regs.clock += 5;
 }
 static void OpB0(void)  // SUBA ABS
-      { 
-        tmp = regs.RdMem(FetchW());  BYTE as = regs.a; 
+      {
+        tmp = regs.RdMem(FetchW());  uint8 as = regs.a;
         regs.a -= tmp;
         (regs.a == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (regs.a&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -1703,7 +1861,7 @@ static void OpB0(void)  // SUBA ABS
 static void OpB1(void)  // CMPA ABS
       {
         tmp = regs.RdMem(FetchW());
-        BYTE db = regs.a - tmp;
+        uint8 db = regs.a - tmp;
         (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (db&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
         (regs.a < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -1712,7 +1870,7 @@ static void OpB1(void)  // CMPA ABS
       }
 static void OpB2(void)  // SBCA ABS
 {
-  tmp = regs.RdMem(FetchW());  BYTE as = regs.a; 
+  tmp = regs.RdMem(FetchW());  uint8 as = regs.a;
   regs.a = regs.a - tmp - (regs.cc&0x01);
   (as < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((as^tmp^regs.a^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1722,8 +1880,8 @@ static void OpB2(void)  // SBCA ABS
 }
 static void OpB3(void)  // SUBD ABS
 {
-  addr = FetchW();  WORD dr = (regs.a<<8)|regs.b, ds = dr;
-  WORD adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+  addr = FetchW();  uint16 dr = (regs.a<<8)|regs.b, ds = dr;
+  uint16 adr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
   dr -= adr2;
   (ds < adr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((ds^adr2^dr^(regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
@@ -1775,10 +1933,10 @@ static void OpB8(void)  // EORA ABS
 static void OpB9(void)  // ADCA ABS
 {
   tmp = regs.RdMem(FetchW());
-  addr = (WORD)regs.a + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.a + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.a = addr;                              // Set accumulator
   (regs.a == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.a&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -1793,9 +1951,9 @@ static void OpBA(void)  // ORA ABS
   regs.clock += 5;
 }
 static void OpBB(void)  // ADDA ABS
-{       
+{
   tmp = regs.RdMem(FetchW());
-  addr = (WORD)regs.a + (WORD)tmp;
+  addr = (uint16)regs.a + (uint16)tmp;
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.a^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
   ((regs.a^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
@@ -1806,8 +1964,8 @@ static void OpBB(void)  // ADDA ABS
 }
 static void OpBC(void)  // CMPX ABS
 {
-  addr = FetchW();  WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
-  WORD dw = regs.x - addr2;
+  addr = FetchW();  uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+  uint16 dw = regs.x - addr2;
   (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
   (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
   (regs.x < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -1818,7 +1976,7 @@ static void OpBD(void)  // JSR ABS
 {
   addr = FetchW();
   regs.WrMem(--regs.s, regs.pc&0xFF);  regs.WrMem(--regs.s, regs.pc>>8);
-  regs.pc = addr;                          // Go to absolute address (Not indir) 
+  regs.pc = addr;                          // Go to absolute address (Not indir)
   regs.clock += 8;
 }
 
@@ -1849,8 +2007,8 @@ static void OpBF(void)									// STX ABS
 }
 
 static void OpC0(void)  // SUBB #
-      { 
-        tmp = regs.RdMem(regs.pc++);  BYTE bs = regs.b; 
+      {
+        tmp = regs.RdMem(regs.pc++);  uint8 bs = regs.b;
         regs.b -= tmp;
         (regs.b == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (regs.b&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -1861,7 +2019,7 @@ static void OpC0(void)  // SUBB #
 static void OpC1(void)  // CMPB #
       {
         tmp = regs.RdMem(regs.pc++);
-        BYTE db = regs.b - tmp;
+        uint8 db = regs.b - tmp;
         (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
         ((regs.b^tmp^db^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
         (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
@@ -1870,7 +2028,7 @@ static void OpC1(void)  // CMPB #
       }
 static void OpC2(void)  // SBCB #
 {
-  tmp = regs.RdMem(regs.pc++);  BYTE bs = regs.b; 
+  tmp = regs.RdMem(regs.pc++);  uint8 bs = regs.b;
   regs.b = regs.b - tmp - (regs.cc&0x01);
   (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -1925,10 +2083,10 @@ static void OpC8(void)  // EORB #
 static void OpC9(void)  // ADCB #
 {
   tmp = regs.RdMem(regs.pc++);
-  addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
   regs.b = addr & 0xFF;                       // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -1943,11 +2101,11 @@ static void OpCA(void)  // ORB #
         regs.clock += 2;
       }
 static void OpCB(void)  // ADDB #
-{       
+{
   tmp = regs.RdMem(regs.pc++);  addr = regs.b + tmp;
   (addr > 0xFF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
   regs.b = addr & 0xFF;                       // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -1970,8 +2128,8 @@ static void OpCE(void)  // LDU #
   regs.clock += 3;
 }
 static void OpD0(void)  // SUBB DP
-{ 
-  tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  BYTE bs = regs.b; 
+{
+  tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  uint8 bs = regs.b;
   regs.b -= tmp;
   (regs.b == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
   (regs.b&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -1982,7 +2140,7 @@ static void OpD0(void)  // SUBB DP
 static void OpD1(void)  // CMPB DP
 {
   tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
-  BYTE db = regs.b - tmp;
+  uint8 db = regs.b - tmp;
   (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
   (db&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
   (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -1991,7 +2149,7 @@ static void OpD1(void)  // CMPB DP
 }
 static void OpD2(void)  // SBCB DP
 {
-  tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  BYTE bs = regs.b; 
+  tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));  uint8 bs = regs.b;
   regs.b = regs.b - tmp - (regs.cc&0x01);
   (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -2002,7 +2160,7 @@ static void OpD2(void)  // SBCB DP
 static void OpD3(void)  // ADDD DP
 {
   addr = (regs.dp<<8)|regs.RdMem(regs.pc++);  long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
-  WORD adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+  uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
   dr += adr2;
   (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   dr &= 0xFFFF;
@@ -2055,10 +2213,10 @@ static void OpD8(void)  // EORB DP
 static void OpD9(void)  // ADCB DP
 {
   tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
-  addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.b = addr;                              // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -2073,12 +2231,12 @@ static void OpDA(void)  // ORB DP
         regs.clock += 4;
       }
 static void OpDB(void)  // ADDB DP
-{       
+{
   tmp = regs.RdMem((regs.dp<<8)|regs.RdMem(regs.pc++));
-  addr = (WORD)regs.b + (WORD)tmp;
+  addr = (uint16)regs.b + (uint16)tmp;
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.b = addr & 0xFF;                       // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -2121,8 +2279,8 @@ static void OpDF(void)  // STU DP
   regs.clock += 5;
 }
 static void OpE0(void)  // SUBB IDX
-{ 
-  tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  BYTE bs = regs.b; 
+{
+  tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  uint8 bs = regs.b;
   regs.b -= tmp;
   (regs.b == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
   (regs.b&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -2133,7 +2291,7 @@ static void OpE0(void)  // SUBB IDX
 static void OpE1(void)  // CMPB IDX
 {
   tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
-  BYTE db = regs.b - tmp;
+  uint8 db = regs.b - tmp;
   (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
   (db&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
   (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2142,7 +2300,7 @@ static void OpE1(void)  // CMPB IDX
 }
 static void OpE2(void)  // SBCB IDX
 {
-  tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  BYTE bs = regs.b; 
+  tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));  uint8 bs = regs.b;
   regs.b = regs.b - tmp - (regs.cc&0x01);
   (bs < (tmp+(regs.cc&0x01)) ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   ((bs^tmp^regs.b^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
@@ -2153,7 +2311,7 @@ static void OpE2(void)  // SBCB IDX
 static void OpE3(void)  // ADDD IDX
 {
   addr = DecodeIDX(regs.RdMem(regs.pc++));  long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
-  WORD adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+  uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
   dr += adr2;
   (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   dr &= 0xFFFF;
@@ -2206,10 +2364,10 @@ static void OpE8(void)  // EORB IDX
 static void OpE9(void)  // ADCB IDX
 {
   tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
-  addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.b = addr;                              // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -2224,12 +2382,12 @@ static void OpEA(void)  // ORB IDX
         regs.clock += 4;
       }
 static void OpEB(void)  // ADDB IDX
-{       
+{
   tmp = regs.RdMem(DecodeIDX(regs.RdMem(regs.pc++)));
-  addr = (WORD)regs.b + (WORD)tmp;
+  addr = (uint16)regs.b + (uint16)tmp;
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflow
   regs.b = addr;                              // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -2272,8 +2430,8 @@ static void OpEF(void)  // STU IDX
   regs.clock += 5;
 }
 static void OpF0(void)  // SUBB ABS
-      { 
-        tmp = regs.RdMem(FetchW());  BYTE bs = regs.b; 
+      {
+        tmp = regs.RdMem(FetchW());  uint8 bs = regs.b;
         regs.b -= tmp;
         (regs.b == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (regs.b&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -2283,7 +2441,7 @@ static void OpF0(void)  // SUBB ABS
 static void OpF1(void)  // CMPB ABS
       {
         tmp = regs.RdMem(FetchW());
-        BYTE db = regs.b - tmp;
+        uint8 db = regs.b - tmp;
         (db == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (db&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
         (regs.b < tmp ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2292,7 +2450,7 @@ static void OpF1(void)  // CMPB ABS
       }
 static void OpF2(void)  // SBCB ABS
 {
-  tmp = regs.RdMem(FetchW());  BYTE bs = regs.b; 
+  tmp = regs.RdMem(FetchW());  uint8 bs = regs.b;
   regs.b = regs.b - tmp - (regs.cc&0x01);
   (regs.b == 0  ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
   (regs.b&0x80  ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
@@ -2303,7 +2461,7 @@ static void OpF2(void)  // SBCB ABS
 static void OpF3(void)  // ADDD ABS
 {
   addr = FetchW();  long dr = ((regs.a<<8)|regs.b)&0xFFFF, ds = dr;
-  WORD adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
+  uint16 adr2 = (regs.RdMem(addr)<<8)|regs.RdMem(addr+1);
   dr += adr2;
   (dr > 0xFFFF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
   dr &= 0xFFFF;
@@ -2356,10 +2514,10 @@ static void OpF8(void)  // EORB ABS
 static void OpF9(void)  // ADCB ABS
 {
   tmp = regs.RdMem(FetchW());
-  addr = (WORD)regs.b + (WORD)tmp + (WORD)(regs.cc&0x01);
+  addr = (uint16)regs.b + (uint16)tmp + (uint16)(regs.cc&0x01);
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
   regs.b = addr & 0xFF;                       // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -2372,14 +2530,14 @@ static void OpFA(void)  // ORB ABS
         (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
         (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
         regs.clock += 5;
-      }       
+      }
 static void OpFB(void)  // ADDB ABS
-{       
+{
   tmp = regs.RdMem(FetchW());
-  addr = (WORD)regs.b + (WORD)tmp;
+  addr = (uint16)regs.b + (uint16)tmp;
   (addr > 0x00FF ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Set Carry flag
   ((regs.b^tmp^addr)&0x10 ? regs.cc |= 0x20 : regs.cc &= 0xDF);  // Set Half carry
-  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo 
+  ((regs.b^tmp^addr^(regs.cc<<7))&0x80 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerflo
   regs.b = addr & 0xFF;                       // Set accumulator
   (regs.b == 0 ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Set Zero flag
   (regs.b&0x80 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Set Negative flag
@@ -2426,113 +2584,171 @@ static void OpFF(void)  // STU ABS
 // Page one opcodes' execute code
 //
 
-static void Op1021(void)  // LBRN
+static void Op1021(void)						// LBRN
 {
-  addr = FetchW();
-  regs.clock += 5;
+	addr = FetchW();
+
+	regs.clock += 5;
 }
-static void Op1022(void)  // LBHI
+
+static void Op1022(void)						// LBHI
 {
-  addr = FetchW();
-  if (!((regs.cc&0x01)|(regs.cc&0x04)))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (!((regs.cc & 0x01) | (regs.cc & 0x04)))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op1023(void)  // LBLS
+
+static void Op1023(void)						// LBLS
 {
-  addr = FetchW();
-  if ((regs.cc&0x01)|(regs.cc&0x04))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if ((regs.cc & 0x01) | (regs.cc & 0x04))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op1024(void)  // LBCC (LBHS)
+
+static void Op1024(void)						// LBCC (LBHS)
 {
-  addr = FetchW();
-  if (!(regs.cc&0x01))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (!(regs.cc & 0x01))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op1025(void)  // LBCS (LBLO)
+
+static void Op1025(void)						// LBCS (LBLO)
 {
-  addr = FetchW();
-  if (regs.cc&0x01)  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (regs.cc & 0x01)
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op1026(void)  // LBNE
+
+static void Op1026(void)						// LBNE
 {
-  addr = FetchW();
-  if (!(regs.cc&0x04))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (!(regs.cc & 0x04))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op1027(void)  // LBEQ
+
+static void Op1027(void)						// LBEQ
 {
-  addr = FetchW();
-  if (regs.cc&0x04)  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (regs.cc & 0x04)
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op1028(void)  // LBVC
+
+static void Op1028(void)						// LBVC
 {
-  addr = FetchW();
-  if (!(regs.cc&0x02))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (!(regs.cc & 0x02))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op1029(void)  // LBVS
+
+static void Op1029(void)						// LBVS
 {
-  addr = FetchW();
-  if (regs.cc&0x02)  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (regs.cc & 0x02)
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op102A(void)  // LBPL
+
+static void Op102A(void)						// LBPL
 {
-  addr = FetchW();
-  if (!(regs.cc&0x08))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (!(regs.cc & 0x08))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op102B(void)  // LBMI
+
+static void Op102B(void)						// LBMI
 {
-  addr = FetchW();
-  if (regs.cc&0x08)  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (regs.cc & 0x08)
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op102C(void)  // LBGE
+
+static void Op102C(void)						// LBGE
 {
-  addr = FetchW();
-  if (!(((regs.cc&0x08) >> 2) ^ (regs.cc&0x02)))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (!(((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op102D(void)  // LBLT
+
+static void Op102D(void)						// LBLT
 {
-  addr = FetchW();
-  if (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op102E(void)  // LBGT
+
+static void Op102E(void)						// LBGT
 {
-  addr = FetchW();
-  if (!((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))))  regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if (!((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02))))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
-static void Op102F(void)  // LBLE
+
+static void Op102F(void)						// LBLE
 {
-  addr = FetchW();
-  if ((regs.cc&0x04) | (((regs.cc&0x08) >> 2) ^ (regs.cc&0x02))) regs.pc += SignedW(addr);
-  regs.clock += 5;
+	uint16 word = FetchW();
+
+	if ((regs.cc & 0x04) | (((regs.cc & 0x08) >> 2) ^ (regs.cc & 0x02)))
+		regs.pc += word;
+
+	regs.clock += 5;
 }
+
 static void Op103F(void)  // SWI2 (Not yet implemented)
 {
   regs.clock += 20;
 }
 static void Op1083(void)  // CMPD #
     {
-      addr = FetchW();  WORD dr = (regs.a<<8)|regs.b;
-      WORD dw = dr - addr;
+      addr = FetchW();  uint16 dr = (regs.a<<8)|regs.b;
+      uint16 dw = dr - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
-      ((dr^addr^dw^((WORD)regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
+      ((dr^addr^dw^((uint16)regs.cc<<15))&0x8000 ? regs.cc |= 0x02 : regs.cc &= 0xFD); // oVerfl
       regs.clock += 5;
     }
 static void Op108C(void)  // CMPY #
     {
       addr = FetchW();
-      WORD dw = regs.y - addr;
+      uint16 dw = regs.y - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2549,9 +2765,9 @@ static void Op108E(void)  // LDY #
     }
 static void Op1093(void)  // CMPD DP
     {
-      WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++), dr = (regs.a<<8)|regs.b;
+      uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++), dr = (regs.a<<8)|regs.b;
       addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
-      WORD dw = dr - addr;
+      uint16 dw = dr - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (dr < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2560,9 +2776,9 @@ static void Op1093(void)  // CMPD DP
     }
 static void Op109C(void)  // CMPY DP
     {
-      WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+      uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
       addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
-      WORD dw = regs.y - addr;
+      uint16 dw = regs.y - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2591,9 +2807,9 @@ static void Op109F(void)  // STY DP
     }
 static void Op10A3(void)  // CMPD IDX
 {
-  WORD adr2 = DecodeIDX(regs.RdMem(regs.pc++)), dr = (regs.a<<8)|regs.b;
+  uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++)), dr = (regs.a<<8)|regs.b;
   addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
-  WORD dw = dr - addr;
+  uint16 dw = dr - addr;
   regs.cc &= 0xF0;                              // CLC CLV CLZ CLN
   if (dr < addr)  regs.cc |= 0x01;              // Set Carry flag
   if ((dr^addr^dw^(regs.cc<<15))&0x8000)  regs.cc |= 0x02; // Set oVerflow
@@ -2603,9 +2819,9 @@ static void Op10A3(void)  // CMPD IDX
 }
 static void Op10AC(void)  // CMPY IDX
     {
-      WORD adr2 = DecodeIDX(regs.RdMem(regs.pc++));
+      uint16 adr2 = DecodeIDX(regs.RdMem(regs.pc++));
       addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
-      WORD dw = regs.y - addr;
+      uint16 dw = regs.y - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.y < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2632,9 +2848,9 @@ static void Op10AF(void)  // STY IDX
     }
 static void Op10B3(void)  // CMPD ABS
     {
-      addr = FetchW();  WORD dr = (regs.a<<8)|regs.b;
-      WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
-      WORD dw = dr - addr2;
+      addr = FetchW();  uint16 dr = (regs.a<<8)|regs.b;
+      uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+      uint16 dw = dr - addr2;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (dr < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2643,8 +2859,8 @@ static void Op10B3(void)  // CMPD ABS
     }
 static void Op10BC(void)  // CMPY ABS
     {
-      addr = FetchW();  WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
-      WORD dw = regs.y - addr2;
+      addr = FetchW();  uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+      uint16 dw = regs.y - addr2;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.y < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2684,7 +2900,7 @@ static void Op10DE(void)  // LDS DP
       regs.cc &= 0xFD;                              // CLV
       (regs.s == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (regs.s&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
-      regs.clock += 6;                     
+      regs.clock += 6;
     }
 static void Op10DF(void)  // STS DP
     {
@@ -2743,7 +2959,7 @@ static void Op113F(void)  // SWI3
 static void Op1183(void)  // CMPU #
     {
       addr = FetchW();
-      WORD dw = regs.u - addr;
+      uint16 dw = regs.u - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2753,7 +2969,7 @@ static void Op1183(void)  // CMPU #
 static void Op118C(void)  // CMPS #
     {
       addr = FetchW();
-      WORD dw = regs.s - addr;
+      uint16 dw = regs.s - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2762,9 +2978,9 @@ static void Op118C(void)  // CMPS #
     }
 static void Op1193(void)  // CMPU DP
     {
-      WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+      uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
       addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
-      WORD dw = regs.u - addr;
+      uint16 dw = regs.u - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2773,9 +2989,9 @@ static void Op1193(void)  // CMPU DP
     }
 static void Op119C(void)  // CMPS DP
     {
-      WORD adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
+      uint16 adr2 = (regs.dp<<8)|regs.RdMem(regs.pc++);
       addr = (regs.RdMem(adr2)<<8) | regs.RdMem(adr2+1);
-      WORD dw = regs.s - addr;
+      uint16 dw = regs.s - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2784,9 +3000,9 @@ static void Op119C(void)  // CMPS DP
     }
 static void Op11A3(void)  // CMPU IDX
     {
-      WORD addr2 = DecodeIDX(regs.RdMem(regs.pc++));
+      uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
       addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
-      WORD dw = regs.u - addr;
+      uint16 dw = regs.u - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.u < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2795,9 +3011,9 @@ static void Op11A3(void)  // CMPU IDX
     }
 static void Op11AC(void)  // CMPS IDX
     {
-      WORD addr2 = DecodeIDX(regs.RdMem(regs.pc++));
+      uint16 addr2 = DecodeIDX(regs.RdMem(regs.pc++));
       addr = (regs.RdMem(addr2)<<8) | regs.RdMem(addr2+1);
-      WORD dw = regs.s - addr;
+      uint16 dw = regs.s - addr;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.s < addr ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2806,8 +3022,8 @@ static void Op11AC(void)  // CMPS IDX
     }
 static void Op11B3(void)  // CMPU ABS
     {
-      addr = FetchW();  WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
-      WORD dw = regs.u - addr2;
+      addr = FetchW();  uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+      uint16 dw = regs.u - addr2;
       (dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
       (dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
       (regs.u < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2817,8 +3033,8 @@ static void Op11B3(void)  // CMPU ABS
 
 static void Op11BC(void)  // CMPS ABS
 {
-	addr = FetchW();  WORD addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
-	WORD dw = regs.s - addr2;
+	addr = FetchW();  uint16 addr2 = (regs.RdMem(addr)<<8) | regs.RdMem(addr+1);
+	uint16 dw = regs.s - addr2;
 	(dw == 0   ? regs.cc |= 0x04 : regs.cc &= 0xFB);  // Adjust Zero flag
 	(dw&0x8000 ? regs.cc |= 0x08 : regs.cc &= 0xF7);  // Adjust Negative flag
 	(regs.s < addr2 ? regs.cc |= 0x01 : regs.cc &= 0xFE);  // Adjust Carry flag
@@ -2827,63 +3043,127 @@ static void Op11BC(void)  // CMPS ABS
 }
 
 //temp, for testing...
-/*static BYTE backTrace[256];
-static WORD btPC[256];
+#ifdef __DEBUG__
+static uint8 backTrace[256];
+static uint16 btPC[256];
 static int btPtr = 0;//*/
+#endif
 static void Op__(void)									// Illegal opcode
 {
 	regs.clock++;
 //	illegal = true;
 	regs.cpuFlags |= V6809_STATE_ILLEGAL_INST;
+#ifdef __DEBUG__
 /*WriteLog("V6809: Executed illegal opcode %02X at PC=%04X...\n\nBacktrace:\n\n", regs.RdMem(regs.pc - 1), regs.pc - 1);
 for(int i=0; i<256; i++)
 {
-	dpc = btPC[(btPtr+i)&0xFF];
-	Decode_6809();
+	Decode6809(btPC[(btPtr + i) & 0xFF]);
+	WriteLog("\n");
 }//*/
+#endif
 }
 
 
 //
 // Internal "memcpy" (so we don't have to link with any external libraries!)
 //
-static void myMemcpy(void * dst, void * src, DWORD size)
+static void myMemcpy(void * dst, void * src, uint32 size)
 {
-	BYTE * d = (BYTE *)dst, * s = (BYTE *)src;
+	uint8 * d = (uint8 *)dst, * s = (uint8 *)src;
 
-	for(DWORD i=0; i<size; i++)
+	for(uint32 i=0; i<size; i++)
 		d[i] = s[i];
 }
 
 //
 // Function to execute 6809 instructions
 //
-void Execute6809(V6809REGS * context, DWORD cycles)
+//#define DEBUG_ILLEGAL
+#ifdef DEBUG_ILLEGAL
+#include "log.h"
+#include "dis6809.h"
+uint8 btPtr = 0;
+uint8 backTrace[256];
+V6809REGS btRegs[256];
+bool tripped = false;
+#endif
+#ifdef __DEBUG__
+//Here so this can be externally linked
+bool disasm = false;
+//bool disasm = true;
+#endif
+void Execute6809(V6809REGS * context, uint32 cycles)
 {
+	// If this is not in place, the clockOverrun calculations can cause the V6809 to get
+	// stuck in an infinite loop.
+	if (cycles == 0)							// Nothing to do, so bail!
+		return;
+
 	myMemcpy(&regs, context, sizeof(V6809REGS));
 
 	// Execute here...
-DWORD clockSave = regs.clock;
-regs.clock = 0;
-	while (regs.clock < cycles)
+
+	// Since we can't guarantee that we'll execute the number of cycles passed in
+	// exactly, we have to keep track of how much we overran the number of cycles
+	// the last time we executed. Since we already executed those cycles, this time
+	// through we remove them from the cycles passed in in order to come out
+	// approximately even. Over the long run, this unevenness in execution times
+	// evens out.
+	uint64 endCycles = regs.clock + (uint64)(cycles - regs.clockOverrun);
+
+	while (regs.clock < endCycles)
+	{
+#ifdef DEBUG_ILLEGAL
+if (!tripped)
+{
+	backTrace[btPtr] = regs.RdMem(regs.pc);
+	btRegs[btPtr] = regs;
+	btPtr = (btPtr + 1) & 0xFF;
+
+	if (regs.cpuFlags & V6809_STATE_ILLEGAL_INST)
 	{
-/*static bool disasm = false;
-if (regs.pc == 0x15BA)	disasm = true;
-if (disasm) { dpc = regs.pc; Decode_6809(); }
-if (regs.pc == 0x164A)	disasm = false;//*/
+		WriteLog("V6809: Executed illegal instruction!!!!\n\nBacktrace:\n\n");
+		regs.cpuFlags &= ~V6809_STATE_ILLEGAL_INST;
+
+		for(uint16 i=btPtr; i<btPtr+256; i++)
+		{
+			Decode6809(btRegs[i & 0xFF].pc);
+// Note that these values are *before* execution, so stale...
+			WriteLog("\n\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+				btRegs[i & 0xFF].a, btRegs[i & 0xFF].b, btRegs[i & 0xFF].cc, btRegs[i & 0xFF].dp, btRegs[i & 0xFF].x, btRegs[i & 0xFF].y, btRegs[i & 0xFF].s, btRegs[i & 0xFF].u, btRegs[i & 0xFF].pc);//*/
+		}
+
+		tripped = true;
+	}
+}
+#endif
+#ifdef __DEBUG__
+//Decode6809(regs.pc);
+if (disasm) Decode6809(regs);
+/*//if (regs.pc == 0x15BA)	disasm = true;
+//if (regs.pc == 0xFE76)	disasm = true;
+if (regs.x == 0xFED4)	disasm = true;
+if (disasm) Decode6809(regs.pc);
+//if (regs.pc == 0x164A)	disasm = false;//*/
 
 //temp, for testing...
 /*backTrace[btPtr] = regs.RdMem(regs.pc);
 btPC[btPtr] = regs.pc;
-btPtr = (btPtr++) & 0xFF;//*/
+btPtr = (btPtr + 1) & 0xFF;//*/
+#endif
 		exec_op0[regs.RdMem(regs.pc++)]();
 
 		// Handle any pending interrupts
 
-		DWORD flags = context->cpuFlags;
+// Hmm, this is bad and only works when flags are changed OUTSIDE of the running context...
+//		uint32 flags = context->cpuFlags;
+		uint32 flags = regs.cpuFlags;
 
 		if (flags & V6809_ASSERT_LINE_RESET)			// *** RESET handler ***
 		{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: RESET line asserted!\n");
+#endif
 			regs.cc |= (FLAG_F | FLAG_I);				// Set F, I
 			regs.dp = 0;								// Reset direct page register
 			regs.pc = RdMemW(0xFFFE);					// And load PC with the RESET vector
@@ -2892,6 +3172,9 @@ btPtr = (btPtr++) & 0xFF;//*/
 		}
 		else if (flags & V6809_ASSERT_LINE_NMI)			// *** NMI handler ***
 		{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: NMI line asserted!\n");
+#endif
 			regs.cc |= FLAG_E;							// Set the Entire flag
 
 			regs.WrMem(--regs.s, regs.pc & 0xFF);		// Save all regs...
@@ -2910,13 +3193,19 @@ btPtr = (btPtr++) & 0xFF;//*/
 			regs.cc |= (FLAG_I | FLAG_F);				// Set IRQ/FIRQ suppress flags
 			regs.pc = RdMemW(0xFFFC);					// And load PC with the NMI vector
 			regs.clock += 19;
-			context->cpuFlags &= ~V6809_ASSERT_LINE_NMI;// Reset the asserted line (NMI)...
-			regs.cpuFlags &= ~V6809_ASSERT_LINE_NMI;	// Reset the asserted line (NMI)...
+//			context->cpuFlags &= ~V6809_ASSERT_LINE_NMI;// Reset the asserted line (NMI)...
+//			regs.cpuFlags &= ~V6809_ASSERT_LINE_NMI;	// Reset the asserted line (NMI)...
 		}
 		else if (flags & V6809_ASSERT_LINE_FIRQ)		// *** FIRQ handler ***
 		{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: FIRQ line asserted!\n");
+#endif
 			if (!(regs.cc & FLAG_F))					// Is the FIRQ masked (F == 1)?
 			{
+#ifdef __DEBUG__
+if (disasm) WriteLog("       FIRQ taken...\n");
+#endif
 				regs.cc &= ~FLAG_E;						// Clear the Entire flag
 
 				regs.WrMem(--regs.s, regs.pc & 0xFF);	// Save PC, CC regs...
@@ -2926,14 +3215,20 @@ btPtr = (btPtr++) & 0xFF;//*/
 				regs.cc |= (FLAG_I | FLAG_F);			// Set IRQ/FIRQ suppress flags
 				regs.pc = RdMemW(0xFFF6);				// And load PC with the IRQ vector
 				regs.clock += 10;
-				context->cpuFlags &= ~V6809_ASSERT_LINE_FIRQ;	// Reset the asserted line (FIRQ)...
-				regs.cpuFlags &= ~V6809_ASSERT_LINE_FIRQ;	// Reset the asserted line (FIRQ)...
+//				context->cpuFlags &= ~V6809_ASSERT_LINE_FIRQ;	// Reset the asserted line (FIRQ)...
+//				regs.cpuFlags &= ~V6809_ASSERT_LINE_FIRQ;	// Reset the asserted line (FIRQ)...
 			}
 		}
 		else if (flags & V6809_ASSERT_LINE_IRQ)			// *** IRQ handler ***
 		{
+#ifdef __DEBUG__
+if (disasm) WriteLog("\nV6809: IRQ line asserted!\n");
+#endif
 			if (!(regs.cc & FLAG_I))					// Is the IRQ masked (I == 1)?
 			{
+#ifdef __DEBUG__
+if (disasm) WriteLog("       IRQ taken...\n");
+#endif
 				regs.cc |= FLAG_E;						// Set the Entire flag
 
 				regs.WrMem(--regs.s, regs.pc & 0xFF);	// Save all regs...
@@ -2952,14 +3247,98 @@ btPtr = (btPtr++) & 0xFF;//*/
 				regs.cc |= FLAG_I;						// Specs say that it doesn't affect FIRQ... or FLAG_F [WAS: Set IRQ/FIRQ suppress flags]
 				regs.pc = RdMemW(0xFFF8);				// And load PC with the IRQ vector
 				regs.clock += 19;
-				context->cpuFlags &= ~V6809_ASSERT_LINE_IRQ;	// Reset the asserted line (IRQ)...
-				regs.cpuFlags &= ~V6809_ASSERT_LINE_IRQ;	// Reset the asserted line (IRQ)...
+// Apparently, not done here!
+// Need to put IRQ handling in somewhere... It shouldn't be cleared here!
+//				context->cpuFlags &= ~V6809_ASSERT_LINE_IRQ;	// Reset the asserted line (IRQ)...
+//				regs.cpuFlags &= ~V6809_ASSERT_LINE_IRQ;	// Reset the asserted line (IRQ)...
 			}
 		}
-/*if (disasm) WriteLog("\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+#ifdef __DEBUG__
+if (disasm) WriteLog("\tCC=%s%s%s%s%s%s%s%s A=%02X B=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
+	(regs.cc & FLAG_E ? "E" : "-"), (regs.cc & FLAG_F ? "F" : "-"), (regs.cc & FLAG_H ? "H" : "-"),
+	(regs.cc & FLAG_I ? "I" : "-"), (regs.cc & FLAG_N ? "N" : "-"), (regs.cc & FLAG_Z ? "Z" : "-"),
+	(regs.cc & FLAG_V ? "V" : "-"), (regs.cc & FLAG_C ? "C" : "-"),
+	regs.a, regs.b, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
+/*WriteLog("\tA=%02X B=%02X CC=%02X DP=%02X X=%04X Y=%04X S=%04X U=%04X PC=%04X\n",
 	regs.a, regs.b, regs.cc, regs.dp, regs.x, regs.y, regs.s, regs.u, regs.pc);//*/
+#endif
 	}
-regs.clock += clockSave;
+	// Keep track of how much we overran so we can adjust on the next run...
+	regs.clockOverrun = (uint32)(regs.clock - endCycles);
 
 	myMemcpy(context, &regs, sizeof(V6809REGS));
+
+#ifdef __DEBUG__
+	if (disasm)
+		WriteLog("\n*** CONTEXT SWITCH ***\n\n");
+#endif
+}
+
+//
+// Get the clock of the currently executing CPU
+//
+uint64 GetCurrentV6809Clock(void)
+{
+	return regs.clock;
+}
+
+//
+// Get the PC of the currently executing CPU
+//
+uint16 GetCurrentV6809PC(void)
+{
+	return regs.pc;
+}
+
+// Set a line of the currently executing CPU
+void SetLineOfCurrentV6809(uint32 line)
+{
+	regs.cpuFlags |= line;
+}
+
+// Clear a line of the currently executing CPU
+void ClearLineOfCurrentV6809(uint32 line)
+{
+#ifdef __DEBUG__
+if (disasm)
+	WriteLog("V6809: Clearing line %s...", (line == V6809_ASSERT_LINE_IRQ ? "IRQ" : "OTHER"));
+#endif
+	regs.cpuFlags &= ~line;
 }
+
+/*
+Small problem: IRQ is not getting cleared!
+
+
+820E: 9A 01          ORA   $01
+V6809: IRQ line asserted!
+        CC=EF-I-Z-- A=00 B=00 DP=56 X=533C Y=53C0 S=57EE U=8215 PC=8210
+8210: A6 C6          LDA   (A),U
+V6809: IRQ line asserted!
+        CC=EF-I---- A=01 B=00 DP=56 X=533C Y=53C0 S=57EE U=8215 PC=8212
+
+*** CONTEXT SWITCH ***
+
+818E: B7 80 00       STA   $8000
+V6809: IRQ line asserted!
+        CC=EF-I---- A=02 B=00 DP=16 X=81AD Y=6224 S=03F2 U=89D7 PC=8191
+8191: B7 88 00       STA   $8800
+WriteMem: CPU #2 Acknowledging IRQ...
+V6809: Clearing line IRQ...
+V6809: IRQ line asserted!
+        CC=EF-I---- A=02 B=00 DP=16 X=81AD Y=6224 S=03F2 U=89D7 PC=8194
+8194: 3B             RTI
+V6809: IRQ line asserted!
+       IRQ taken...
+        CC=EF-I-Z-- A=03 B=00 DP=16 X=1308 Y=6224 S=03F2 U=B0DC PC=8173
+
+*** CONTEXT SWITCH ***
+
+8212: 97 1E          STA   $1E
+V6809: IRQ line asserted!
+        CC=EF-I---- A=01 B=00 DP=56 X=533C Y=53C0 S=57EE U=8215 PC=8214
+8214: 39             RTS
+V6809: IRQ line asserted!
+
+
+*/
\ No newline at end of file