X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fv63701.cpp;h=31e2fb07e5bfdf85f83f400c7e9fecb664ca83a0;hb=8ba4c4438d796f83851cd53914dff928193ed658;hp=ea225bd0c6c7642bdfe3ec8df4d013322762ca1e;hpb=d22f243fc585a46e4c29d00bd32727d9f9f4055c;p=thunder diff --git a/src/v63701.cpp b/src/v63701.cpp index ea225bd..31e2fb0 100644 --- a/src/v63701.cpp +++ b/src/v63701.cpp @@ -29,14 +29,6 @@ // work well. It's a fair sight better than the one that's in MAME, // that's for sure. :-D -// Some random thoughts: Could there be a performance gain by breaking -// out the flags in regs.cc into separate uint8_t variables (or bools)? -// You'd have to convert on entering and exiting the emulation loop, but I -// think the perfomance hit would be negligible compared to the gain in not -// having to mask and shift flags all the time. Investigate after the -// conversion to macro style opcodes is completed. :-) -// [DONE--remain to be seen if there is any performance increase] - #define __DEBUG__ #define TEST_DONT_BRANCH_OPTIMIZATION @@ -143,7 +135,6 @@ static uint16_t RdMemW(uint16_t); static uint16_t FetchMemW(uint16_t); static inline void HandleInterrupt(uint16_t, uint16_t flag = 0); - // // Read a word out of 63701 memory (little endian format) // @@ -152,7 +143,6 @@ static inline uint16_t RdMemW(uint16_t address) return (uint16_t)(regs.RdMem(address) << 8) | regs.RdMem(address + 1); } - // // Fetch a word out of 63701 memory (little endian format). Increments PC // @@ -162,7 +152,6 @@ static inline uint16_t FetchMemW(uint16_t address) return (uint16_t)(regs.RdMem(address) << 8) | regs.RdMem(address + 1); } - // // 63701 OPCODE IMPLEMENTATION // @@ -204,97 +193,83 @@ static void Op8B(void) // ADDA # OP_ADD_HANDLER(m, regs.d.acc.a); } - static void Op9B(void) // ADDA ZP { uint16_t m = READ_ZP; OP_ADD_HANDLER(m, regs.d.acc.a); } - static void OpAB(void) // ADDA ZP, X { uint16_t m = READ_ZP_X; OP_ADD_HANDLER(m, regs.d.acc.a); } - static void OpBB(void) // ADDA ABS { uint16_t m = READ_ABS; OP_ADD_HANDLER(m, regs.d.acc.a); } - static void OpCB(void) // ADDB # { uint16_t m = READ_IMM; OP_ADD_HANDLER(m, regs.d.acc.b); } - static void OpDB(void) // ADDB ZP { uint16_t m = READ_ZP; OP_ADD_HANDLER(m, regs.d.acc.b); } - static void OpEB(void) // ADDB ZP, X { uint16_t m = READ_ZP_X; OP_ADD_HANDLER(m, regs.d.acc.b); } - static void OpFB(void) // ADDB ABS { uint16_t m = READ_ABS; OP_ADD_HANDLER(m, regs.d.acc.b); } - static void Op1B(void) // ABA { OP_ADD_HANDLER(regs.d.acc.b, regs.d.acc.a); } - static void Op3A(void) // ABX { // Seems this one does *not* affect any flags... regs.x += (uint16_t)regs.d.acc.b; } - static void OpC3(void) // ADDD # { uint16_t m = READ_IMM16; OP_ADD_HANDLER16(m, regs.d.word); } - static void OpD3(void) // ADDD ZP { uint16_t m = READ_ZP16; OP_ADD_HANDLER16(m, regs.d.word); } - static void OpE3(void) // ADDD ZP, X { uint16_t m = READ_ZP_X16; OP_ADD_HANDLER16(m, regs.d.word); } - static void OpF3(void) // ADDD ABS { uint16_t m = READ_ABS16; OP_ADD_HANDLER16(m, regs.d.word); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -318,56 +293,48 @@ static void Op89(void) // ADCA # OP_ADC_HANDLER(m, regs.d.acc.a); } - static void Op99(void) // ADCA ZP { uint16_t m = READ_ZP; OP_ADC_HANDLER(m, regs.d.acc.a); } - static void OpA9(void) // ADCA ZP, X { uint16_t m = READ_ZP_X; OP_ADC_HANDLER(m, regs.d.acc.a); } - static void OpB9(void) // ADCA ABS { uint16_t m = READ_ABS; OP_ADC_HANDLER(m, regs.d.acc.a); } - static void OpC9(void) // ADCB # { uint16_t m = READ_IMM; OP_ADC_HANDLER(m, regs.d.acc.b); } - static void OpD9(void) // ADCB ZP { uint16_t m = READ_ZP; OP_ADC_HANDLER(m, regs.d.acc.b); } - static void OpE9(void) // ADCB ZP, X { uint16_t m = READ_ZP_X; OP_ADC_HANDLER(m, regs.d.acc.b); } - static void OpF9(void) // ADCB ABS { uint16_t m = READ_ABS; OP_ADC_HANDLER(m, regs.d.acc.b); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -388,56 +355,48 @@ static void Op84(void) // ANDA # OP_AND_HANDLER(m, regs.d.acc.a); } - static void Op94(void) // ANDA ZP { uint8_t m = READ_ZP; OP_AND_HANDLER(m, regs.d.acc.a); } - static void OpA4(void) // ANDA ZP, X { uint16_t m = READ_ZP_X; OP_AND_HANDLER(m, regs.d.acc.a); } - static void OpB4(void) // ANDA ABS { uint16_t m = READ_ABS; OP_AND_HANDLER(m, regs.d.acc.a); } - static void OpC4(void) // ANDB # { uint8_t m = READ_IMM; OP_AND_HANDLER(m, regs.d.acc.b); } - static void OpD4(void) // ANDB ZP { uint8_t m = READ_ZP; OP_AND_HANDLER(m, regs.d.acc.b); } - static void OpE4(void) // ANDB ZP, X { uint16_t m = READ_ZP_X; OP_AND_HANDLER(m, regs.d.acc.b); } - static void OpF4(void) // ANDB ABS { uint16_t m = READ_ABS; OP_AND_HANDLER(m, regs.d.acc.b); } - static void Op61(void) // AIM ZP, X (AND immediate with index) { uint8_t m; @@ -447,7 +406,6 @@ static void Op61(void) // AIM ZP, X (AND immediate with index) WRITE_BACK(m); } - static void Op71(void) // AIM ZP (AND immediate with zero page) { uint8_t m; @@ -457,7 +415,6 @@ static void Op71(void) // AIM ZP (AND immediate with zero page) WRITE_BACK(m); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -477,49 +434,42 @@ static void Op85(void) // BITA # OP_BIT_HANDLER(m, regs.d.acc.a); } - static void Op95(void) // BITA ZP { uint8_t m = READ_ZP; OP_BIT_HANDLER(m, regs.d.acc.a); } - static void OpA5(void) // BITA ZP, X { uint8_t m = READ_ZP_X; OP_BIT_HANDLER(m, regs.d.acc.a); } - static void OpB5(void) // BITA ABS { uint8_t m = READ_ABS; OP_BIT_HANDLER(m, regs.d.acc.a); } - static void OpC5(void) // BITB # { uint8_t m = READ_IMM; OP_BIT_HANDLER(m, regs.d.acc.b); } - static void OpD5(void) // BITB ZP { uint8_t m = READ_ZP; OP_BIT_HANDLER(m, regs.d.acc.b); } - static void OpE5(void) // BITB ZP, X { uint8_t m = READ_ZP_X; OP_BIT_HANDLER(m, regs.d.acc.b); } - static void OpF5(void) // BITB ABS { uint8_t m = READ_ABS; @@ -543,7 +493,6 @@ static void Op6F(void) // CLR ZP, X SET_Z(0); } - static void Op7F(void) // CLR ABS { regs.WrMem(EA_ABS, 0); @@ -551,7 +500,6 @@ static void Op7F(void) // CLR ABS SET_Z(0); } - static void Op4F(void) // CLRA { regs.d.acc.a = 0; @@ -559,7 +507,6 @@ static void Op4F(void) // CLRA SET_Z(0); } - static void Op5F(void) // CLRB { regs.d.acc.b = 0; @@ -591,56 +538,48 @@ static void Op81(void) // CMPA # OP_CMP_HANDLER(m, regs.d.acc.a); } - static void Op91(void) // CMPA ZP { uint8_t m = READ_ZP; OP_CMP_HANDLER(m, regs.d.acc.a); } - static void OpA1(void) // CMPA ZP, X { uint8_t m = READ_ZP_X; OP_CMP_HANDLER(m, regs.d.acc.a); } - static void OpB1(void) // CMPA ABS { uint8_t m = READ_ABS; OP_CMP_HANDLER(m, regs.d.acc.a); } - static void OpC1(void) // CMPB # { uint8_t m = READ_IMM; OP_CMP_HANDLER(m, regs.d.acc.b); } - static void OpD1(void) // CMPB ZP { uint8_t m = READ_ZP; OP_CMP_HANDLER(m, regs.d.acc.b); } - static void OpE1(void) // CMPB ZP, X { uint8_t m = READ_ZP_X; OP_CMP_HANDLER(m, regs.d.acc.b); } - static void OpF1(void) // CMPB ABS { uint8_t m = READ_ABS; OP_CMP_HANDLER(m, regs.d.acc.b); } - static void Op11(void) // CBA { OP_CMP_HANDLER(regs.d.acc.b, regs.d.acc.a); @@ -670,7 +609,6 @@ static void Op63(void) // COM ZP, X WRITE_BACK(m); } - static void Op73(void) // COM ABS { uint8_t m; @@ -679,13 +617,11 @@ static void Op73(void) // COM ABS WRITE_BACK(m); } - static void Op43(void) // COMA { OP_COM_HANDLER(regs.d.acc.a); } - static void Op53(void) // COMB { OP_COM_HANDLER(regs.d.acc.b); @@ -715,7 +651,6 @@ static void Op60(void) // NEG ZP, X WRITE_BACK(m); } - static void Op70(void) // NEG ABS { uint8_t m; @@ -724,13 +659,11 @@ static void Op70(void) // NEG ABS WRITE_BACK(m); } - static void Op40(void) // NEGA { OP_NEG_HANDLER(regs.d.acc.a); } - static void Op50(void) // NEGB { OP_NEG_HANDLER(regs.d.acc.b); @@ -781,7 +714,6 @@ static void Op6A(void) // DEC ZP, X WRITE_BACK(m); } - static void Op7A(void) // DEC ABS { uint8_t m; @@ -790,13 +722,11 @@ static void Op7A(void) // DEC ABS WRITE_BACK(m); } - static void Op4A(void) // DECA { OP_DEC_HANDLER(regs.d.acc.a); } - static void Op5A(void) // DECB { OP_DEC_HANDLER(regs.d.acc.b); @@ -822,56 +752,48 @@ static void Op88(void) // EORA # OP_EOR_HANDLER(m, regs.d.acc.a); } - static void Op98(void) // EORA ZP { uint8_t m = READ_ZP; OP_EOR_HANDLER(m, regs.d.acc.a); } - static void OpA8(void) // EORA ZP, X { uint8_t m = READ_ZP_X; OP_EOR_HANDLER(m, regs.d.acc.a); } - static void OpB8(void) // EORA ABS { uint8_t m = READ_ABS; OP_EOR_HANDLER(m, regs.d.acc.a); } - static void OpC8(void) // EORB # { uint8_t m = READ_IMM; OP_EOR_HANDLER(m, regs.d.acc.b); } - static void OpD8(void) // EORB ZP { uint8_t m = READ_ZP; OP_EOR_HANDLER(m, regs.d.acc.b); } - static void OpE8(void) // EORB ZP, X { uint8_t m = READ_ZP_X; OP_EOR_HANDLER(m, regs.d.acc.b); } - static void OpF8(void) // EORB ABS { uint8_t m = READ_ABS; OP_EOR_HANDLER(m, regs.d.acc.b); } - static void Op65(void) // EIM ZP, X (EOR immediate with index) { uint8_t m; @@ -881,7 +803,6 @@ static void Op65(void) // EIM ZP, X (EOR immediate with index) WRITE_BACK(m); } - static void Op75(void) // EIM ZP (EOR immediate with zero page) { uint8_t m; @@ -891,7 +812,6 @@ static void Op75(void) // EIM ZP (EOR immediate with zero page) WRITE_BACK(m); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -915,7 +835,6 @@ static void Op6C(void) // INC ZP, X WRITE_BACK(m); } - static void Op7C(void) // INC ABS { uint8_t m; @@ -924,13 +843,11 @@ static void Op7C(void) // INC ABS WRITE_BACK(m); } - static void Op4C(void) // INCA { OP_INC_HANDLER(regs.d.acc.a); } - static void Op5C(void) // INCB { OP_INC_HANDLER(regs.d.acc.b); @@ -956,56 +873,48 @@ static void Op86(void) // LDAA # OP_LDA_HANDLER(m, regs.d.acc.a); } - static void Op96(void) // LDAA ZP { uint8_t m = READ_ZP; OP_LDA_HANDLER(m, regs.d.acc.a); } - static void OpA6(void) // LDAA ZP, X { uint8_t m = READ_ZP_X; OP_LDA_HANDLER(m, regs.d.acc.a); } - static void OpB6(void) // LDAA ABS { uint8_t m = READ_ABS; OP_LDA_HANDLER(m, regs.d.acc.a); } - static void OpC6(void) // LDAB # { uint8_t m = READ_IMM; OP_LDA_HANDLER(m, regs.d.acc.b); } - static void OpD6(void) // LDAB ZP { uint8_t m = READ_ZP; OP_LDA_HANDLER(m, regs.d.acc.b); } - static void OpE6(void) // LDAB ZP, X { uint8_t m = READ_ZP_X; OP_LDA_HANDLER(m, regs.d.acc.b); } - static void OpF6(void) // LDAB ABS { uint8_t m = READ_ABS; OP_LDA_HANDLER(m, regs.d.acc.b); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1026,56 +935,48 @@ static void Op8A(void) // ORAA # OP_ORA_HANDLER(m, regs.d.acc.a); } - static void Op9A(void) // ORAA ZP { uint8_t m = READ_ZP; OP_ORA_HANDLER(m, regs.d.acc.a); } - static void OpAA(void) // ORAA ZP, X { uint8_t m = READ_ZP_X; OP_ORA_HANDLER(m, regs.d.acc.a); } - static void OpBA(void) // ORAA ABS { uint8_t m = READ_ABS; OP_ORA_HANDLER(m, regs.d.acc.a); } - static void OpCA(void) // ORAB # { uint8_t m = READ_IMM; OP_ORA_HANDLER(m, regs.d.acc.b); } - static void OpDA(void) // ORAB ZP { uint8_t m = READ_ZP; OP_ORA_HANDLER(m, regs.d.acc.b); } - static void OpEA(void) // ORAB ZP, X { uint8_t m = READ_ZP_X; OP_ORA_HANDLER(m, regs.d.acc.b); } - static void OpFA(void) // ORAB ABS { uint8_t m = READ_ABS; OP_ORA_HANDLER(m, regs.d.acc.b); } - static void Op62(void) // OIM ZP, X (ORA immediate with index) { uint8_t m; @@ -1085,7 +986,6 @@ static void Op62(void) // OIM ZP, X (ORA immediate with index) WRITE_BACK(m); } - static void Op72(void) // OIM ZP (ORA immediate with zero page) { uint8_t m; @@ -1095,7 +995,6 @@ static void Op72(void) // OIM ZP (ORA immediate with zero page) WRITE_BACK(m); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1110,37 +1009,31 @@ static void Op36(void) // PSHA PUSH(regs.d.acc.a); } - static void Op37(void) // PSHB { PUSH(regs.d.acc.b); } - static void Op32(void) // PULA { regs.d.acc.a = PULL; } - static void Op33(void) // PULB { regs.d.acc.b = PULL; } - static void Op38(void) // PULX { regs.x = PULL16; } - static void Op3C(void) // PSHX { PUSH16(regs.x); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1166,7 +1059,6 @@ static void Op69(void) // ROL ZP, X WRITE_BACK(m); } - static void Op79(void) // ROL ABS { uint8_t m; @@ -1175,13 +1067,11 @@ static void Op79(void) // ROL ABS WRITE_BACK(m); } - static void Op49(void) // ROLA { OP_ROL_HANDLER(regs.d.acc.a); } - static void Op59(void) // ROLB { OP_ROL_HANDLER(regs.d.acc.b); @@ -1212,7 +1102,6 @@ static void Op66(void) // ROR ZP, X WRITE_BACK(m); } - static void Op76(void) // ROR ABS { uint8_t m; @@ -1221,13 +1110,11 @@ static void Op76(void) // ROR ABS WRITE_BACK(m); } - static void Op46(void) // RORA { OP_ROR_HANDLER(regs.d.acc.a); } - static void Op56(void) // RORB { OP_ROR_HANDLER(regs.d.acc.b); @@ -1258,7 +1145,6 @@ static void Op68(void) // ASL ZP, X WRITE_BACK(m); } - static void Op78(void) // ASL ABS { uint8_t m; @@ -1267,19 +1153,16 @@ static void Op78(void) // ASL ABS WRITE_BACK(m); } - static void Op48(void) // ASLA { OP_ASL_HANDLER(regs.d.acc.a); } - static void Op58(void) // ASLB { OP_ASL_HANDLER(regs.d.acc.b); } - static void Op05(void) // ASLD { uint8_t newCarry = (regs.d.word & 0x8000) >> 15; @@ -1290,7 +1173,6 @@ static void Op05(void) // ASLD flagV = flagN ^ flagC; } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1316,7 +1198,6 @@ static void Op67(void) // ASR ZP, X WRITE_BACK(m); } - static void Op77(void) // ASR ABS { uint8_t m; @@ -1325,19 +1206,16 @@ static void Op77(void) // ASR ABS WRITE_BACK(m); } - static void Op47(void) // ASRA { OP_ASR_HANDLER(regs.d.acc.a); } - static void Op57(void) // ASRB { OP_ASR_HANDLER(regs.d.acc.b); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1363,7 +1241,6 @@ static void Op64(void) // LSR ZP, X WRITE_BACK(m); } - static void Op74(void) // LSR ABS { uint8_t m; @@ -1372,19 +1249,16 @@ static void Op74(void) // LSR ABS WRITE_BACK(m); } - static void Op44(void) // LSRA { OP_LSR_HANDLER(regs.d.acc.a); } - static void Op54(void) // LSRB { OP_LSR_HANDLER(regs.d.acc.b); } - static void Op04(void) // LSRD { uint8_t newCarry = regs.d.word & 0x01; @@ -1395,7 +1269,6 @@ static void Op04(void) // LSRD flagV = flagN ^ flagC; } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1408,37 +1281,31 @@ static void Op97(void) // STAA ZP regs.WrMem(EA_ZP, regs.d.acc.a); } - static void OpA7(void) // STAA ZP, X { regs.WrMem(EA_ZP_X, regs.d.acc.a); } - static void OpB7(void) // STAA ABS { regs.WrMem(EA_ABS, regs.d.acc.a); } - static void OpD7(void) // STAB ZP { regs.WrMem(EA_ZP, regs.d.acc.b); } - static void OpE7(void) // STAB ZP, X { regs.WrMem(EA_ZP_X, regs.d.acc.b); } - static void OpF7(void) // STAB ABS { regs.WrMem(EA_ABS, regs.d.acc.b); } - // These are illegal instructions! #if 0 static void Op87(void) // STA # @@ -1465,7 +1332,6 @@ static void OpC7(void) // STB # } #endif - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1497,90 +1363,77 @@ static void Op80(void) // SUBA # OP_SUB_HANDLER(m, regs.d.acc.a); } - static void Op90(void) // SUBA ZP { uint16_t m = READ_ZP; OP_SUB_HANDLER(m, regs.d.acc.a); } - static void OpA0(void) // SUBA ZP, X { uint16_t m = READ_ZP_X; OP_SUB_HANDLER(m, regs.d.acc.a); } - static void OpB0(void) // SUBA ABS { uint16_t m = READ_ABS; OP_SUB_HANDLER(m, regs.d.acc.a); } - static void OpC0(void) // SUBB # { uint16_t m = READ_IMM; OP_SUB_HANDLER(m, regs.d.acc.b); } - static void OpD0(void) // SUBB ZP { uint16_t m = READ_ZP; OP_SUB_HANDLER(m, regs.d.acc.b); } - static void OpE0(void) // SUBB ZP, X { uint16_t m = READ_ZP_X; OP_SUB_HANDLER(m, regs.d.acc.b); } - static void OpF0(void) // SUBB ABS { uint16_t m = READ_ABS; OP_SUB_HANDLER(m, regs.d.acc.b); } - static void Op10(void) // SBA { OP_SUB_HANDLER(regs.d.acc.b, regs.d.acc.a); } - static void Op83(void) // SUBD # { uint16_t m = READ_IMM16; OP_SUB_HANDLER16(m, regs.d.word); } - static void Op93(void) // SUBD ZP { uint16_t m = READ_ZP16; OP_SUB_HANDLER16(m, regs.d.word); } - static void OpA3(void) // SUBD ZP, X { uint16_t m = READ_ZP_X16; OP_SUB_HANDLER16(m, regs.d.word); } - static void OpB3(void) // SUBD ABS { uint16_t m = READ_ABS16; OP_SUB_HANDLER16(m, regs.d.word); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1603,49 +1456,42 @@ static void Op82(void) // SBCA # OP_SBC_HANDLER(m, regs.d.acc.a); } - static void Op92(void) // SBCA ZP { uint16_t m = READ_ZP; OP_SBC_HANDLER(m, regs.d.acc.a); } - static void OpA2(void) // SBCA ZP, X { uint16_t m = READ_ZP_X; OP_SBC_HANDLER(m, regs.d.acc.a); } - static void OpB2(void) // SBCA ABS { uint16_t m = READ_ABS; OP_SBC_HANDLER(m, regs.d.acc.a); } - static void OpC2(void) // SBCB # { uint16_t m = READ_IMM; OP_SBC_HANDLER(m, regs.d.acc.b); } - static void OpD2(void) // SBCB ZP { uint16_t m = READ_ZP; OP_SBC_HANDLER(m, regs.d.acc.b); } - static void OpE2(void) // SBCB ZP, X { uint16_t m = READ_ZP_X; OP_SBC_HANDLER(m, regs.d.acc.b); } - static void OpF2(void) // SBCB ABS { uint16_t m = READ_ABS; @@ -1666,7 +1512,6 @@ static void Op16(void) // TAB CLR_V; } - static void Op17(void) // TBA { regs.d.acc.a = regs.d.acc.b; @@ -1706,7 +1551,6 @@ static void Op6D(void) // TST ZP, X #endif } - static void Op7D(void) // TST ABS { #if 0 @@ -1719,19 +1563,16 @@ static void Op7D(void) // TST ABS #endif } - static void Op4D(void) // TSTA { OP_TST_HANDLER(regs.d.acc.a); } - static void Op5D(void) // TSTB { OP_TST_HANDLER(regs.d.acc.b); } - static void Op6B(void) // TIM ZP, X (TST immediate with index) { // uint8_t m; @@ -1741,7 +1582,6 @@ static void Op6B(void) // TIM ZP, X (TST immediate with index) // WRITE_BACK(m); } - static void Op7B(void) // TIM ZP (TST immediate with zero page) { // uint8_t m; @@ -1751,7 +1591,6 @@ static void Op7B(void) // TIM ZP (TST immediate with zero page) // WRITE_BACK(m); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1774,21 +1613,18 @@ static void Op8C(void) // CPX # OP_CPX_HANDLER(m); } - static void Op9C(void) // CPX ZP { uint16_t m = READ_ZP16; OP_CPX_HANDLER(m); } - static void OpAC(void) // CPX ZP, X { uint16_t m = READ_ZP_X16; OP_CPX_HANDLER(m); } - static void OpBC(void) // CPX ABS { uint16_t m = READ_ABS16; @@ -1810,20 +1646,17 @@ static void Op09(void) // DEX SET_Z(regs.x); } - static void Op34(void) // DES { regs.s--; } - static void Op08(void) // INX { regs.x++; SET_Z(regs.x); } - static void Op31(void) // INS { regs.s++; @@ -1849,84 +1682,72 @@ static void OpCE(void) // LDX # OP_LD_HANDLER(regs.x); } - static void OpDE(void) // LDX ZP { regs.x = READ_ZP16; OP_LD_HANDLER(regs.x); } - static void OpEE(void) // LDX ZP, X { regs.x = READ_ZP_X16; OP_LD_HANDLER(regs.x); } - static void OpFE(void) // LDX ABS { regs.x = READ_ABS16; OP_LD_HANDLER(regs.x); } - static void Op8E(void) // LDS # { regs.s = READ_IMM16; OP_LD_HANDLER(regs.s); } - static void Op9E(void) // LDS ZP { regs.s = READ_ZP16; OP_LD_HANDLER(regs.s); } - static void OpAE(void) // LDS ZP, X { regs.s = READ_ZP_X16; OP_LD_HANDLER(regs.s); } - static void OpBE(void) // LDS ABS { regs.s = READ_ABS16; OP_LD_HANDLER(regs.s); } - static void OpCC(void) // LDD # { regs.d.word = READ_IMM16; OP_LD_HANDLER(regs.d.word); } - static void OpDC(void) // LDD ZP { regs.d.word = READ_ZP16; OP_LD_HANDLER(regs.d.word); } - static void OpEC(void) // LDD ZP, X { regs.d.word = READ_ZP_X16; OP_LD_HANDLER(regs.d.word); } - static void OpFC(void) // LDD ABS { regs.d.word = READ_ABS16; OP_LD_HANDLER(regs.d.word); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -1949,42 +1770,36 @@ static void OpDF(void) // STX ZP OP_ST_HANDLER(m, regs.x); } - static void OpEF(void) // STX ZP, X { uint16_t m = EA_ZP_X; OP_ST_HANDLER(m, regs.x); } - static void OpFF(void) // STX ABS { uint16_t m = EA_ABS; OP_ST_HANDLER(m, regs.x); } - static void Op9F(void) // STS ZP { uint16_t m = EA_ZP; OP_ST_HANDLER(m, regs.s); } - static void OpAF(void) // STS ZP, X { uint16_t m = EA_ZP_X; OP_ST_HANDLER(m, regs.s); } - static void OpBF(void) // STS ABS { uint16_t m = EA_ABS; OP_ST_HANDLER(m, regs.s); } - // These are illegal instructions! #if 0 // Store immediate--nonsensical opcodes :-P @@ -1995,7 +1810,6 @@ static void Op8F(void) // STS # OP_ST_HANDLER(effectiveAddress, regs.s); } - static void OpCF(void) // STX # { uint16_t effectiveAddress = regs.pc; @@ -2003,7 +1817,6 @@ static void OpCF(void) // STX # OP_ST_HANDLER(effectiveAddress, regs.x); } - static void OpCD(void) // STD # { uint16_t effectiveAddress = regs.pc; @@ -2012,28 +1825,24 @@ static void OpCD(void) // STD # } #endif - static void OpDD(void) // STD ZP { uint16_t m = EA_ZP; OP_ST_HANDLER(m, regs.d.word); } - static void OpED(void) // STD ZP, X { uint16_t m = EA_ZP_X; OP_ST_HANDLER(m, regs.d.word); } - static void OpFD(void) // STD ABS { uint16_t m = EA_ABS; OP_ST_HANDLER(m, regs.d.word); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -2046,7 +1855,6 @@ static void Op35(void) // TXS regs.s = regs.x - 1; } - static void Op30(void) // TSX { regs.x = regs.s + 1; @@ -2078,14 +1886,12 @@ static void Op20(void) // BRA regs.pc += m; } - static void Op21(void) // BRN { int16_t m = (int16_t)(int8_t)READ_IMM; // regs.pc += m; } - static void Op24(void) // BCC { // NOTE: We can optimize this by following the maxim: "Don't branch!" by @@ -2103,7 +1909,6 @@ static void Op24(void) // BCC #endif } - static void Op25(void) // BCS { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2116,7 +1921,6 @@ static void Op25(void) // BCS #endif } - static void Op27(void) // BEQ { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2129,7 +1933,6 @@ static void Op27(void) // BEQ #endif } - static void Op2C(void) // BGE { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2142,7 +1945,6 @@ static void Op2C(void) // BGE #endif } - static void Op2E(void) // BGT { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2155,7 +1957,6 @@ static void Op2E(void) // BGT #endif } - static void Op22(void) // BHI { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2168,7 +1969,6 @@ static void Op22(void) // BHI #endif } - static void Op2F(void) // BLE { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2181,7 +1981,6 @@ static void Op2F(void) // BLE #endif } - static void Op23(void) // BLS { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2194,7 +1993,6 @@ static void Op23(void) // BLS #endif } - static void Op2D(void) // BLT { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2207,7 +2005,6 @@ static void Op2D(void) // BLT #endif } - static void Op2B(void) // BMI { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2220,7 +2017,6 @@ static void Op2B(void) // BMI #endif } - static void Op26(void) // BNE { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2233,7 +2029,6 @@ static void Op26(void) // BNE #endif } - static void Op28(void) // BVC { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2246,7 +2041,6 @@ static void Op28(void) // BVC #endif } - static void Op29(void) // BVS { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2259,7 +2053,6 @@ static void Op29(void) // BVS #endif } - static void Op2A(void) // BPL { int16_t m = (int16_t)(int8_t)READ_IMM; @@ -2287,20 +2080,17 @@ static void Op8D(void) // BSR regs.pc += m; } - static void Op6E(void) // JMP ZP, X { uint16_t m = EA_ZP_X; regs.pc = m; } - static void Op7E(void) // JMP ABS { regs.pc = EA_ABS; } - static void Op9D(void) // JSR ZP { uint16_t m = (uint16_t)EA_ZP; @@ -2308,7 +2098,6 @@ static void Op9D(void) // JSR ZP regs.pc = m; } - static void OpAD(void) // JSR ZP, X { uint16_t m = EA_ZP_X; @@ -2316,7 +2105,6 @@ static void OpAD(void) // JSR ZP, X regs.pc = m; } - static void OpBD(void) // JSR ABS { uint16_t m = EA_ABS; @@ -2324,7 +2112,6 @@ static void OpBD(void) // JSR ABS regs.pc = m; } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -2339,7 +2126,6 @@ static void Op01(void) // NOP { } - static void Op3B(void) // RTI { regs.cc = PULL; @@ -2350,13 +2136,11 @@ static void Op3B(void) // RTI UNPACK_FLAGS; } - static void Op39(void) // RTS { regs.pc = PULL16; } - static void Op3F(void) // SWI { // It seems that the SWI is non-maskable, unlike the IRQ... @@ -2373,7 +2157,6 @@ static void Op3F(void) // SWI HandleInterrupt(0xFFFA); } - static void Op3E(void) // WAI { #ifdef __DEBUG__ @@ -2388,7 +2171,6 @@ WriteLog("*** WAI STATE ASSERTED ***\n"); regs.cpuFlags |= V63701_STATE_WAI; // And signal that we're in WAI mode } - // Multiply opcode static void Op3D(void) // MUL @@ -2397,7 +2179,6 @@ static void Op3D(void) // MUL flagC = regs.d.acc.b >> 7; // bug? No, this is how it really does it } - // Exchange X and D opcode static void Op18(void) // XGDX @@ -2408,7 +2189,6 @@ static void Op18(void) // XGDX regs.d.word = temp; } - // Sleep opcode (similar to WAI) static void Op1A(void) // SLP @@ -2421,7 +2201,6 @@ static void Op1A(void) // SLP regs.cpuFlags |= V63701_STATE_WAI; } - // Undocumented opcode ($12 & $13) static void OpUN(void) // Undocumented @@ -2429,7 +2208,6 @@ static void OpUN(void) // Undocumented regs.x += regs.RdMem(regs.s + 1); } - /* Operation |Mnem.|Immed.|Direct|Index |Extend|Inher.|Operation |CC Reg| | |OP ~ #|OP ~ #|OP ~ #|OP ~ #|OP ~ #| |HINZVC| @@ -2448,50 +2226,42 @@ static void Op0C(void) // CLC flagC = 0; } - static void Op0E(void) // CLI { flagI = 0; } - static void Op0A(void) // CLV { flagV = 0; } - static void Op0D(void) // SEC { flagC = 1; } - static void Op0F(void) // SEI { flagI = 1; } - static void Op0B(void) // SEV { flagV = 1; } - static void Op06(void) // TAP { regs.cc = regs.d.acc.a; UNPACK_FLAGS; } - static void Op07(void) // TPA { regs.d.acc.a = PACK_FLAGS; } - /* OP Operation Code, in Hexadecimal ~ Number of MPU cycles required @@ -2548,7 +2318,6 @@ static void Op07(void) // TPA 4: M=Xh, M+1=Xl */ - static void Op__(void) { // TRAP is non-maskable, unlike the IRQ... Also, highest priority after @@ -2557,7 +2326,6 @@ static void Op__(void) // regs.cpuFlags |= V63701_STATE_ILLEGAL_INST; } - // // Ok, the exec_op[] array is globally defined here basically to save // a LOT of unnecessary typing. Sure it's ugly, but hey, it works! @@ -2581,7 +2349,6 @@ static void (* exec_op[256])() = { OpF0, OpF1, OpF2, OpF3, OpF4, OpF5, OpF6, OpF7, OpF8, OpF9, OpFA, OpFB, OpFC, OpFD, OpFE, OpFF }; - // // Internal "memcpy" (so we don't have to link with any external libraries!) // @@ -2593,7 +2360,6 @@ static void myMemcpy(void * dst, void * src, uint32_t size) d[i] = s[i]; } - #ifdef __DEBUG__ //int instCount[256]; bool V63701LogGo = false; @@ -2640,7 +2406,7 @@ if (V63701LogGo) if (regs.cpuFlags & V63701_STATE_WAI) { // Only bail out if no interrupts/resets are pending - if (!(regs.cpuFlags & (V63701_ASSERT_LINE_IRQ | V63701_ASSERT_LINE_NMI | V63701_ASSERT_LINE_RESET | V63701_ASSERT_TIMER_OVERFLOW | V63701_ASSERT_OUTPUT_COMPARE | V63701_ASSERT_INPUT_CAPTURE))) + if (!(regs.cpuFlags & (V63701_LINE_IRQ | V63701_LINE_NMI | V63701_LINE_RESET | V63701_TIMER_OVERFLOW | V63701_OUTPUT_COMPARE | V63701_INPUT_CAPTURE))) // Burn any remaining cycles... regs.clock = endCycles; } @@ -2668,8 +2434,8 @@ if (V63701LogGo) if (regs.tcsr.bit.eoci) { - regs.cpuFlags |= V63701_ASSERT_OUTPUT_COMPARE; - regsPointer->cpuFlags |= V63701_ASSERT_OUTPUT_COMPARE; + regs.cpuFlags |= V63701_OUTPUT_COMPARE; + regsPointer->cpuFlags |= V63701_OUTPUT_COMPARE; } } @@ -2681,8 +2447,8 @@ if (V63701LogGo) if (regs.tcsr.bit.etoi) { - regs.cpuFlags |= V63701_ASSERT_TIMER_OVERFLOW; - regsPointer->cpuFlags |= V63701_ASSERT_TIMER_OVERFLOW; + regs.cpuFlags |= V63701_TIMER_OVERFLOW; + regsPointer->cpuFlags |= V63701_TIMER_OVERFLOW; } } #ifdef __DEBUG__ @@ -2692,7 +2458,7 @@ if (V63701LogGo) #endif } - if (regs.cpuFlags & V63701_ASSERT_LINE_RESET) + if (regs.cpuFlags & V63701_LINE_RESET) { #ifdef __DEBUG__ if (V63701LogGo) @@ -2707,15 +2473,15 @@ if (V63701LogGo) context->cpuFlags = 0; // Clear all lingering flags... regs.cpuFlags = 0; } - else if (regs.cpuFlags & V63701_ASSERT_LINE_NMI) + else if (regs.cpuFlags & V63701_LINE_NMI) { #ifdef __DEBUG__ if (V63701LogGo) WriteLog("*** NMI LINE ASSERTED ***\n"); #endif - HandleInterrupt(0xFFFC, V63701_ASSERT_LINE_NMI); + HandleInterrupt(0xFFFC, V63701_LINE_NMI); } - else if (regs.cpuFlags & V63701_ASSERT_LINE_IRQ) + else if (regs.cpuFlags & V63701_LINE_IRQ) { #ifdef __DEBUG__ if (V63701LogGo) @@ -2729,10 +2495,10 @@ if (V63701LogGo) WriteLog(" IRQ TAKEN!\n"); //V63701LogGo = true; #endif - HandleInterrupt(0xFFF8, V63701_ASSERT_LINE_IRQ); + HandleInterrupt(0xFFF8, V63701_LINE_IRQ); } } - else if (regs.cpuFlags & V63701_ASSERT_INPUT_CAPTURE) + else if (regs.cpuFlags & V63701_INPUT_CAPTURE) { #ifdef __DEBUG__ if (V63701LogGo) @@ -2746,10 +2512,10 @@ if (V63701LogGo) WriteLog(" IC TAKEN!\n"); //V63701LogGo = true; #endif - HandleInterrupt(0xFFF6, V63701_ASSERT_INPUT_CAPTURE); + HandleInterrupt(0xFFF6, V63701_INPUT_CAPTURE); } } - else if (regs.cpuFlags & V63701_ASSERT_OUTPUT_COMPARE) + else if (regs.cpuFlags & V63701_OUTPUT_COMPARE) { #ifdef __DEBUG__ if (V63701LogGo) @@ -2763,10 +2529,10 @@ if (V63701LogGo) WriteLog(" OC TAKEN!\n"); //V63701LogGo = true; #endif - HandleInterrupt(0xFFF4, V63701_ASSERT_OUTPUT_COMPARE); + HandleInterrupt(0xFFF4, V63701_OUTPUT_COMPARE); } } - else if (regs.cpuFlags & V63701_ASSERT_TIMER_OVERFLOW) + else if (regs.cpuFlags & V63701_TIMER_OVERFLOW) { #ifdef __DEBUG__ if (V63701LogGo) @@ -2780,7 +2546,7 @@ if (V63701LogGo) WriteLog(" TO TAKEN!\n"); //V63701LogGo = true; #endif - HandleInterrupt(0xFFF2, V63701_ASSERT_TIMER_OVERFLOW); + HandleInterrupt(0xFFF2, V63701_TIMER_OVERFLOW); } } } @@ -2795,7 +2561,6 @@ if (V63701LogGo) myMemcpy(context, ®s, sizeof(V63701REGS)); } - // // Get the clock of the currently executing CPU // @@ -2804,7 +2569,6 @@ uint64_t GetCurrentV63701Clock(void) return regs.clock; } - static inline void HandleInterrupt(uint16_t vector, uint16_t flag/*= 0*/) { if (regs.cpuFlags & V63701_STATE_WAI) @@ -2828,7 +2592,6 @@ static inline void HandleInterrupt(uint16_t vector, uint16_t flag/*= 0*/) regsPointer->cpuFlags &= ~(flag | V63701_STATE_WAI); } - uint8_t InternalRegisterRead(uint16_t address) { switch (address & 0x1F) @@ -2881,7 +2644,6 @@ uint8_t InternalRegisterRead(uint16_t address) return 0x00; } - void InternalRegisterWrite(uint16_t address, uint8_t data) { uint8_t writeData; @@ -2952,4 +2714,3 @@ void InternalRegisterWrite(uint16_t address, uint8_t data) #endif } } -