X-Git-Url: http://shamusworld.gotdns.org/cgi-bin/gitweb.cgi?a=blobdiff_plain;f=src%2Fgpu.h;h=47ec01252a6e870a8ab061e5fe9b1bbb695bdfb4;hb=10d7ab1fb217c01030a0b637f9a571c1faf61ede;hp=1b83d74c2e7eea137aa398731eb3c84531639812;hpb=2ae315f25e623cc8279d3c9012a3a166d86684c2;p=virtualjaguar

diff --git a/src/gpu.h b/src/gpu.h
index 1b83d74..47ec012 100644
--- a/src/gpu.h
+++ b/src/gpu.h
@@ -5,33 +5,38 @@
 #ifndef __GPU_H__
 #define __GPU_H__
 
-#include "jaguar.h"
+//#include "types.h"
+#include "memory.h"
 
 #define GPU_CONTROL_RAM_BASE    0x00F02100
 #define GPU_WORK_RAM_BASE		0x00F03000
 
-void gpu_init(void);
-void gpu_reset(void);
-void gpu_exec(int32);
-void gpu_done(void);
-void gpu_update_register_banks(void);
+void GPUInit(void);
+void GPUReset(void);
+void GPUExec(int32_t);
+void GPUDone(void);
+void GPUUpdateRegisterBanks(void);
 void GPUHandleIRQs(void);
 void GPUSetIRQLine(int irqline, int state);
 
-uint8 GPUReadByte(uint32 offset, uint32 who = UNKNOWN);
-uint16 GPUReadWord(uint32 offset, uint32 who = UNKNOWN);
-uint32 GPUReadLong(uint32 offset, uint32 who = UNKNOWN);
-void GPUWriteByte(uint32 offset, uint8 data, uint32 who = UNKNOWN);
-void GPUWriteWord(uint32 offset, uint16 data, uint32 who = UNKNOWN);
-void GPUWriteLong(uint32 offset, uint32 data, uint32 who = UNKNOWN);
+uint8_t GPUReadByte(uint32_t offset, uint32_t who = UNKNOWN);
+uint16_t GPUReadWord(uint32_t offset, uint32_t who = UNKNOWN);
+uint32_t GPUReadLong(uint32_t offset, uint32_t who = UNKNOWN);
+void GPUWriteByte(uint32_t offset, uint8_t data, uint32_t who = UNKNOWN);
+void GPUWriteWord(uint32_t offset, uint16_t data, uint32_t who = UNKNOWN);
+void GPUWriteLong(uint32_t offset, uint32_t data, uint32_t who = UNKNOWN);
 
-uint32 gpu_get_pc(void);
-void gpu_releaseTimeslice(void);
-void gpu_reset_stats(void);
-uint32 gpu_read_pc(void);
+uint32_t GPUGetPC(void);
+void GPUReleaseTimeslice(void);
+void GPUResetStats(void);
+uint32_t GPUReadPC(void);
 
 // GPU interrupt numbers (from $F00100, bits 4-8)
 
 enum { GPUIRQ_CPU = 0, GPUIRQ_DSP, GPUIRQ_TIMER, GPUIRQ_OBJECT, GPUIRQ_BLITTER };
 
+// Exported vars
+
+extern uint32_t gpu_reg_bank_0[], gpu_reg_bank_1[];
+
 #endif	// __GPU_H__